1a69d2774SRui Miguel Silva// SPDX-License-Identifier: GPL-2.0 or MIT 2a69d2774SRui Miguel Silva/* 3a69d2774SRui Miguel Silva * Copyright (c) 2022, Arm Limited. All rights reserved. 4a69d2774SRui Miguel Silva * Copyright (c) 2022, Linaro Limited. All rights reserved. 5a69d2774SRui Miguel Silva * 6a69d2774SRui Miguel Silva */ 7a69d2774SRui Miguel Silva 8a69d2774SRui Miguel Silva#include <dt-bindings/interrupt-controller/arm-gic.h> 9a69d2774SRui Miguel Silva 10a69d2774SRui Miguel Silva/ { 11a69d2774SRui Miguel Silva interrupt-parent = <&gic>; 12a69d2774SRui Miguel Silva #address-cells = <1>; 13a69d2774SRui Miguel Silva #size-cells = <1>; 14a69d2774SRui Miguel Silva 15a69d2774SRui Miguel Silva aliases { 16a69d2774SRui Miguel Silva serial0 = &uart0; 17a69d2774SRui Miguel Silva serial1 = &uart1; 18a69d2774SRui Miguel Silva }; 19a69d2774SRui Miguel Silva 20a69d2774SRui Miguel Silva chosen { 21a69d2774SRui Miguel Silva stdout-path = "serial0:115200n8"; 22a69d2774SRui Miguel Silva }; 23a69d2774SRui Miguel Silva 24a69d2774SRui Miguel Silva cpus { 25a69d2774SRui Miguel Silva #address-cells = <1>; 26a69d2774SRui Miguel Silva #size-cells = <0>; 27a69d2774SRui Miguel Silva 28a69d2774SRui Miguel Silva cpu: cpu@0 { 29a69d2774SRui Miguel Silva device_type = "cpu"; 30a69d2774SRui Miguel Silva compatible = "arm,cortex-a35"; 31a69d2774SRui Miguel Silva reg = <0>; 32a69d2774SRui Miguel Silva next-level-cache = <&L2_0>; 33a69d2774SRui Miguel Silva }; 34a69d2774SRui Miguel Silva }; 35a69d2774SRui Miguel Silva 36a69d2774SRui Miguel Silva memory@88200000 { 37a69d2774SRui Miguel Silva device_type = "memory"; 38a69d2774SRui Miguel Silva reg = <0x88200000 0x77e00000>; 39a69d2774SRui Miguel Silva }; 40a69d2774SRui Miguel Silva 41a69d2774SRui Miguel Silva gic: interrupt-controller@1c000000 { 42a69d2774SRui Miguel Silva compatible = "arm,gic-400"; 43a69d2774SRui Miguel Silva #interrupt-cells = <3>; 44a69d2774SRui Miguel Silva #address-cells = <0>; 45a69d2774SRui Miguel Silva interrupt-controller; 46a69d2774SRui Miguel Silva reg = <0x1c010000 0x1000>, 47a69d2774SRui Miguel Silva <0x1c02f000 0x2000>, 48a69d2774SRui Miguel Silva <0x1c04f000 0x1000>, 49a69d2774SRui Miguel Silva <0x1c06f000 0x2000>; 50a69d2774SRui Miguel Silva interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | 51a69d2774SRui Miguel Silva IRQ_TYPE_LEVEL_LOW)>; 52a69d2774SRui Miguel Silva }; 53a69d2774SRui Miguel Silva 54a69d2774SRui Miguel Silva L2_0: l2-cache0 { 55a69d2774SRui Miguel Silva compatible = "cache"; 56*59fb813fSPierre Gondois cache-unified; 57a69d2774SRui Miguel Silva cache-level = <2>; 58a69d2774SRui Miguel Silva cache-size = <0x80000>; 59a69d2774SRui Miguel Silva cache-line-size = <64>; 60a69d2774SRui Miguel Silva cache-sets = <1024>; 61a69d2774SRui Miguel Silva }; 62a69d2774SRui Miguel Silva 63a69d2774SRui Miguel Silva refclk100mhz: refclk100mhz { 64a69d2774SRui Miguel Silva compatible = "fixed-clock"; 65a69d2774SRui Miguel Silva #clock-cells = <0>; 66a69d2774SRui Miguel Silva clock-frequency = <100000000>; 67a69d2774SRui Miguel Silva clock-output-names = "apb_pclk"; 68a69d2774SRui Miguel Silva }; 69a69d2774SRui Miguel Silva 70a69d2774SRui Miguel Silva smbclk: refclk24mhzx2 { 71a69d2774SRui Miguel Silva /* Reference 24MHz clock x 2 */ 72a69d2774SRui Miguel Silva compatible = "fixed-clock"; 73a69d2774SRui Miguel Silva #clock-cells = <0>; 74a69d2774SRui Miguel Silva clock-frequency = <48000000>; 75a69d2774SRui Miguel Silva clock-output-names = "smclk"; 76a69d2774SRui Miguel Silva }; 77a69d2774SRui Miguel Silva 78a69d2774SRui Miguel Silva timer { 79a69d2774SRui Miguel Silva compatible = "arm,armv8-timer"; 80a69d2774SRui Miguel Silva interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | 81a69d2774SRui Miguel Silva IRQ_TYPE_LEVEL_LOW)>, 82a69d2774SRui Miguel Silva <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | 83a69d2774SRui Miguel Silva IRQ_TYPE_LEVEL_LOW)>, 84a69d2774SRui Miguel Silva <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | 85a69d2774SRui Miguel Silva IRQ_TYPE_LEVEL_LOW)>, 86a69d2774SRui Miguel Silva <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | 87a69d2774SRui Miguel Silva IRQ_TYPE_LEVEL_LOW)>; 88a69d2774SRui Miguel Silva }; 89a69d2774SRui Miguel Silva 90a69d2774SRui Miguel Silva uartclk: uartclk { 91a69d2774SRui Miguel Silva /* UART clock - 50MHz */ 92a69d2774SRui Miguel Silva compatible = "fixed-clock"; 93a69d2774SRui Miguel Silva #clock-cells = <0>; 94a69d2774SRui Miguel Silva clock-frequency = <50000000>; 95a69d2774SRui Miguel Silva clock-output-names = "uartclk"; 96a69d2774SRui Miguel Silva }; 97a69d2774SRui Miguel Silva 98a69d2774SRui Miguel Silva psci { 99a69d2774SRui Miguel Silva compatible = "arm,psci-1.0", "arm,psci-0.2"; 100a69d2774SRui Miguel Silva method = "smc"; 101a69d2774SRui Miguel Silva }; 102a69d2774SRui Miguel Silva 103a69d2774SRui Miguel Silva soc { 104a69d2774SRui Miguel Silva compatible = "simple-bus"; 105a69d2774SRui Miguel Silva #address-cells = <1>; 106a69d2774SRui Miguel Silva #size-cells = <1>; 107a69d2774SRui Miguel Silva interrupt-parent = <&gic>; 108a69d2774SRui Miguel Silva ranges; 109a69d2774SRui Miguel Silva 110a69d2774SRui Miguel Silva timer@1a220000 { 111a69d2774SRui Miguel Silva compatible = "arm,armv7-timer-mem"; 112a69d2774SRui Miguel Silva reg = <0x1a220000 0x1000>; 113a69d2774SRui Miguel Silva #address-cells = <1>; 114a69d2774SRui Miguel Silva #size-cells = <1>; 115a69d2774SRui Miguel Silva clock-frequency = <50000000>; 116a69d2774SRui Miguel Silva ranges; 117a69d2774SRui Miguel Silva 118a69d2774SRui Miguel Silva frame@1a230000 { 119a69d2774SRui Miguel Silva frame-number = <0>; 120a69d2774SRui Miguel Silva interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 121a69d2774SRui Miguel Silva reg = <0x1a230000 0x1000>; 122a69d2774SRui Miguel Silva }; 123a69d2774SRui Miguel Silva }; 124a69d2774SRui Miguel Silva 125a69d2774SRui Miguel Silva uart0: serial@1a510000 { 126a69d2774SRui Miguel Silva compatible = "arm,pl011", "arm,primecell"; 127a69d2774SRui Miguel Silva reg = <0x1a510000 0x1000>; 128a69d2774SRui Miguel Silva interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 129a69d2774SRui Miguel Silva clocks = <&uartclk>, <&refclk100mhz>; 130a69d2774SRui Miguel Silva clock-names = "uartclk", "apb_pclk"; 131a69d2774SRui Miguel Silva }; 132a69d2774SRui Miguel Silva 133a69d2774SRui Miguel Silva uart1: serial@1a520000 { 134a69d2774SRui Miguel Silva compatible = "arm,pl011", "arm,primecell"; 135a69d2774SRui Miguel Silva reg = <0x1a520000 0x1000>; 136a69d2774SRui Miguel Silva interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 137a69d2774SRui Miguel Silva clocks = <&uartclk>, <&refclk100mhz>; 138a69d2774SRui Miguel Silva clock-names = "uartclk", "apb_pclk"; 139a69d2774SRui Miguel Silva }; 140a69d2774SRui Miguel Silva 141a69d2774SRui Miguel Silva mhu_hse1: mailbox@1b820000 { 142a69d2774SRui Miguel Silva compatible = "arm,mhuv2-tx", "arm,primecell"; 143a69d2774SRui Miguel Silva reg = <0x1b820000 0x1000>; 144a69d2774SRui Miguel Silva clocks = <&refclk100mhz>; 145a69d2774SRui Miguel Silva clock-names = "apb_pclk"; 146a69d2774SRui Miguel Silva interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 147a69d2774SRui Miguel Silva #mbox-cells = <2>; 148a69d2774SRui Miguel Silva arm,mhuv2-protocols = <0 0>; 149a69d2774SRui Miguel Silva secure-status = "okay"; /* secure-world-only */ 150a69d2774SRui Miguel Silva status = "disabled"; 151a69d2774SRui Miguel Silva }; 152a69d2774SRui Miguel Silva 153a69d2774SRui Miguel Silva mhu_seh1: mailbox@1b830000 { 154a69d2774SRui Miguel Silva compatible = "arm,mhuv2-rx", "arm,primecell"; 155a69d2774SRui Miguel Silva reg = <0x1b830000 0x1000>; 156a69d2774SRui Miguel Silva clocks = <&refclk100mhz>; 157a69d2774SRui Miguel Silva clock-names = "apb_pclk"; 158a69d2774SRui Miguel Silva interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 159a69d2774SRui Miguel Silva #mbox-cells = <2>; 160a69d2774SRui Miguel Silva arm,mhuv2-protocols = <0 0>; 161a69d2774SRui Miguel Silva secure-status = "okay"; /* secure-world-only */ 162a69d2774SRui Miguel Silva status = "disabled"; 163a69d2774SRui Miguel Silva }; 164a69d2774SRui Miguel Silva }; 165a69d2774SRui Miguel Silva}; 166