1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/interrupt-controller/apple-aic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/pinctrl/apple.h> 13 14/ { 15 compatible = "apple,t8103", "apple,arm-platform"; 16 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <2>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "apple,icestorm"; 26 device_type = "cpu"; 27 reg = <0x0 0x0>; 28 enable-method = "spin-table"; 29 cpu-release-addr = <0 0>; /* To be filled by loader */ 30 }; 31 32 cpu1: cpu@1 { 33 compatible = "apple,icestorm"; 34 device_type = "cpu"; 35 reg = <0x0 0x1>; 36 enable-method = "spin-table"; 37 cpu-release-addr = <0 0>; /* To be filled by loader */ 38 }; 39 40 cpu2: cpu@2 { 41 compatible = "apple,icestorm"; 42 device_type = "cpu"; 43 reg = <0x0 0x2>; 44 enable-method = "spin-table"; 45 cpu-release-addr = <0 0>; /* To be filled by loader */ 46 }; 47 48 cpu3: cpu@3 { 49 compatible = "apple,icestorm"; 50 device_type = "cpu"; 51 reg = <0x0 0x3>; 52 enable-method = "spin-table"; 53 cpu-release-addr = <0 0>; /* To be filled by loader */ 54 }; 55 56 cpu4: cpu@10100 { 57 compatible = "apple,firestorm"; 58 device_type = "cpu"; 59 reg = <0x0 0x10100>; 60 enable-method = "spin-table"; 61 cpu-release-addr = <0 0>; /* To be filled by loader */ 62 }; 63 64 cpu5: cpu@10101 { 65 compatible = "apple,firestorm"; 66 device_type = "cpu"; 67 reg = <0x0 0x10101>; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0 0>; /* To be filled by loader */ 70 }; 71 72 cpu6: cpu@10102 { 73 compatible = "apple,firestorm"; 74 device_type = "cpu"; 75 reg = <0x0 0x10102>; 76 enable-method = "spin-table"; 77 cpu-release-addr = <0 0>; /* To be filled by loader */ 78 }; 79 80 cpu7: cpu@10103 { 81 compatible = "apple,firestorm"; 82 device_type = "cpu"; 83 reg = <0x0 0x10103>; 84 enable-method = "spin-table"; 85 cpu-release-addr = <0 0>; /* To be filled by loader */ 86 }; 87 }; 88 89 timer { 90 compatible = "arm,armv8-timer"; 91 interrupt-parent = <&aic>; 92 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 93 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 94 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 95 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 96 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 97 }; 98 99 clk24: clock-24m { 100 compatible = "fixed-clock"; 101 #clock-cells = <0>; 102 clock-frequency = <24000000>; 103 clock-output-names = "clk24"; 104 }; 105 106 soc { 107 compatible = "simple-bus"; 108 #address-cells = <2>; 109 #size-cells = <2>; 110 111 ranges; 112 nonposted-mmio; 113 114 serial0: serial@235200000 { 115 compatible = "apple,s5l-uart"; 116 reg = <0x2 0x35200000 0x0 0x1000>; 117 reg-io-width = <4>; 118 interrupt-parent = <&aic>; 119 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 120 /* 121 * TODO: figure out the clocking properly, there may 122 * be a third selectable clock. 123 */ 124 clocks = <&clk24>, <&clk24>; 125 clock-names = "uart", "clk_uart_baud0"; 126 status = "disabled"; 127 }; 128 129 aic: interrupt-controller@23b100000 { 130 compatible = "apple,t8103-aic", "apple,aic"; 131 #interrupt-cells = <3>; 132 interrupt-controller; 133 reg = <0x2 0x3b100000 0x0 0x8000>; 134 }; 135 136 pinctrl_ap: pinctrl@23c100000 { 137 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 138 reg = <0x2 0x3c100000 0x0 0x100000>; 139 140 gpio-controller; 141 #gpio-cells = <2>; 142 gpio-ranges = <&pinctrl_ap 0 0 212>; 143 apple,npins = <212>; 144 145 interrupt-controller; 146 interrupt-parent = <&aic>; 147 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 148 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 149 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 150 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 151 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 152 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 153 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 154 155 pcie_pins: pcie-pins { 156 pinmux = <APPLE_PINMUX(150, 1)>, 157 <APPLE_PINMUX(151, 1)>, 158 <APPLE_PINMUX(32, 1)>; 159 }; 160 }; 161 162 pinctrl_aop: pinctrl@24a820000 { 163 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 164 reg = <0x2 0x4a820000 0x0 0x4000>; 165 166 gpio-controller; 167 #gpio-cells = <2>; 168 gpio-ranges = <&pinctrl_aop 0 0 42>; 169 apple,npins = <42>; 170 171 interrupt-controller; 172 interrupt-parent = <&aic>; 173 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 174 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 175 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 176 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 177 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 178 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 179 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 180 }; 181 182 pinctrl_nub: pinctrl@23d1f0000 { 183 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 184 reg = <0x2 0x3d1f0000 0x0 0x4000>; 185 186 gpio-controller; 187 #gpio-cells = <2>; 188 gpio-ranges = <&pinctrl_nub 0 0 23>; 189 apple,npins = <23>; 190 191 interrupt-controller; 192 interrupt-parent = <&aic>; 193 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 194 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 195 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 196 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 197 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 198 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 199 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 200 }; 201 202 pinctrl_smc: pinctrl@23e820000 { 203 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 204 reg = <0x2 0x3e820000 0x0 0x4000>; 205 206 gpio-controller; 207 #gpio-cells = <2>; 208 gpio-ranges = <&pinctrl_smc 0 0 16>; 209 apple,npins = <16>; 210 211 interrupt-controller; 212 interrupt-parent = <&aic>; 213 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 214 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 215 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 216 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 217 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 218 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 219 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 220 }; 221 222 pcie0_dart_0: dart@681008000 { 223 compatible = "apple,t8103-dart"; 224 reg = <0x6 0x81008000 0x0 0x4000>; 225 #iommu-cells = <1>; 226 interrupt-parent = <&aic>; 227 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 228 }; 229 230 pcie0_dart_1: dart@682008000 { 231 compatible = "apple,t8103-dart"; 232 reg = <0x6 0x82008000 0x0 0x4000>; 233 #iommu-cells = <1>; 234 interrupt-parent = <&aic>; 235 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 236 }; 237 238 pcie0_dart_2: dart@683008000 { 239 compatible = "apple,t8103-dart"; 240 reg = <0x6 0x83008000 0x0 0x4000>; 241 #iommu-cells = <1>; 242 interrupt-parent = <&aic>; 243 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 244 }; 245 246 pcie0: pcie@690000000 { 247 compatible = "apple,t8103-pcie", "apple,pcie"; 248 device_type = "pci"; 249 250 reg = <0x6 0x90000000 0x0 0x1000000>, 251 <0x6 0x80000000 0x0 0x100000>, 252 <0x6 0x81000000 0x0 0x4000>, 253 <0x6 0x82000000 0x0 0x4000>, 254 <0x6 0x83000000 0x0 0x4000>; 255 reg-names = "config", "rc", "port0", "port1", "port2"; 256 257 interrupt-parent = <&aic>; 258 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 259 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 260 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 261 262 msi-controller; 263 msi-parent = <&pcie0>; 264 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 265 266 267 iommu-map = <0x100 &pcie0_dart_0 1 1>, 268 <0x200 &pcie0_dart_1 1 1>, 269 <0x300 &pcie0_dart_2 1 1>; 270 iommu-map-mask = <0xff00>; 271 272 bus-range = <0 3>; 273 #address-cells = <3>; 274 #size-cells = <2>; 275 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 276 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 277 278 pinctrl-0 = <&pcie_pins>; 279 pinctrl-names = "default"; 280 281 port00: pci@0,0 { 282 device_type = "pci"; 283 reg = <0x0 0x0 0x0 0x0 0x0>; 284 reset-gpios = <&pinctrl_ap 152 0>; 285 max-link-speed = <2>; 286 287 #address-cells = <3>; 288 #size-cells = <2>; 289 ranges; 290 291 interrupt-controller; 292 #interrupt-cells = <1>; 293 294 interrupt-map-mask = <0 0 0 7>; 295 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 296 <0 0 0 2 &port00 0 0 0 1>, 297 <0 0 0 3 &port00 0 0 0 2>, 298 <0 0 0 4 &port00 0 0 0 3>; 299 }; 300 301 port01: pci@1,0 { 302 device_type = "pci"; 303 reg = <0x800 0x0 0x0 0x0 0x0>; 304 reset-gpios = <&pinctrl_ap 153 0>; 305 max-link-speed = <2>; 306 307 #address-cells = <3>; 308 #size-cells = <2>; 309 ranges; 310 311 interrupt-controller; 312 #interrupt-cells = <1>; 313 314 interrupt-map-mask = <0 0 0 7>; 315 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 316 <0 0 0 2 &port01 0 0 0 1>, 317 <0 0 0 3 &port01 0 0 0 2>, 318 <0 0 0 4 &port01 0 0 0 3>; 319 }; 320 321 port02: pci@2,0 { 322 device_type = "pci"; 323 reg = <0x1000 0x0 0x0 0x0 0x0>; 324 reset-gpios = <&pinctrl_ap 33 0>; 325 max-link-speed = <1>; 326 327 #address-cells = <3>; 328 #size-cells = <2>; 329 ranges; 330 331 interrupt-controller; 332 #interrupt-cells = <1>; 333 334 interrupt-map-mask = <0 0 0 7>; 335 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 336 <0 0 0 2 &port02 0 0 0 1>, 337 <0 0 0 3 &port02 0 0 0 2>, 338 <0 0 0 4 &port02 0 0 0 3>; 339 }; 340 }; 341 }; 342}; 343