1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2/* 3 * Apple T8103 "M1" SoC 4 * 5 * Other names: H13G, "Tonga" 6 * 7 * Copyright The Asahi Linux Contributors 8 */ 9 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interrupt-controller/apple-aic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/pinctrl/apple.h> 14 15/ { 16 compatible = "apple,t8103", "apple,arm-platform"; 17 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus { 22 #address-cells = <2>; 23 #size-cells = <0>; 24 25 cpu0: cpu@0 { 26 compatible = "apple,icestorm"; 27 device_type = "cpu"; 28 reg = <0x0 0x0>; 29 enable-method = "spin-table"; 30 cpu-release-addr = <0 0>; /* To be filled by loader */ 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "apple,icestorm"; 35 device_type = "cpu"; 36 reg = <0x0 0x1>; 37 enable-method = "spin-table"; 38 cpu-release-addr = <0 0>; /* To be filled by loader */ 39 }; 40 41 cpu2: cpu@2 { 42 compatible = "apple,icestorm"; 43 device_type = "cpu"; 44 reg = <0x0 0x2>; 45 enable-method = "spin-table"; 46 cpu-release-addr = <0 0>; /* To be filled by loader */ 47 }; 48 49 cpu3: cpu@3 { 50 compatible = "apple,icestorm"; 51 device_type = "cpu"; 52 reg = <0x0 0x3>; 53 enable-method = "spin-table"; 54 cpu-release-addr = <0 0>; /* To be filled by loader */ 55 }; 56 57 cpu4: cpu@10100 { 58 compatible = "apple,firestorm"; 59 device_type = "cpu"; 60 reg = <0x0 0x10100>; 61 enable-method = "spin-table"; 62 cpu-release-addr = <0 0>; /* To be filled by loader */ 63 }; 64 65 cpu5: cpu@10101 { 66 compatible = "apple,firestorm"; 67 device_type = "cpu"; 68 reg = <0x0 0x10101>; 69 enable-method = "spin-table"; 70 cpu-release-addr = <0 0>; /* To be filled by loader */ 71 }; 72 73 cpu6: cpu@10102 { 74 compatible = "apple,firestorm"; 75 device_type = "cpu"; 76 reg = <0x0 0x10102>; 77 enable-method = "spin-table"; 78 cpu-release-addr = <0 0>; /* To be filled by loader */ 79 }; 80 81 cpu7: cpu@10103 { 82 compatible = "apple,firestorm"; 83 device_type = "cpu"; 84 reg = <0x0 0x10103>; 85 enable-method = "spin-table"; 86 cpu-release-addr = <0 0>; /* To be filled by loader */ 87 }; 88 }; 89 90 timer { 91 compatible = "arm,armv8-timer"; 92 interrupt-parent = <&aic>; 93 interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt"; 94 interrupts = <AIC_FIQ AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>, 95 <AIC_FIQ AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>, 96 <AIC_FIQ AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>, 97 <AIC_FIQ AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>; 98 }; 99 100 clk24: clock-24m { 101 compatible = "fixed-clock"; 102 #clock-cells = <0>; 103 clock-frequency = <24000000>; 104 clock-output-names = "clk24"; 105 }; 106 107 soc { 108 compatible = "simple-bus"; 109 #address-cells = <2>; 110 #size-cells = <2>; 111 112 ranges; 113 nonposted-mmio; 114 115 serial0: serial@235200000 { 116 compatible = "apple,s5l-uart"; 117 reg = <0x2 0x35200000 0x0 0x1000>; 118 reg-io-width = <4>; 119 interrupt-parent = <&aic>; 120 interrupts = <AIC_IRQ 605 IRQ_TYPE_LEVEL_HIGH>; 121 /* 122 * TODO: figure out the clocking properly, there may 123 * be a third selectable clock. 124 */ 125 clocks = <&clk24>, <&clk24>; 126 clock-names = "uart", "clk_uart_baud0"; 127 status = "disabled"; 128 }; 129 130 aic: interrupt-controller@23b100000 { 131 compatible = "apple,t8103-aic", "apple,aic"; 132 #interrupt-cells = <3>; 133 interrupt-controller; 134 reg = <0x2 0x3b100000 0x0 0x8000>; 135 }; 136 137 pinctrl_ap: pinctrl@23c100000 { 138 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 139 reg = <0x2 0x3c100000 0x0 0x100000>; 140 141 gpio-controller; 142 #gpio-cells = <2>; 143 gpio-ranges = <&pinctrl_ap 0 0 212>; 144 apple,npins = <212>; 145 146 interrupt-controller; 147 interrupt-parent = <&aic>; 148 interrupts = <AIC_IRQ 190 IRQ_TYPE_LEVEL_HIGH>, 149 <AIC_IRQ 191 IRQ_TYPE_LEVEL_HIGH>, 150 <AIC_IRQ 192 IRQ_TYPE_LEVEL_HIGH>, 151 <AIC_IRQ 193 IRQ_TYPE_LEVEL_HIGH>, 152 <AIC_IRQ 194 IRQ_TYPE_LEVEL_HIGH>, 153 <AIC_IRQ 195 IRQ_TYPE_LEVEL_HIGH>, 154 <AIC_IRQ 196 IRQ_TYPE_LEVEL_HIGH>; 155 156 pcie_pins: pcie-pins { 157 pinmux = <APPLE_PINMUX(150, 1)>, 158 <APPLE_PINMUX(151, 1)>, 159 <APPLE_PINMUX(32, 1)>; 160 }; 161 }; 162 163 pinctrl_aop: pinctrl@24a820000 { 164 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 165 reg = <0x2 0x4a820000 0x0 0x4000>; 166 167 gpio-controller; 168 #gpio-cells = <2>; 169 gpio-ranges = <&pinctrl_aop 0 0 42>; 170 apple,npins = <42>; 171 172 interrupt-controller; 173 interrupt-parent = <&aic>; 174 interrupts = <AIC_IRQ 268 IRQ_TYPE_LEVEL_HIGH>, 175 <AIC_IRQ 269 IRQ_TYPE_LEVEL_HIGH>, 176 <AIC_IRQ 270 IRQ_TYPE_LEVEL_HIGH>, 177 <AIC_IRQ 271 IRQ_TYPE_LEVEL_HIGH>, 178 <AIC_IRQ 272 IRQ_TYPE_LEVEL_HIGH>, 179 <AIC_IRQ 273 IRQ_TYPE_LEVEL_HIGH>, 180 <AIC_IRQ 274 IRQ_TYPE_LEVEL_HIGH>; 181 }; 182 183 pinctrl_nub: pinctrl@23d1f0000 { 184 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 185 reg = <0x2 0x3d1f0000 0x0 0x4000>; 186 187 gpio-controller; 188 #gpio-cells = <2>; 189 gpio-ranges = <&pinctrl_nub 0 0 23>; 190 apple,npins = <23>; 191 192 interrupt-controller; 193 interrupt-parent = <&aic>; 194 interrupts = <AIC_IRQ 330 IRQ_TYPE_LEVEL_HIGH>, 195 <AIC_IRQ 331 IRQ_TYPE_LEVEL_HIGH>, 196 <AIC_IRQ 332 IRQ_TYPE_LEVEL_HIGH>, 197 <AIC_IRQ 333 IRQ_TYPE_LEVEL_HIGH>, 198 <AIC_IRQ 334 IRQ_TYPE_LEVEL_HIGH>, 199 <AIC_IRQ 335 IRQ_TYPE_LEVEL_HIGH>, 200 <AIC_IRQ 336 IRQ_TYPE_LEVEL_HIGH>; 201 }; 202 203 pinctrl_smc: pinctrl@23e820000 { 204 compatible = "apple,t8103-pinctrl", "apple,pinctrl"; 205 reg = <0x2 0x3e820000 0x0 0x4000>; 206 207 gpio-controller; 208 #gpio-cells = <2>; 209 gpio-ranges = <&pinctrl_smc 0 0 16>; 210 apple,npins = <16>; 211 212 interrupt-controller; 213 interrupt-parent = <&aic>; 214 interrupts = <AIC_IRQ 391 IRQ_TYPE_LEVEL_HIGH>, 215 <AIC_IRQ 392 IRQ_TYPE_LEVEL_HIGH>, 216 <AIC_IRQ 393 IRQ_TYPE_LEVEL_HIGH>, 217 <AIC_IRQ 394 IRQ_TYPE_LEVEL_HIGH>, 218 <AIC_IRQ 395 IRQ_TYPE_LEVEL_HIGH>, 219 <AIC_IRQ 396 IRQ_TYPE_LEVEL_HIGH>, 220 <AIC_IRQ 397 IRQ_TYPE_LEVEL_HIGH>; 221 }; 222 223 pcie0_dart_0: dart@681008000 { 224 compatible = "apple,t8103-dart"; 225 reg = <0x6 0x81008000 0x0 0x4000>; 226 #iommu-cells = <1>; 227 interrupt-parent = <&aic>; 228 interrupts = <AIC_IRQ 696 IRQ_TYPE_LEVEL_HIGH>; 229 }; 230 231 pcie0_dart_1: dart@682008000 { 232 compatible = "apple,t8103-dart"; 233 reg = <0x6 0x82008000 0x0 0x4000>; 234 #iommu-cells = <1>; 235 interrupt-parent = <&aic>; 236 interrupts = <AIC_IRQ 699 IRQ_TYPE_LEVEL_HIGH>; 237 }; 238 239 pcie0_dart_2: dart@683008000 { 240 compatible = "apple,t8103-dart"; 241 reg = <0x6 0x83008000 0x0 0x4000>; 242 #iommu-cells = <1>; 243 interrupt-parent = <&aic>; 244 interrupts = <AIC_IRQ 702 IRQ_TYPE_LEVEL_HIGH>; 245 }; 246 247 pcie0: pcie@690000000 { 248 compatible = "apple,t8103-pcie", "apple,pcie"; 249 device_type = "pci"; 250 251 reg = <0x6 0x90000000 0x0 0x1000000>, 252 <0x6 0x80000000 0x0 0x100000>, 253 <0x6 0x81000000 0x0 0x4000>, 254 <0x6 0x82000000 0x0 0x4000>, 255 <0x6 0x83000000 0x0 0x4000>; 256 reg-names = "config", "rc", "port0", "port1", "port2"; 257 258 interrupt-parent = <&aic>; 259 interrupts = <AIC_IRQ 695 IRQ_TYPE_LEVEL_HIGH>, 260 <AIC_IRQ 698 IRQ_TYPE_LEVEL_HIGH>, 261 <AIC_IRQ 701 IRQ_TYPE_LEVEL_HIGH>; 262 263 msi-controller; 264 msi-parent = <&pcie0>; 265 msi-ranges = <&aic AIC_IRQ 704 IRQ_TYPE_EDGE_RISING 32>; 266 267 268 iommu-map = <0x100 &pcie0_dart_0 1 1>, 269 <0x200 &pcie0_dart_1 1 1>, 270 <0x300 &pcie0_dart_2 1 1>; 271 iommu-map-mask = <0xff00>; 272 273 bus-range = <0 3>; 274 #address-cells = <3>; 275 #size-cells = <2>; 276 ranges = <0x43000000 0x6 0xa0000000 0x6 0xa0000000 0x0 0x20000000>, 277 <0x02000000 0x0 0xc0000000 0x6 0xc0000000 0x0 0x40000000>; 278 279 pinctrl-0 = <&pcie_pins>; 280 pinctrl-names = "default"; 281 282 port00: pci@0,0 { 283 device_type = "pci"; 284 reg = <0x0 0x0 0x0 0x0 0x0>; 285 reset-gpios = <&pinctrl_ap 152 GPIO_ACTIVE_LOW>; 286 max-link-speed = <2>; 287 288 #address-cells = <3>; 289 #size-cells = <2>; 290 ranges; 291 292 interrupt-controller; 293 #interrupt-cells = <1>; 294 295 interrupt-map-mask = <0 0 0 7>; 296 interrupt-map = <0 0 0 1 &port00 0 0 0 0>, 297 <0 0 0 2 &port00 0 0 0 1>, 298 <0 0 0 3 &port00 0 0 0 2>, 299 <0 0 0 4 &port00 0 0 0 3>; 300 }; 301 302 port01: pci@1,0 { 303 device_type = "pci"; 304 reg = <0x800 0x0 0x0 0x0 0x0>; 305 reset-gpios = <&pinctrl_ap 153 GPIO_ACTIVE_LOW>; 306 max-link-speed = <2>; 307 308 #address-cells = <3>; 309 #size-cells = <2>; 310 ranges; 311 312 interrupt-controller; 313 #interrupt-cells = <1>; 314 315 interrupt-map-mask = <0 0 0 7>; 316 interrupt-map = <0 0 0 1 &port01 0 0 0 0>, 317 <0 0 0 2 &port01 0 0 0 1>, 318 <0 0 0 3 &port01 0 0 0 2>, 319 <0 0 0 4 &port01 0 0 0 3>; 320 }; 321 322 port02: pci@2,0 { 323 device_type = "pci"; 324 reg = <0x1000 0x0 0x0 0x0 0x0>; 325 reset-gpios = <&pinctrl_ap 33 GPIO_ACTIVE_LOW>; 326 max-link-speed = <1>; 327 328 #address-cells = <3>; 329 #size-cells = <2>; 330 ranges; 331 332 interrupt-controller; 333 #interrupt-cells = <1>; 334 335 interrupt-map-mask = <0 0 0 7>; 336 interrupt-map = <0 0 0 1 &port02 0 0 0 0>, 337 <0 0 0 2 &port02 0 0 0 1>, 338 <0 0 0 3 &port02 0 0 0 2>, 339 <0 0 0 4 &port02 0 0 0 3>; 340 }; 341 }; 342 }; 343}; 344