1/* 2 * dts file for AppliedMicro (APM) X-Gene Storm SOC 3 * 4 * Copyright (C) 2013, Applied Micro Circuits Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12/ { 13 compatible = "apm,xgene-storm"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu@000 { 23 device_type = "cpu"; 24 compatible = "apm,potenza", "arm,armv8"; 25 reg = <0x0 0x000>; 26 enable-method = "spin-table"; 27 cpu-release-addr = <0x1 0x0000fff8>; 28 next-level-cache = <&xgene_L2_0>; 29 }; 30 cpu@001 { 31 device_type = "cpu"; 32 compatible = "apm,potenza", "arm,armv8"; 33 reg = <0x0 0x001>; 34 enable-method = "spin-table"; 35 cpu-release-addr = <0x1 0x0000fff8>; 36 next-level-cache = <&xgene_L2_0>; 37 }; 38 cpu@100 { 39 device_type = "cpu"; 40 compatible = "apm,potenza", "arm,armv8"; 41 reg = <0x0 0x100>; 42 enable-method = "spin-table"; 43 cpu-release-addr = <0x1 0x0000fff8>; 44 next-level-cache = <&xgene_L2_1>; 45 }; 46 cpu@101 { 47 device_type = "cpu"; 48 compatible = "apm,potenza", "arm,armv8"; 49 reg = <0x0 0x101>; 50 enable-method = "spin-table"; 51 cpu-release-addr = <0x1 0x0000fff8>; 52 next-level-cache = <&xgene_L2_1>; 53 }; 54 cpu@200 { 55 device_type = "cpu"; 56 compatible = "apm,potenza", "arm,armv8"; 57 reg = <0x0 0x200>; 58 enable-method = "spin-table"; 59 cpu-release-addr = <0x1 0x0000fff8>; 60 next-level-cache = <&xgene_L2_2>; 61 }; 62 cpu@201 { 63 device_type = "cpu"; 64 compatible = "apm,potenza", "arm,armv8"; 65 reg = <0x0 0x201>; 66 enable-method = "spin-table"; 67 cpu-release-addr = <0x1 0x0000fff8>; 68 next-level-cache = <&xgene_L2_2>; 69 }; 70 cpu@300 { 71 device_type = "cpu"; 72 compatible = "apm,potenza", "arm,armv8"; 73 reg = <0x0 0x300>; 74 enable-method = "spin-table"; 75 cpu-release-addr = <0x1 0x0000fff8>; 76 next-level-cache = <&xgene_L2_3>; 77 }; 78 cpu@301 { 79 device_type = "cpu"; 80 compatible = "apm,potenza", "arm,armv8"; 81 reg = <0x0 0x301>; 82 enable-method = "spin-table"; 83 cpu-release-addr = <0x1 0x0000fff8>; 84 next-level-cache = <&xgene_L2_3>; 85 }; 86 xgene_L2_0: l2-cache-0 { 87 compatible = "cache"; 88 }; 89 xgene_L2_1: l2-cache-1 { 90 compatible = "cache"; 91 }; 92 xgene_L2_2: l2-cache-2 { 93 compatible = "cache"; 94 }; 95 xgene_L2_3: l2-cache-3 { 96 compatible = "cache"; 97 }; 98 }; 99 100 gic: interrupt-controller@78010000 { 101 compatible = "arm,cortex-a15-gic"; 102 #interrupt-cells = <3>; 103 interrupt-controller; 104 reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ 105 <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ 106 <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ 107 <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ 108 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 109 }; 110 111 timer { 112 compatible = "arm,armv8-timer"; 113 interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ 114 <1 13 0xff01>, /* Non-secure Phys IRQ */ 115 <1 14 0xff01>, /* Virt IRQ */ 116 <1 15 0xff01>; /* Hyp IRQ */ 117 clock-frequency = <50000000>; 118 }; 119 120 pmu { 121 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; 122 interrupts = <1 12 0xff04>; 123 }; 124 125 soc { 126 compatible = "simple-bus"; 127 #address-cells = <2>; 128 #size-cells = <2>; 129 ranges; 130 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; 131 132 clocks { 133 #address-cells = <2>; 134 #size-cells = <2>; 135 ranges; 136 refclk: refclk { 137 compatible = "fixed-clock"; 138 #clock-cells = <1>; 139 clock-frequency = <100000000>; 140 clock-output-names = "refclk"; 141 }; 142 143 pcppll: pcppll@17000100 { 144 compatible = "apm,xgene-pcppll-clock"; 145 #clock-cells = <1>; 146 clocks = <&refclk 0>; 147 clock-names = "pcppll"; 148 reg = <0x0 0x17000100 0x0 0x1000>; 149 clock-output-names = "pcppll"; 150 type = <0>; 151 }; 152 153 socpll: socpll@17000120 { 154 compatible = "apm,xgene-socpll-clock"; 155 #clock-cells = <1>; 156 clocks = <&refclk 0>; 157 clock-names = "socpll"; 158 reg = <0x0 0x17000120 0x0 0x1000>; 159 clock-output-names = "socpll"; 160 type = <1>; 161 }; 162 163 socplldiv2: socplldiv2 { 164 compatible = "fixed-factor-clock"; 165 #clock-cells = <1>; 166 clocks = <&socpll 0>; 167 clock-names = "socplldiv2"; 168 clock-mult = <1>; 169 clock-div = <2>; 170 clock-output-names = "socplldiv2"; 171 }; 172 173 ahbclk: ahbclk@17000000 { 174 compatible = "apm,xgene-device-clock"; 175 #clock-cells = <1>; 176 clocks = <&socplldiv2 0>; 177 reg = <0x0 0x17000000 0x0 0x2000>; 178 reg-names = "div-reg"; 179 divider-offset = <0x164>; 180 divider-width = <0x5>; 181 divider-shift = <0x0>; 182 clock-output-names = "ahbclk"; 183 }; 184 185 sdioclk: sdioclk@1f2ac000 { 186 compatible = "apm,xgene-device-clock"; 187 #clock-cells = <1>; 188 clocks = <&socplldiv2 0>; 189 reg = <0x0 0x1f2ac000 0x0 0x1000 190 0x0 0x17000000 0x0 0x2000>; 191 reg-names = "csr-reg", "div-reg"; 192 csr-offset = <0x0>; 193 csr-mask = <0x2>; 194 enable-offset = <0x8>; 195 enable-mask = <0x2>; 196 divider-offset = <0x178>; 197 divider-width = <0x8>; 198 divider-shift = <0x0>; 199 clock-output-names = "sdioclk"; 200 }; 201 202 qmlclk: qmlclk { 203 compatible = "apm,xgene-device-clock"; 204 #clock-cells = <1>; 205 clocks = <&socplldiv2 0>; 206 clock-names = "qmlclk"; 207 reg = <0x0 0x1703C000 0x0 0x1000>; 208 reg-names = "csr-reg"; 209 clock-output-names = "qmlclk"; 210 }; 211 212 ethclk: ethclk { 213 compatible = "apm,xgene-device-clock"; 214 #clock-cells = <1>; 215 clocks = <&socplldiv2 0>; 216 clock-names = "ethclk"; 217 reg = <0x0 0x17000000 0x0 0x1000>; 218 reg-names = "div-reg"; 219 divider-offset = <0x238>; 220 divider-width = <0x9>; 221 divider-shift = <0x0>; 222 clock-output-names = "ethclk"; 223 }; 224 225 menetclk: menetclk { 226 compatible = "apm,xgene-device-clock"; 227 #clock-cells = <1>; 228 clocks = <ðclk 0>; 229 reg = <0x0 0x1702C000 0x0 0x1000>; 230 reg-names = "csr-reg"; 231 clock-output-names = "menetclk"; 232 }; 233 234 sge0clk: sge0clk@1f21c000 { 235 compatible = "apm,xgene-device-clock"; 236 #clock-cells = <1>; 237 clocks = <&socplldiv2 0>; 238 reg = <0x0 0x1f21c000 0x0 0x1000>; 239 reg-names = "csr-reg"; 240 csr-mask = <0x3>; 241 clock-output-names = "sge0clk"; 242 }; 243 244 sge1clk: sge1clk@1f21c000 { 245 compatible = "apm,xgene-device-clock"; 246 #clock-cells = <1>; 247 clocks = <&socplldiv2 0>; 248 reg = <0x0 0x1f21c000 0x0 0x1000>; 249 reg-names = "csr-reg"; 250 csr-mask = <0xc>; 251 clock-output-names = "sge1clk"; 252 }; 253 254 xge0clk: xge0clk@1f61c000 { 255 compatible = "apm,xgene-device-clock"; 256 #clock-cells = <1>; 257 clocks = <&socplldiv2 0>; 258 reg = <0x0 0x1f61c000 0x0 0x1000>; 259 reg-names = "csr-reg"; 260 csr-mask = <0x3>; 261 clock-output-names = "xge0clk"; 262 }; 263 264 xge1clk: xge1clk@1f62c000 { 265 compatible = "apm,xgene-device-clock"; 266 status = "disabled"; 267 #clock-cells = <1>; 268 clocks = <&socplldiv2 0>; 269 reg = <0x0 0x1f62c000 0x0 0x1000>; 270 reg-names = "csr-reg"; 271 csr-mask = <0x3>; 272 clock-output-names = "xge1clk"; 273 }; 274 275 sataphy1clk: sataphy1clk@1f21c000 { 276 compatible = "apm,xgene-device-clock"; 277 #clock-cells = <1>; 278 clocks = <&socplldiv2 0>; 279 reg = <0x0 0x1f21c000 0x0 0x1000>; 280 reg-names = "csr-reg"; 281 clock-output-names = "sataphy1clk"; 282 status = "disabled"; 283 csr-offset = <0x4>; 284 csr-mask = <0x00>; 285 enable-offset = <0x0>; 286 enable-mask = <0x06>; 287 }; 288 289 sataphy2clk: sataphy1clk@1f22c000 { 290 compatible = "apm,xgene-device-clock"; 291 #clock-cells = <1>; 292 clocks = <&socplldiv2 0>; 293 reg = <0x0 0x1f22c000 0x0 0x1000>; 294 reg-names = "csr-reg"; 295 clock-output-names = "sataphy2clk"; 296 status = "ok"; 297 csr-offset = <0x4>; 298 csr-mask = <0x3a>; 299 enable-offset = <0x0>; 300 enable-mask = <0x06>; 301 }; 302 303 sataphy3clk: sataphy1clk@1f23c000 { 304 compatible = "apm,xgene-device-clock"; 305 #clock-cells = <1>; 306 clocks = <&socplldiv2 0>; 307 reg = <0x0 0x1f23c000 0x0 0x1000>; 308 reg-names = "csr-reg"; 309 clock-output-names = "sataphy3clk"; 310 status = "ok"; 311 csr-offset = <0x4>; 312 csr-mask = <0x3a>; 313 enable-offset = <0x0>; 314 enable-mask = <0x06>; 315 }; 316 317 sata01clk: sata01clk@1f21c000 { 318 compatible = "apm,xgene-device-clock"; 319 #clock-cells = <1>; 320 clocks = <&socplldiv2 0>; 321 reg = <0x0 0x1f21c000 0x0 0x1000>; 322 reg-names = "csr-reg"; 323 clock-output-names = "sata01clk"; 324 csr-offset = <0x4>; 325 csr-mask = <0x05>; 326 enable-offset = <0x0>; 327 enable-mask = <0x39>; 328 }; 329 330 sata23clk: sata23clk@1f22c000 { 331 compatible = "apm,xgene-device-clock"; 332 #clock-cells = <1>; 333 clocks = <&socplldiv2 0>; 334 reg = <0x0 0x1f22c000 0x0 0x1000>; 335 reg-names = "csr-reg"; 336 clock-output-names = "sata23clk"; 337 csr-offset = <0x4>; 338 csr-mask = <0x05>; 339 enable-offset = <0x0>; 340 enable-mask = <0x39>; 341 }; 342 343 sata45clk: sata45clk@1f23c000 { 344 compatible = "apm,xgene-device-clock"; 345 #clock-cells = <1>; 346 clocks = <&socplldiv2 0>; 347 reg = <0x0 0x1f23c000 0x0 0x1000>; 348 reg-names = "csr-reg"; 349 clock-output-names = "sata45clk"; 350 csr-offset = <0x4>; 351 csr-mask = <0x05>; 352 enable-offset = <0x0>; 353 enable-mask = <0x39>; 354 }; 355 356 rtcclk: rtcclk@17000000 { 357 compatible = "apm,xgene-device-clock"; 358 #clock-cells = <1>; 359 clocks = <&socplldiv2 0>; 360 reg = <0x0 0x17000000 0x0 0x2000>; 361 reg-names = "csr-reg"; 362 csr-offset = <0xc>; 363 csr-mask = <0x2>; 364 enable-offset = <0x10>; 365 enable-mask = <0x2>; 366 clock-output-names = "rtcclk"; 367 }; 368 369 rngpkaclk: rngpkaclk@17000000 { 370 compatible = "apm,xgene-device-clock"; 371 #clock-cells = <1>; 372 clocks = <&socplldiv2 0>; 373 reg = <0x0 0x17000000 0x0 0x2000>; 374 reg-names = "csr-reg"; 375 csr-offset = <0xc>; 376 csr-mask = <0x10>; 377 enable-offset = <0x10>; 378 enable-mask = <0x10>; 379 clock-output-names = "rngpkaclk"; 380 }; 381 382 pcie0clk: pcie0clk@1f2bc000 { 383 status = "disabled"; 384 compatible = "apm,xgene-device-clock"; 385 #clock-cells = <1>; 386 clocks = <&socplldiv2 0>; 387 reg = <0x0 0x1f2bc000 0x0 0x1000>; 388 reg-names = "csr-reg"; 389 clock-output-names = "pcie0clk"; 390 }; 391 392 pcie1clk: pcie1clk@1f2cc000 { 393 status = "disabled"; 394 compatible = "apm,xgene-device-clock"; 395 #clock-cells = <1>; 396 clocks = <&socplldiv2 0>; 397 reg = <0x0 0x1f2cc000 0x0 0x1000>; 398 reg-names = "csr-reg"; 399 clock-output-names = "pcie1clk"; 400 }; 401 402 pcie2clk: pcie2clk@1f2dc000 { 403 status = "disabled"; 404 compatible = "apm,xgene-device-clock"; 405 #clock-cells = <1>; 406 clocks = <&socplldiv2 0>; 407 reg = <0x0 0x1f2dc000 0x0 0x1000>; 408 reg-names = "csr-reg"; 409 clock-output-names = "pcie2clk"; 410 }; 411 412 pcie3clk: pcie3clk@1f50c000 { 413 status = "disabled"; 414 compatible = "apm,xgene-device-clock"; 415 #clock-cells = <1>; 416 clocks = <&socplldiv2 0>; 417 reg = <0x0 0x1f50c000 0x0 0x1000>; 418 reg-names = "csr-reg"; 419 clock-output-names = "pcie3clk"; 420 }; 421 422 pcie4clk: pcie4clk@1f51c000 { 423 status = "disabled"; 424 compatible = "apm,xgene-device-clock"; 425 #clock-cells = <1>; 426 clocks = <&socplldiv2 0>; 427 reg = <0x0 0x1f51c000 0x0 0x1000>; 428 reg-names = "csr-reg"; 429 clock-output-names = "pcie4clk"; 430 }; 431 432 dmaclk: dmaclk@1f27c000 { 433 compatible = "apm,xgene-device-clock"; 434 #clock-cells = <1>; 435 clocks = <&socplldiv2 0>; 436 reg = <0x0 0x1f27c000 0x0 0x1000>; 437 reg-names = "csr-reg"; 438 clock-output-names = "dmaclk"; 439 }; 440 }; 441 442 msi: msi@79000000 { 443 compatible = "apm,xgene1-msi"; 444 msi-controller; 445 reg = <0x00 0x79000000 0x0 0x900000>; 446 interrupts = < 0x0 0x10 0x4 447 0x0 0x11 0x4 448 0x0 0x12 0x4 449 0x0 0x13 0x4 450 0x0 0x14 0x4 451 0x0 0x15 0x4 452 0x0 0x16 0x4 453 0x0 0x17 0x4 454 0x0 0x18 0x4 455 0x0 0x19 0x4 456 0x0 0x1a 0x4 457 0x0 0x1b 0x4 458 0x0 0x1c 0x4 459 0x0 0x1d 0x4 460 0x0 0x1e 0x4 461 0x0 0x1f 0x4>; 462 }; 463 464 scu: system-clk-controller@17000000 { 465 compatible = "apm,xgene-scu","syscon"; 466 reg = <0x0 0x17000000 0x0 0x400>; 467 }; 468 469 reboot: reboot@17000014 { 470 compatible = "syscon-reboot"; 471 regmap = <&scu>; 472 offset = <0x14>; 473 mask = <0x1>; 474 }; 475 476 csw: csw@7e200000 { 477 compatible = "apm,xgene-csw", "syscon"; 478 reg = <0x0 0x7e200000 0x0 0x1000>; 479 }; 480 481 mcba: mcba@7e700000 { 482 compatible = "apm,xgene-mcb", "syscon"; 483 reg = <0x0 0x7e700000 0x0 0x1000>; 484 }; 485 486 mcbb: mcbb@7e720000 { 487 compatible = "apm,xgene-mcb", "syscon"; 488 reg = <0x0 0x7e720000 0x0 0x1000>; 489 }; 490 491 efuse: efuse@1054a000 { 492 compatible = "apm,xgene-efuse", "syscon"; 493 reg = <0x0 0x1054a000 0x0 0x20>; 494 }; 495 496 edac@78800000 { 497 compatible = "apm,xgene-edac"; 498 #address-cells = <2>; 499 #size-cells = <2>; 500 ranges; 501 regmap-csw = <&csw>; 502 regmap-mcba = <&mcba>; 503 regmap-mcbb = <&mcbb>; 504 regmap-efuse = <&efuse>; 505 reg = <0x0 0x78800000 0x0 0x100>; 506 interrupts = <0x0 0x20 0x4>, 507 <0x0 0x21 0x4>, 508 <0x0 0x27 0x4>; 509 510 edacmc@7e800000 { 511 compatible = "apm,xgene-edac-mc"; 512 reg = <0x0 0x7e800000 0x0 0x1000>; 513 memory-controller = <0>; 514 }; 515 516 edacmc@7e840000 { 517 compatible = "apm,xgene-edac-mc"; 518 reg = <0x0 0x7e840000 0x0 0x1000>; 519 memory-controller = <1>; 520 }; 521 522 edacmc@7e880000 { 523 compatible = "apm,xgene-edac-mc"; 524 reg = <0x0 0x7e880000 0x0 0x1000>; 525 memory-controller = <2>; 526 }; 527 528 edacmc@7e8c0000 { 529 compatible = "apm,xgene-edac-mc"; 530 reg = <0x0 0x7e8c0000 0x0 0x1000>; 531 memory-controller = <3>; 532 }; 533 534 edacpmd@7c000000 { 535 compatible = "apm,xgene-edac-pmd"; 536 reg = <0x0 0x7c000000 0x0 0x200000>; 537 pmd-controller = <0>; 538 }; 539 540 edacpmd@7c200000 { 541 compatible = "apm,xgene-edac-pmd"; 542 reg = <0x0 0x7c200000 0x0 0x200000>; 543 pmd-controller = <1>; 544 }; 545 546 edacpmd@7c400000 { 547 compatible = "apm,xgene-edac-pmd"; 548 reg = <0x0 0x7c400000 0x0 0x200000>; 549 pmd-controller = <2>; 550 }; 551 552 edacpmd@7c600000 { 553 compatible = "apm,xgene-edac-pmd"; 554 reg = <0x0 0x7c600000 0x0 0x200000>; 555 pmd-controller = <3>; 556 }; 557 558 edacl3@7e600000 { 559 compatible = "apm,xgene-edac-l3"; 560 reg = <0x0 0x7e600000 0x0 0x1000>; 561 }; 562 563 edacsoc@7e930000 { 564 compatible = "apm,xgene-edac-soc-v1"; 565 reg = <0x0 0x7e930000 0x0 0x1000>; 566 }; 567 }; 568 569 pcie0: pcie@1f2b0000 { 570 status = "disabled"; 571 device_type = "pci"; 572 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 573 #interrupt-cells = <1>; 574 #size-cells = <2>; 575 #address-cells = <3>; 576 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 577 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 578 reg-names = "csr", "cfg"; 579 ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ 580 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ 581 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ 582 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 583 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 584 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 585 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 586 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 587 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 588 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; 589 dma-coherent; 590 clocks = <&pcie0clk 0>; 591 msi-parent = <&msi>; 592 }; 593 594 pcie1: pcie@1f2c0000 { 595 status = "disabled"; 596 device_type = "pci"; 597 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 598 #interrupt-cells = <1>; 599 #size-cells = <2>; 600 #address-cells = <3>; 601 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ 602 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 603 reg-names = "csr", "cfg"; 604 ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ 605 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ 606 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ 607 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 608 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 609 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 610 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1 611 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1 612 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1 613 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; 614 dma-coherent; 615 clocks = <&pcie1clk 0>; 616 msi-parent = <&msi>; 617 }; 618 619 pcie2: pcie@1f2d0000 { 620 status = "disabled"; 621 device_type = "pci"; 622 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 623 #interrupt-cells = <1>; 624 #size-cells = <2>; 625 #address-cells = <3>; 626 reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ 627 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ 628 reg-names = "csr", "cfg"; 629 ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ 630 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ 631 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ 632 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 633 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 634 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 635 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1 636 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1 637 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1 638 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; 639 dma-coherent; 640 clocks = <&pcie2clk 0>; 641 msi-parent = <&msi>; 642 }; 643 644 pcie3: pcie@1f500000 { 645 status = "disabled"; 646 device_type = "pci"; 647 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 648 #interrupt-cells = <1>; 649 #size-cells = <2>; 650 #address-cells = <3>; 651 reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ 652 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 653 reg-names = "csr", "cfg"; 654 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ 655 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ 656 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ 657 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 658 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 659 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 660 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1 661 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1 662 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1 663 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; 664 dma-coherent; 665 clocks = <&pcie3clk 0>; 666 msi-parent = <&msi>; 667 }; 668 669 pcie4: pcie@1f510000 { 670 status = "disabled"; 671 device_type = "pci"; 672 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 673 #interrupt-cells = <1>; 674 #size-cells = <2>; 675 #address-cells = <3>; 676 reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ 677 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ 678 reg-names = "csr", "cfg"; 679 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ 680 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ 681 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ 682 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 683 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 684 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 685 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1 686 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1 687 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1 688 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; 689 dma-coherent; 690 clocks = <&pcie4clk 0>; 691 msi-parent = <&msi>; 692 }; 693 694 serial0: serial@1c020000 { 695 status = "disabled"; 696 device_type = "serial"; 697 compatible = "ns16550a"; 698 reg = <0 0x1c020000 0x0 0x1000>; 699 reg-shift = <2>; 700 clock-frequency = <10000000>; /* Updated by bootloader */ 701 interrupt-parent = <&gic>; 702 interrupts = <0x0 0x4c 0x4>; 703 }; 704 705 serial1: serial@1c021000 { 706 status = "disabled"; 707 device_type = "serial"; 708 compatible = "ns16550a"; 709 reg = <0 0x1c021000 0x0 0x1000>; 710 reg-shift = <2>; 711 clock-frequency = <10000000>; /* Updated by bootloader */ 712 interrupt-parent = <&gic>; 713 interrupts = <0x0 0x4d 0x4>; 714 }; 715 716 serial2: serial@1c022000 { 717 status = "disabled"; 718 device_type = "serial"; 719 compatible = "ns16550a"; 720 reg = <0 0x1c022000 0x0 0x1000>; 721 reg-shift = <2>; 722 clock-frequency = <10000000>; /* Updated by bootloader */ 723 interrupt-parent = <&gic>; 724 interrupts = <0x0 0x4e 0x4>; 725 }; 726 727 serial3: serial@1c023000 { 728 status = "disabled"; 729 device_type = "serial"; 730 compatible = "ns16550a"; 731 reg = <0 0x1c023000 0x0 0x1000>; 732 reg-shift = <2>; 733 clock-frequency = <10000000>; /* Updated by bootloader */ 734 interrupt-parent = <&gic>; 735 interrupts = <0x0 0x4f 0x4>; 736 }; 737 738 mmc0: mmc@1c000000 { 739 compatible = "arasan,sdhci-4.9a"; 740 reg = <0x0 0x1c000000 0x0 0x100>; 741 interrupts = <0x0 0x49 0x4>; 742 dma-coherent; 743 no-1-8-v; 744 clock-names = "clk_xin", "clk_ahb"; 745 clocks = <&sdioclk 0>, <&ahbclk 0>; 746 }; 747 748 gfcgpio: gpio0@1701c000 { 749 compatible = "apm,xgene-gpio"; 750 reg = <0x0 0x1701c000 0x0 0x40>; 751 gpio-controller; 752 #gpio-cells = <2>; 753 }; 754 755 dwgpio: gpio@1c024000 { 756 compatible = "snps,dw-apb-gpio"; 757 reg = <0x0 0x1c024000 0x0 0x1000>; 758 reg-io-width = <4>; 759 #address-cells = <1>; 760 #size-cells = <0>; 761 762 porta: gpio-controller@0 { 763 compatible = "snps,dw-apb-gpio-port"; 764 gpio-controller; 765 snps,nr-gpios = <32>; 766 reg = <0>; 767 }; 768 }; 769 770 i2c0: i2c@10512000 { 771 status = "disabled"; 772 #address-cells = <1>; 773 #size-cells = <0>; 774 compatible = "snps,designware-i2c"; 775 reg = <0x0 0x10512000 0x0 0x1000>; 776 interrupts = <0 0x44 0x4>; 777 #clock-cells = <1>; 778 clocks = <&ahbclk 0>; 779 bus_num = <0>; 780 }; 781 782 phy1: phy@1f21a000 { 783 compatible = "apm,xgene-phy"; 784 reg = <0x0 0x1f21a000 0x0 0x100>; 785 #phy-cells = <1>; 786 clocks = <&sataphy1clk 0>; 787 status = "disabled"; 788 apm,tx-boost-gain = <30 30 30 30 30 30>; 789 apm,tx-eye-tuning = <2 10 10 2 10 10>; 790 }; 791 792 phy2: phy@1f22a000 { 793 compatible = "apm,xgene-phy"; 794 reg = <0x0 0x1f22a000 0x0 0x100>; 795 #phy-cells = <1>; 796 clocks = <&sataphy2clk 0>; 797 status = "ok"; 798 apm,tx-boost-gain = <30 30 30 30 30 30>; 799 apm,tx-eye-tuning = <1 10 10 2 10 10>; 800 }; 801 802 phy3: phy@1f23a000 { 803 compatible = "apm,xgene-phy"; 804 reg = <0x0 0x1f23a000 0x0 0x100>; 805 #phy-cells = <1>; 806 clocks = <&sataphy3clk 0>; 807 status = "ok"; 808 apm,tx-boost-gain = <31 31 31 31 31 31>; 809 apm,tx-eye-tuning = <2 10 10 2 10 10>; 810 }; 811 812 sata1: sata@1a000000 { 813 compatible = "apm,xgene-ahci"; 814 reg = <0x0 0x1a000000 0x0 0x1000>, 815 <0x0 0x1f210000 0x0 0x1000>, 816 <0x0 0x1f21d000 0x0 0x1000>, 817 <0x0 0x1f21e000 0x0 0x1000>, 818 <0x0 0x1f217000 0x0 0x1000>; 819 interrupts = <0x0 0x86 0x4>; 820 dma-coherent; 821 status = "disabled"; 822 clocks = <&sata01clk 0>; 823 phys = <&phy1 0>; 824 phy-names = "sata-phy"; 825 }; 826 827 sata2: sata@1a400000 { 828 compatible = "apm,xgene-ahci"; 829 reg = <0x0 0x1a400000 0x0 0x1000>, 830 <0x0 0x1f220000 0x0 0x1000>, 831 <0x0 0x1f22d000 0x0 0x1000>, 832 <0x0 0x1f22e000 0x0 0x1000>, 833 <0x0 0x1f227000 0x0 0x1000>; 834 interrupts = <0x0 0x87 0x4>; 835 dma-coherent; 836 status = "ok"; 837 clocks = <&sata23clk 0>; 838 phys = <&phy2 0>; 839 phy-names = "sata-phy"; 840 }; 841 842 sata3: sata@1a800000 { 843 compatible = "apm,xgene-ahci"; 844 reg = <0x0 0x1a800000 0x0 0x1000>, 845 <0x0 0x1f230000 0x0 0x1000>, 846 <0x0 0x1f23d000 0x0 0x1000>, 847 <0x0 0x1f23e000 0x0 0x1000>; 848 interrupts = <0x0 0x88 0x4>; 849 dma-coherent; 850 status = "ok"; 851 clocks = <&sata45clk 0>; 852 phys = <&phy3 0>; 853 phy-names = "sata-phy"; 854 }; 855 856 /* Do not change dwusb name, coded for backward compatibility */ 857 usb0: dwusb@19000000 { 858 status = "disabled"; 859 compatible = "snps,dwc3"; 860 reg = <0x0 0x19000000 0x0 0x100000>; 861 interrupts = <0x0 0x89 0x4>; 862 dma-coherent; 863 dr_mode = "host"; 864 }; 865 866 usb1: dwusb@19800000 { 867 status = "disabled"; 868 compatible = "snps,dwc3"; 869 reg = <0x0 0x19800000 0x0 0x100000>; 870 interrupts = <0x0 0x8a 0x4>; 871 dma-coherent; 872 dr_mode = "host"; 873 }; 874 875 sbgpio: gpio@17001000{ 876 compatible = "apm,xgene-gpio-sb"; 877 reg = <0x0 0x17001000 0x0 0x400>; 878 #gpio-cells = <2>; 879 gpio-controller; 880 interrupts = <0x0 0x28 0x1>, 881 <0x0 0x29 0x1>, 882 <0x0 0x2a 0x1>, 883 <0x0 0x2b 0x1>, 884 <0x0 0x2c 0x1>, 885 <0x0 0x2d 0x1>; 886 }; 887 888 rtc: rtc@10510000 { 889 compatible = "apm,xgene-rtc"; 890 reg = <0x0 0x10510000 0x0 0x400>; 891 interrupts = <0x0 0x46 0x4>; 892 #clock-cells = <1>; 893 clocks = <&rtcclk 0>; 894 }; 895 896 menet: ethernet@17020000 { 897 compatible = "apm,xgene-enet"; 898 status = "disabled"; 899 reg = <0x0 0x17020000 0x0 0xd100>, 900 <0x0 0X17030000 0x0 0Xc300>, 901 <0x0 0X10000000 0x0 0X200>; 902 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 903 interrupts = <0x0 0x3c 0x4>; 904 dma-coherent; 905 clocks = <&menetclk 0>; 906 /* mac address will be overwritten by the bootloader */ 907 local-mac-address = [00 00 00 00 00 00]; 908 phy-connection-type = "rgmii"; 909 phy-handle = <&menetphy>; 910 mdio { 911 compatible = "apm,xgene-mdio"; 912 #address-cells = <1>; 913 #size-cells = <0>; 914 menetphy: menetphy@3 { 915 compatible = "ethernet-phy-id001c.c915"; 916 reg = <0x3>; 917 }; 918 919 }; 920 }; 921 922 sgenet0: ethernet@1f210000 { 923 compatible = "apm,xgene1-sgenet"; 924 status = "disabled"; 925 reg = <0x0 0x1f210000 0x0 0xd100>, 926 <0x0 0x1f200000 0x0 0Xc300>, 927 <0x0 0x1B000000 0x0 0X200>; 928 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 929 interrupts = <0x0 0xA0 0x4>, 930 <0x0 0xA1 0x4>; 931 dma-coherent; 932 clocks = <&sge0clk 0>; 933 local-mac-address = [00 00 00 00 00 00]; 934 phy-connection-type = "sgmii"; 935 }; 936 937 sgenet1: ethernet@1f210030 { 938 compatible = "apm,xgene1-sgenet"; 939 status = "disabled"; 940 reg = <0x0 0x1f210030 0x0 0xd100>, 941 <0x0 0x1f200000 0x0 0Xc300>, 942 <0x0 0x1B000000 0x0 0X8000>; 943 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 944 interrupts = <0x0 0xAC 0x4>, 945 <0x0 0xAD 0x4>; 946 port-id = <1>; 947 dma-coherent; 948 clocks = <&sge1clk 0>; 949 local-mac-address = [00 00 00 00 00 00]; 950 phy-connection-type = "sgmii"; 951 }; 952 953 xgenet: ethernet@1f610000 { 954 compatible = "apm,xgene1-xgenet"; 955 status = "disabled"; 956 reg = <0x0 0x1f610000 0x0 0xd100>, 957 <0x0 0x1f600000 0x0 0Xc300>, 958 <0x0 0x18000000 0x0 0X200>; 959 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 960 interrupts = <0x0 0x60 0x4>, 961 <0x0 0x61 0x4>; 962 dma-coherent; 963 clocks = <&xge0clk 0>; 964 /* mac address will be overwritten by the bootloader */ 965 local-mac-address = [00 00 00 00 00 00]; 966 phy-connection-type = "xgmii"; 967 }; 968 969 xgenet1: ethernet@1f620000 { 970 compatible = "apm,xgene1-xgenet"; 971 status = "disabled"; 972 reg = <0x0 0x1f620000 0x0 0xd100>, 973 <0x0 0x1f600000 0x0 0Xc300>, 974 <0x0 0x18000000 0x0 0X8000>; 975 reg-names = "enet_csr", "ring_csr", "ring_cmd"; 976 interrupts = <0x0 0x6C 0x4>, 977 <0x0 0x6D 0x4>; 978 port-id = <1>; 979 dma-coherent; 980 clocks = <&xge1clk 0>; 981 /* mac address will be overwritten by the bootloader */ 982 local-mac-address = [00 00 00 00 00 00]; 983 phy-connection-type = "xgmii"; 984 }; 985 986 rng: rng@10520000 { 987 compatible = "apm,xgene-rng"; 988 reg = <0x0 0x10520000 0x0 0x100>; 989 interrupts = <0x0 0x41 0x4>; 990 clocks = <&rngpkaclk 0>; 991 }; 992 993 dma: dma@1f270000 { 994 compatible = "apm,xgene-storm-dma"; 995 device_type = "dma"; 996 reg = <0x0 0x1f270000 0x0 0x10000>, 997 <0x0 0x1f200000 0x0 0x10000>, 998 <0x0 0x1b000000 0x0 0x400000>, 999 <0x0 0x1054a000 0x0 0x100>; 1000 interrupts = <0x0 0x82 0x4>, 1001 <0x0 0xb8 0x4>, 1002 <0x0 0xb9 0x4>, 1003 <0x0 0xba 0x4>, 1004 <0x0 0xbb 0x4>; 1005 dma-coherent; 1006 clocks = <&dmaclk 0>; 1007 }; 1008 }; 1009}; 1010