1ca5b3410SRobert Richter/* 2ca5b3410SRobert Richter * dts file for AppliedMicro (APM) X-Gene Storm SOC 3ca5b3410SRobert Richter * 4ca5b3410SRobert Richter * Copyright (C) 2013, Applied Micro Circuits Corporation 5ca5b3410SRobert Richter * 6ca5b3410SRobert Richter * This program is free software; you can redistribute it and/or 7ca5b3410SRobert Richter * modify it under the terms of the GNU General Public License as 8ca5b3410SRobert Richter * published by the Free Software Foundation; either version 2 of 9ca5b3410SRobert Richter * the License, or (at your option) any later version. 10ca5b3410SRobert Richter */ 11ca5b3410SRobert Richter 12ca5b3410SRobert Richter/ { 13ca5b3410SRobert Richter compatible = "apm,xgene-storm"; 14ca5b3410SRobert Richter interrupt-parent = <&gic>; 15ca5b3410SRobert Richter #address-cells = <2>; 16ca5b3410SRobert Richter #size-cells = <2>; 17ca5b3410SRobert Richter 18ca5b3410SRobert Richter cpus { 19ca5b3410SRobert Richter #address-cells = <2>; 20ca5b3410SRobert Richter #size-cells = <0>; 21ca5b3410SRobert Richter 22ca5b3410SRobert Richter cpu@000 { 23ca5b3410SRobert Richter device_type = "cpu"; 24ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 25ca5b3410SRobert Richter reg = <0x0 0x000>; 26ca5b3410SRobert Richter enable-method = "spin-table"; 27ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 28ca5b3410SRobert Richter }; 29ca5b3410SRobert Richter cpu@001 { 30ca5b3410SRobert Richter device_type = "cpu"; 31ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 32ca5b3410SRobert Richter reg = <0x0 0x001>; 33ca5b3410SRobert Richter enable-method = "spin-table"; 34ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 35ca5b3410SRobert Richter }; 36ca5b3410SRobert Richter cpu@100 { 37ca5b3410SRobert Richter device_type = "cpu"; 38ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 39ca5b3410SRobert Richter reg = <0x0 0x100>; 40ca5b3410SRobert Richter enable-method = "spin-table"; 41ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 42ca5b3410SRobert Richter }; 43ca5b3410SRobert Richter cpu@101 { 44ca5b3410SRobert Richter device_type = "cpu"; 45ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 46ca5b3410SRobert Richter reg = <0x0 0x101>; 47ca5b3410SRobert Richter enable-method = "spin-table"; 48ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 49ca5b3410SRobert Richter }; 50ca5b3410SRobert Richter cpu@200 { 51ca5b3410SRobert Richter device_type = "cpu"; 52ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 53ca5b3410SRobert Richter reg = <0x0 0x200>; 54ca5b3410SRobert Richter enable-method = "spin-table"; 55ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 56ca5b3410SRobert Richter }; 57ca5b3410SRobert Richter cpu@201 { 58ca5b3410SRobert Richter device_type = "cpu"; 59ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 60ca5b3410SRobert Richter reg = <0x0 0x201>; 61ca5b3410SRobert Richter enable-method = "spin-table"; 62ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 63ca5b3410SRobert Richter }; 64ca5b3410SRobert Richter cpu@300 { 65ca5b3410SRobert Richter device_type = "cpu"; 66ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 67ca5b3410SRobert Richter reg = <0x0 0x300>; 68ca5b3410SRobert Richter enable-method = "spin-table"; 69ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 70ca5b3410SRobert Richter }; 71ca5b3410SRobert Richter cpu@301 { 72ca5b3410SRobert Richter device_type = "cpu"; 73ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 74ca5b3410SRobert Richter reg = <0x0 0x301>; 75ca5b3410SRobert Richter enable-method = "spin-table"; 76ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 77ca5b3410SRobert Richter }; 78ca5b3410SRobert Richter }; 79ca5b3410SRobert Richter 80ca5b3410SRobert Richter gic: interrupt-controller@78010000 { 81ca5b3410SRobert Richter compatible = "arm,cortex-a15-gic"; 82ca5b3410SRobert Richter #interrupt-cells = <3>; 83ca5b3410SRobert Richter interrupt-controller; 84ca5b3410SRobert Richter reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ 85ca5b3410SRobert Richter <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ 86ca5b3410SRobert Richter <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ 87ca5b3410SRobert Richter <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ 88ca5b3410SRobert Richter interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 89ca5b3410SRobert Richter }; 90ca5b3410SRobert Richter 91ca5b3410SRobert Richter timer { 92ca5b3410SRobert Richter compatible = "arm,armv8-timer"; 93ca5b3410SRobert Richter interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ 94ca5b3410SRobert Richter <1 13 0xff01>, /* Non-secure Phys IRQ */ 95ca5b3410SRobert Richter <1 14 0xff01>, /* Virt IRQ */ 96ca5b3410SRobert Richter <1 15 0xff01>; /* Hyp IRQ */ 97ca5b3410SRobert Richter clock-frequency = <50000000>; 98ca5b3410SRobert Richter }; 99ca5b3410SRobert Richter 100ca5b3410SRobert Richter soc { 101ca5b3410SRobert Richter compatible = "simple-bus"; 102ca5b3410SRobert Richter #address-cells = <2>; 103ca5b3410SRobert Richter #size-cells = <2>; 104ca5b3410SRobert Richter ranges; 10574e353e1SRameshwar Prasad Sahu dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; 106ca5b3410SRobert Richter 107ca5b3410SRobert Richter clocks { 108ca5b3410SRobert Richter #address-cells = <2>; 109ca5b3410SRobert Richter #size-cells = <2>; 110ca5b3410SRobert Richter ranges; 111ca5b3410SRobert Richter refclk: refclk { 112ca5b3410SRobert Richter compatible = "fixed-clock"; 113ca5b3410SRobert Richter #clock-cells = <1>; 114ca5b3410SRobert Richter clock-frequency = <100000000>; 115ca5b3410SRobert Richter clock-output-names = "refclk"; 116ca5b3410SRobert Richter }; 117ca5b3410SRobert Richter 118ca5b3410SRobert Richter pcppll: pcppll@17000100 { 119ca5b3410SRobert Richter compatible = "apm,xgene-pcppll-clock"; 120ca5b3410SRobert Richter #clock-cells = <1>; 121ca5b3410SRobert Richter clocks = <&refclk 0>; 122ca5b3410SRobert Richter clock-names = "pcppll"; 123ca5b3410SRobert Richter reg = <0x0 0x17000100 0x0 0x1000>; 124ca5b3410SRobert Richter clock-output-names = "pcppll"; 125ca5b3410SRobert Richter type = <0>; 126ca5b3410SRobert Richter }; 127ca5b3410SRobert Richter 128ca5b3410SRobert Richter socpll: socpll@17000120 { 129ca5b3410SRobert Richter compatible = "apm,xgene-socpll-clock"; 130ca5b3410SRobert Richter #clock-cells = <1>; 131ca5b3410SRobert Richter clocks = <&refclk 0>; 132ca5b3410SRobert Richter clock-names = "socpll"; 133ca5b3410SRobert Richter reg = <0x0 0x17000120 0x0 0x1000>; 134ca5b3410SRobert Richter clock-output-names = "socpll"; 135ca5b3410SRobert Richter type = <1>; 136ca5b3410SRobert Richter }; 137ca5b3410SRobert Richter 138ca5b3410SRobert Richter socplldiv2: socplldiv2 { 139ca5b3410SRobert Richter compatible = "fixed-factor-clock"; 140ca5b3410SRobert Richter #clock-cells = <1>; 141ca5b3410SRobert Richter clocks = <&socpll 0>; 142ca5b3410SRobert Richter clock-names = "socplldiv2"; 143ca5b3410SRobert Richter clock-mult = <1>; 144ca5b3410SRobert Richter clock-div = <2>; 145ca5b3410SRobert Richter clock-output-names = "socplldiv2"; 146ca5b3410SRobert Richter }; 147ca5b3410SRobert Richter 148ca5b3410SRobert Richter qmlclk: qmlclk { 149ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 150ca5b3410SRobert Richter #clock-cells = <1>; 151ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 152ca5b3410SRobert Richter clock-names = "qmlclk"; 153ca5b3410SRobert Richter reg = <0x0 0x1703C000 0x0 0x1000>; 154ca5b3410SRobert Richter reg-names = "csr-reg"; 155ca5b3410SRobert Richter clock-output-names = "qmlclk"; 156ca5b3410SRobert Richter }; 157ca5b3410SRobert Richter 158ca5b3410SRobert Richter ethclk: ethclk { 159ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 160ca5b3410SRobert Richter #clock-cells = <1>; 161ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 162ca5b3410SRobert Richter clock-names = "ethclk"; 163ca5b3410SRobert Richter reg = <0x0 0x17000000 0x0 0x1000>; 164ca5b3410SRobert Richter reg-names = "div-reg"; 165ca5b3410SRobert Richter divider-offset = <0x238>; 166ca5b3410SRobert Richter divider-width = <0x9>; 167ca5b3410SRobert Richter divider-shift = <0x0>; 168ca5b3410SRobert Richter clock-output-names = "ethclk"; 169ca5b3410SRobert Richter }; 170ca5b3410SRobert Richter 171ca5b3410SRobert Richter menetclk: menetclk { 172ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 173ca5b3410SRobert Richter #clock-cells = <1>; 174ca5b3410SRobert Richter clocks = <ðclk 0>; 175ca5b3410SRobert Richter reg = <0x0 0x1702C000 0x0 0x1000>; 176ca5b3410SRobert Richter reg-names = "csr-reg"; 177ca5b3410SRobert Richter clock-output-names = "menetclk"; 178ca5b3410SRobert Richter }; 179ca5b3410SRobert Richter 180ca5b3410SRobert Richter sge0clk: sge0clk@1f21c000 { 181ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 182ca5b3410SRobert Richter #clock-cells = <1>; 183ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 184ca5b3410SRobert Richter reg = <0x0 0x1f21c000 0x0 0x1000>; 185ca5b3410SRobert Richter reg-names = "csr-reg"; 186ca5b3410SRobert Richter csr-mask = <0x3>; 187ca5b3410SRobert Richter clock-output-names = "sge0clk"; 188ca5b3410SRobert Richter }; 189ca5b3410SRobert Richter 1902d33394eSKeyur Chudgar sge1clk: sge1clk@1f21c000 { 1912d33394eSKeyur Chudgar compatible = "apm,xgene-device-clock"; 1922d33394eSKeyur Chudgar #clock-cells = <1>; 1932d33394eSKeyur Chudgar clocks = <&socplldiv2 0>; 1942d33394eSKeyur Chudgar reg = <0x0 0x1f21c000 0x0 0x1000>; 1952d33394eSKeyur Chudgar reg-names = "csr-reg"; 1962d33394eSKeyur Chudgar csr-mask = <0xc>; 1972d33394eSKeyur Chudgar clock-output-names = "sge1clk"; 1982d33394eSKeyur Chudgar }; 1992d33394eSKeyur Chudgar 200ca5b3410SRobert Richter xge0clk: xge0clk@1f61c000 { 201ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 202ca5b3410SRobert Richter #clock-cells = <1>; 203ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 204ca5b3410SRobert Richter reg = <0x0 0x1f61c000 0x0 0x1000>; 205ca5b3410SRobert Richter reg-names = "csr-reg"; 206ca5b3410SRobert Richter csr-mask = <0x3>; 207ca5b3410SRobert Richter clock-output-names = "xge0clk"; 208ca5b3410SRobert Richter }; 209ca5b3410SRobert Richter 210e63c7a09SIyappan Subramanian xge1clk: xge1clk@1f62c000 { 211e63c7a09SIyappan Subramanian compatible = "apm,xgene-device-clock"; 212e63c7a09SIyappan Subramanian status = "disabled"; 213e63c7a09SIyappan Subramanian #clock-cells = <1>; 214e63c7a09SIyappan Subramanian clocks = <&socplldiv2 0>; 215e63c7a09SIyappan Subramanian reg = <0x0 0x1f62c000 0x0 0x1000>; 216e63c7a09SIyappan Subramanian reg-names = "csr-reg"; 217e63c7a09SIyappan Subramanian csr-mask = <0x3>; 218e63c7a09SIyappan Subramanian clock-output-names = "xge1clk"; 219e63c7a09SIyappan Subramanian }; 220e63c7a09SIyappan Subramanian 221ca5b3410SRobert Richter sataphy1clk: sataphy1clk@1f21c000 { 222ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 223ca5b3410SRobert Richter #clock-cells = <1>; 224ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 225ca5b3410SRobert Richter reg = <0x0 0x1f21c000 0x0 0x1000>; 226ca5b3410SRobert Richter reg-names = "csr-reg"; 227ca5b3410SRobert Richter clock-output-names = "sataphy1clk"; 228ca5b3410SRobert Richter status = "disabled"; 229ca5b3410SRobert Richter csr-offset = <0x4>; 230ca5b3410SRobert Richter csr-mask = <0x00>; 231ca5b3410SRobert Richter enable-offset = <0x0>; 232ca5b3410SRobert Richter enable-mask = <0x06>; 233ca5b3410SRobert Richter }; 234ca5b3410SRobert Richter 235ca5b3410SRobert Richter sataphy2clk: sataphy1clk@1f22c000 { 236ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 237ca5b3410SRobert Richter #clock-cells = <1>; 238ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 239ca5b3410SRobert Richter reg = <0x0 0x1f22c000 0x0 0x1000>; 240ca5b3410SRobert Richter reg-names = "csr-reg"; 241ca5b3410SRobert Richter clock-output-names = "sataphy2clk"; 242ca5b3410SRobert Richter status = "ok"; 243ca5b3410SRobert Richter csr-offset = <0x4>; 244ca5b3410SRobert Richter csr-mask = <0x3a>; 245ca5b3410SRobert Richter enable-offset = <0x0>; 246ca5b3410SRobert Richter enable-mask = <0x06>; 247ca5b3410SRobert Richter }; 248ca5b3410SRobert Richter 249ca5b3410SRobert Richter sataphy3clk: sataphy1clk@1f23c000 { 250ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 251ca5b3410SRobert Richter #clock-cells = <1>; 252ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 253ca5b3410SRobert Richter reg = <0x0 0x1f23c000 0x0 0x1000>; 254ca5b3410SRobert Richter reg-names = "csr-reg"; 255ca5b3410SRobert Richter clock-output-names = "sataphy3clk"; 256ca5b3410SRobert Richter status = "ok"; 257ca5b3410SRobert Richter csr-offset = <0x4>; 258ca5b3410SRobert Richter csr-mask = <0x3a>; 259ca5b3410SRobert Richter enable-offset = <0x0>; 260ca5b3410SRobert Richter enable-mask = <0x06>; 261ca5b3410SRobert Richter }; 262ca5b3410SRobert Richter 263ca5b3410SRobert Richter sata01clk: sata01clk@1f21c000 { 264ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 265ca5b3410SRobert Richter #clock-cells = <1>; 266ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 267ca5b3410SRobert Richter reg = <0x0 0x1f21c000 0x0 0x1000>; 268ca5b3410SRobert Richter reg-names = "csr-reg"; 269ca5b3410SRobert Richter clock-output-names = "sata01clk"; 270ca5b3410SRobert Richter csr-offset = <0x4>; 271ca5b3410SRobert Richter csr-mask = <0x05>; 272ca5b3410SRobert Richter enable-offset = <0x0>; 273ca5b3410SRobert Richter enable-mask = <0x39>; 274ca5b3410SRobert Richter }; 275ca5b3410SRobert Richter 276ca5b3410SRobert Richter sata23clk: sata23clk@1f22c000 { 277ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 278ca5b3410SRobert Richter #clock-cells = <1>; 279ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 280ca5b3410SRobert Richter reg = <0x0 0x1f22c000 0x0 0x1000>; 281ca5b3410SRobert Richter reg-names = "csr-reg"; 282ca5b3410SRobert Richter clock-output-names = "sata23clk"; 283ca5b3410SRobert Richter csr-offset = <0x4>; 284ca5b3410SRobert Richter csr-mask = <0x05>; 285ca5b3410SRobert Richter enable-offset = <0x0>; 286ca5b3410SRobert Richter enable-mask = <0x39>; 287ca5b3410SRobert Richter }; 288ca5b3410SRobert Richter 289ca5b3410SRobert Richter sata45clk: sata45clk@1f23c000 { 290ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 291ca5b3410SRobert Richter #clock-cells = <1>; 292ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 293ca5b3410SRobert Richter reg = <0x0 0x1f23c000 0x0 0x1000>; 294ca5b3410SRobert Richter reg-names = "csr-reg"; 295ca5b3410SRobert Richter clock-output-names = "sata45clk"; 296ca5b3410SRobert Richter csr-offset = <0x4>; 297ca5b3410SRobert Richter csr-mask = <0x05>; 298ca5b3410SRobert Richter enable-offset = <0x0>; 299ca5b3410SRobert Richter enable-mask = <0x39>; 300ca5b3410SRobert Richter }; 301ca5b3410SRobert Richter 302ca5b3410SRobert Richter rtcclk: rtcclk@17000000 { 303ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 304ca5b3410SRobert Richter #clock-cells = <1>; 305ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 306ca5b3410SRobert Richter reg = <0x0 0x17000000 0x0 0x2000>; 307ca5b3410SRobert Richter reg-names = "csr-reg"; 308ca5b3410SRobert Richter csr-offset = <0xc>; 309ca5b3410SRobert Richter csr-mask = <0x2>; 310ca5b3410SRobert Richter enable-offset = <0x10>; 311ca5b3410SRobert Richter enable-mask = <0x2>; 312ca5b3410SRobert Richter clock-output-names = "rtcclk"; 313ca5b3410SRobert Richter }; 314ca5b3410SRobert Richter 315ca5b3410SRobert Richter rngpkaclk: rngpkaclk@17000000 { 316ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 317ca5b3410SRobert Richter #clock-cells = <1>; 318ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 319ca5b3410SRobert Richter reg = <0x0 0x17000000 0x0 0x2000>; 320ca5b3410SRobert Richter reg-names = "csr-reg"; 321ca5b3410SRobert Richter csr-offset = <0xc>; 322ca5b3410SRobert Richter csr-mask = <0x10>; 323ca5b3410SRobert Richter enable-offset = <0x10>; 324ca5b3410SRobert Richter enable-mask = <0x10>; 325ca5b3410SRobert Richter clock-output-names = "rngpkaclk"; 326ca5b3410SRobert Richter }; 327ca5b3410SRobert Richter 328ca5b3410SRobert Richter pcie0clk: pcie0clk@1f2bc000 { 329ca5b3410SRobert Richter status = "disabled"; 330ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 331ca5b3410SRobert Richter #clock-cells = <1>; 332ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 333ca5b3410SRobert Richter reg = <0x0 0x1f2bc000 0x0 0x1000>; 334ca5b3410SRobert Richter reg-names = "csr-reg"; 335ca5b3410SRobert Richter clock-output-names = "pcie0clk"; 336ca5b3410SRobert Richter }; 337ca5b3410SRobert Richter 338ca5b3410SRobert Richter pcie1clk: pcie1clk@1f2cc000 { 339ca5b3410SRobert Richter status = "disabled"; 340ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 341ca5b3410SRobert Richter #clock-cells = <1>; 342ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 343ca5b3410SRobert Richter reg = <0x0 0x1f2cc000 0x0 0x1000>; 344ca5b3410SRobert Richter reg-names = "csr-reg"; 345ca5b3410SRobert Richter clock-output-names = "pcie1clk"; 346ca5b3410SRobert Richter }; 347ca5b3410SRobert Richter 348ca5b3410SRobert Richter pcie2clk: pcie2clk@1f2dc000 { 349ca5b3410SRobert Richter status = "disabled"; 350ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 351ca5b3410SRobert Richter #clock-cells = <1>; 352ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 353ca5b3410SRobert Richter reg = <0x0 0x1f2dc000 0x0 0x1000>; 354ca5b3410SRobert Richter reg-names = "csr-reg"; 355ca5b3410SRobert Richter clock-output-names = "pcie2clk"; 356ca5b3410SRobert Richter }; 357ca5b3410SRobert Richter 358ca5b3410SRobert Richter pcie3clk: pcie3clk@1f50c000 { 359ca5b3410SRobert Richter status = "disabled"; 360ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 361ca5b3410SRobert Richter #clock-cells = <1>; 362ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 363ca5b3410SRobert Richter reg = <0x0 0x1f50c000 0x0 0x1000>; 364ca5b3410SRobert Richter reg-names = "csr-reg"; 365ca5b3410SRobert Richter clock-output-names = "pcie3clk"; 366ca5b3410SRobert Richter }; 367ca5b3410SRobert Richter 368ca5b3410SRobert Richter pcie4clk: pcie4clk@1f51c000 { 369ca5b3410SRobert Richter status = "disabled"; 370ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 371ca5b3410SRobert Richter #clock-cells = <1>; 372ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 373ca5b3410SRobert Richter reg = <0x0 0x1f51c000 0x0 0x1000>; 374ca5b3410SRobert Richter reg-names = "csr-reg"; 375ca5b3410SRobert Richter clock-output-names = "pcie4clk"; 376ca5b3410SRobert Richter }; 37774e353e1SRameshwar Prasad Sahu 37874e353e1SRameshwar Prasad Sahu dmaclk: dmaclk@1f27c000 { 37974e353e1SRameshwar Prasad Sahu compatible = "apm,xgene-device-clock"; 38074e353e1SRameshwar Prasad Sahu #clock-cells = <1>; 38174e353e1SRameshwar Prasad Sahu clocks = <&socplldiv2 0>; 38274e353e1SRameshwar Prasad Sahu reg = <0x0 0x1f27c000 0x0 0x1000>; 38374e353e1SRameshwar Prasad Sahu reg-names = "csr-reg"; 38474e353e1SRameshwar Prasad Sahu clock-output-names = "dmaclk"; 38574e353e1SRameshwar Prasad Sahu }; 386ca5b3410SRobert Richter }; 387ca5b3410SRobert Richter 388e1e6e5c4SDuc Dang msi: msi@79000000 { 389e1e6e5c4SDuc Dang compatible = "apm,xgene1-msi"; 390e1e6e5c4SDuc Dang msi-controller; 391e1e6e5c4SDuc Dang reg = <0x00 0x79000000 0x0 0x900000>; 392e1e6e5c4SDuc Dang interrupts = < 0x0 0x10 0x4 393e1e6e5c4SDuc Dang 0x0 0x11 0x4 394e1e6e5c4SDuc Dang 0x0 0x12 0x4 395e1e6e5c4SDuc Dang 0x0 0x13 0x4 396e1e6e5c4SDuc Dang 0x0 0x14 0x4 397e1e6e5c4SDuc Dang 0x0 0x15 0x4 398e1e6e5c4SDuc Dang 0x0 0x16 0x4 399e1e6e5c4SDuc Dang 0x0 0x17 0x4 400e1e6e5c4SDuc Dang 0x0 0x18 0x4 401e1e6e5c4SDuc Dang 0x0 0x19 0x4 402e1e6e5c4SDuc Dang 0x0 0x1a 0x4 403e1e6e5c4SDuc Dang 0x0 0x1b 0x4 404e1e6e5c4SDuc Dang 0x0 0x1c 0x4 405e1e6e5c4SDuc Dang 0x0 0x1d 0x4 406e1e6e5c4SDuc Dang 0x0 0x1e 0x4 407e1e6e5c4SDuc Dang 0x0 0x1f 0x4>; 408e1e6e5c4SDuc Dang }; 409e1e6e5c4SDuc Dang 4108f2ae6f3SLoc Ho csw: csw@7e200000 { 4118f2ae6f3SLoc Ho compatible = "apm,xgene-csw", "syscon"; 4128f2ae6f3SLoc Ho reg = <0x0 0x7e200000 0x0 0x1000>; 4138f2ae6f3SLoc Ho }; 4148f2ae6f3SLoc Ho 4158f2ae6f3SLoc Ho mcba: mcba@7e700000 { 4168f2ae6f3SLoc Ho compatible = "apm,xgene-mcb", "syscon"; 4178f2ae6f3SLoc Ho reg = <0x0 0x7e700000 0x0 0x1000>; 4188f2ae6f3SLoc Ho }; 4198f2ae6f3SLoc Ho 4208f2ae6f3SLoc Ho mcbb: mcbb@7e720000 { 4218f2ae6f3SLoc Ho compatible = "apm,xgene-mcb", "syscon"; 4228f2ae6f3SLoc Ho reg = <0x0 0x7e720000 0x0 0x1000>; 4238f2ae6f3SLoc Ho }; 4248f2ae6f3SLoc Ho 4258f2ae6f3SLoc Ho efuse: efuse@1054a000 { 4268f2ae6f3SLoc Ho compatible = "apm,xgene-efuse", "syscon"; 4278f2ae6f3SLoc Ho reg = <0x0 0x1054a000 0x0 0x20>; 4288f2ae6f3SLoc Ho }; 4298f2ae6f3SLoc Ho 4308f2ae6f3SLoc Ho edac@78800000 { 4318f2ae6f3SLoc Ho compatible = "apm,xgene-edac"; 4328f2ae6f3SLoc Ho #address-cells = <2>; 4338f2ae6f3SLoc Ho #size-cells = <2>; 4348f2ae6f3SLoc Ho ranges; 4358f2ae6f3SLoc Ho regmap-csw = <&csw>; 4368f2ae6f3SLoc Ho regmap-mcba = <&mcba>; 4378f2ae6f3SLoc Ho regmap-mcbb = <&mcbb>; 4388f2ae6f3SLoc Ho regmap-efuse = <&efuse>; 4398f2ae6f3SLoc Ho reg = <0x0 0x78800000 0x0 0x100>; 4408f2ae6f3SLoc Ho interrupts = <0x0 0x20 0x4>, 4418f2ae6f3SLoc Ho <0x0 0x21 0x4>, 4428f2ae6f3SLoc Ho <0x0 0x27 0x4>; 4438f2ae6f3SLoc Ho 4448f2ae6f3SLoc Ho edacmc@7e800000 { 4458f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 4468f2ae6f3SLoc Ho reg = <0x0 0x7e800000 0x0 0x1000>; 4478f2ae6f3SLoc Ho memory-controller = <0>; 4488f2ae6f3SLoc Ho }; 4498f2ae6f3SLoc Ho 4508f2ae6f3SLoc Ho edacmc@7e840000 { 4518f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 4528f2ae6f3SLoc Ho reg = <0x0 0x7e840000 0x0 0x1000>; 4538f2ae6f3SLoc Ho memory-controller = <1>; 4548f2ae6f3SLoc Ho }; 4558f2ae6f3SLoc Ho 4568f2ae6f3SLoc Ho edacmc@7e880000 { 4578f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 4588f2ae6f3SLoc Ho reg = <0x0 0x7e880000 0x0 0x1000>; 4598f2ae6f3SLoc Ho memory-controller = <2>; 4608f2ae6f3SLoc Ho }; 4618f2ae6f3SLoc Ho 4628f2ae6f3SLoc Ho edacmc@7e8c0000 { 4638f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 4648f2ae6f3SLoc Ho reg = <0x0 0x7e8c0000 0x0 0x1000>; 4658f2ae6f3SLoc Ho memory-controller = <3>; 4668f2ae6f3SLoc Ho }; 4678f2ae6f3SLoc Ho 4688f2ae6f3SLoc Ho edacpmd@7c000000 { 4698f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 4708f2ae6f3SLoc Ho reg = <0x0 0x7c000000 0x0 0x200000>; 4718f2ae6f3SLoc Ho pmd-controller = <0>; 4728f2ae6f3SLoc Ho }; 4738f2ae6f3SLoc Ho 4748f2ae6f3SLoc Ho edacpmd@7c200000 { 4758f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 4768f2ae6f3SLoc Ho reg = <0x0 0x7c200000 0x0 0x200000>; 4778f2ae6f3SLoc Ho pmd-controller = <1>; 4788f2ae6f3SLoc Ho }; 4798f2ae6f3SLoc Ho 4808f2ae6f3SLoc Ho edacpmd@7c400000 { 4818f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 4828f2ae6f3SLoc Ho reg = <0x0 0x7c400000 0x0 0x200000>; 4838f2ae6f3SLoc Ho pmd-controller = <2>; 4848f2ae6f3SLoc Ho }; 4858f2ae6f3SLoc Ho 4868f2ae6f3SLoc Ho edacpmd@7c600000 { 4878f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 4888f2ae6f3SLoc Ho reg = <0x0 0x7c600000 0x0 0x200000>; 4898f2ae6f3SLoc Ho pmd-controller = <3>; 4908f2ae6f3SLoc Ho }; 4918f2ae6f3SLoc Ho }; 4928f2ae6f3SLoc Ho 493ca5b3410SRobert Richter pcie0: pcie@1f2b0000 { 494ca5b3410SRobert Richter status = "disabled"; 495ca5b3410SRobert Richter device_type = "pci"; 496ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 497ca5b3410SRobert Richter #interrupt-cells = <1>; 498ca5b3410SRobert Richter #size-cells = <2>; 499ca5b3410SRobert Richter #address-cells = <3>; 500ca5b3410SRobert Richter reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 501ca5b3410SRobert Richter 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 502ca5b3410SRobert Richter reg-names = "csr", "cfg"; 503ca5b3410SRobert Richter ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ 50480bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ 50580bb3edaSDuc Dang 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ 506ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 507ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 508ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 509ca5b3410SRobert Richter interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 510ca5b3410SRobert Richter 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 511ca5b3410SRobert Richter 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 512ca5b3410SRobert Richter 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; 513ca5b3410SRobert Richter dma-coherent; 514ca5b3410SRobert Richter clocks = <&pcie0clk 0>; 515e1e6e5c4SDuc Dang msi-parent = <&msi>; 516ca5b3410SRobert Richter }; 517ca5b3410SRobert Richter 518ca5b3410SRobert Richter pcie1: pcie@1f2c0000 { 519ca5b3410SRobert Richter status = "disabled"; 520ca5b3410SRobert Richter device_type = "pci"; 521ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 522ca5b3410SRobert Richter #interrupt-cells = <1>; 523ca5b3410SRobert Richter #size-cells = <2>; 524ca5b3410SRobert Richter #address-cells = <3>; 525ca5b3410SRobert Richter reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ 526ca5b3410SRobert Richter 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 527ca5b3410SRobert Richter reg-names = "csr", "cfg"; 52880bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ 52980bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ 53080bb3edaSDuc Dang 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ 531ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 532ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 533ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 534ca5b3410SRobert Richter interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x1 535ca5b3410SRobert Richter 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x1 536ca5b3410SRobert Richter 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x1 537ca5b3410SRobert Richter 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x1>; 538ca5b3410SRobert Richter dma-coherent; 539ca5b3410SRobert Richter clocks = <&pcie1clk 0>; 540e1e6e5c4SDuc Dang msi-parent = <&msi>; 541ca5b3410SRobert Richter }; 542ca5b3410SRobert Richter 543ca5b3410SRobert Richter pcie2: pcie@1f2d0000 { 544ca5b3410SRobert Richter status = "disabled"; 545ca5b3410SRobert Richter device_type = "pci"; 546ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 547ca5b3410SRobert Richter #interrupt-cells = <1>; 548ca5b3410SRobert Richter #size-cells = <2>; 549ca5b3410SRobert Richter #address-cells = <3>; 550ca5b3410SRobert Richter reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ 551ca5b3410SRobert Richter 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ 552ca5b3410SRobert Richter reg-names = "csr", "cfg"; 55380bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ 55480bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ 55580bb3edaSDuc Dang 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ 556ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 557ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 558ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 559ca5b3410SRobert Richter interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x1 560ca5b3410SRobert Richter 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x1 561ca5b3410SRobert Richter 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x1 562ca5b3410SRobert Richter 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x1>; 563ca5b3410SRobert Richter dma-coherent; 564ca5b3410SRobert Richter clocks = <&pcie2clk 0>; 565e1e6e5c4SDuc Dang msi-parent = <&msi>; 566ca5b3410SRobert Richter }; 567ca5b3410SRobert Richter 568ca5b3410SRobert Richter pcie3: pcie@1f500000 { 569ca5b3410SRobert Richter status = "disabled"; 570ca5b3410SRobert Richter device_type = "pci"; 571ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 572ca5b3410SRobert Richter #interrupt-cells = <1>; 573ca5b3410SRobert Richter #size-cells = <2>; 574ca5b3410SRobert Richter #address-cells = <3>; 575ca5b3410SRobert Richter reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ 576ca5b3410SRobert Richter 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 577ca5b3410SRobert Richter reg-names = "csr", "cfg"; 57880bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ 57980bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ 58080bb3edaSDuc Dang 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ 581ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 582ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 583ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 584ca5b3410SRobert Richter interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x1 585ca5b3410SRobert Richter 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x1 586ca5b3410SRobert Richter 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x1 587ca5b3410SRobert Richter 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x1>; 588ca5b3410SRobert Richter dma-coherent; 589ca5b3410SRobert Richter clocks = <&pcie3clk 0>; 590e1e6e5c4SDuc Dang msi-parent = <&msi>; 591ca5b3410SRobert Richter }; 592ca5b3410SRobert Richter 593ca5b3410SRobert Richter pcie4: pcie@1f510000 { 594ca5b3410SRobert Richter status = "disabled"; 595ca5b3410SRobert Richter device_type = "pci"; 596ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 597ca5b3410SRobert Richter #interrupt-cells = <1>; 598ca5b3410SRobert Richter #size-cells = <2>; 599ca5b3410SRobert Richter #address-cells = <3>; 600ca5b3410SRobert Richter reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ 601ca5b3410SRobert Richter 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ 602ca5b3410SRobert Richter reg-names = "csr", "cfg"; 60380bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ 60480bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ 60580bb3edaSDuc Dang 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ 606ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 607ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 608ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 609ca5b3410SRobert Richter interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x1 610ca5b3410SRobert Richter 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x1 611ca5b3410SRobert Richter 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x1 612ca5b3410SRobert Richter 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x1>; 613ca5b3410SRobert Richter dma-coherent; 614ca5b3410SRobert Richter clocks = <&pcie4clk 0>; 615e1e6e5c4SDuc Dang msi-parent = <&msi>; 616ca5b3410SRobert Richter }; 617ca5b3410SRobert Richter 618ca5b3410SRobert Richter serial0: serial@1c020000 { 619ca5b3410SRobert Richter status = "disabled"; 620ca5b3410SRobert Richter device_type = "serial"; 621ca5b3410SRobert Richter compatible = "ns16550a"; 622ca5b3410SRobert Richter reg = <0 0x1c020000 0x0 0x1000>; 623ca5b3410SRobert Richter reg-shift = <2>; 624ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 625ca5b3410SRobert Richter interrupt-parent = <&gic>; 626ca5b3410SRobert Richter interrupts = <0x0 0x4c 0x4>; 627ca5b3410SRobert Richter }; 628ca5b3410SRobert Richter 629ca5b3410SRobert Richter serial1: serial@1c021000 { 630ca5b3410SRobert Richter status = "disabled"; 631ca5b3410SRobert Richter device_type = "serial"; 632ca5b3410SRobert Richter compatible = "ns16550a"; 633ca5b3410SRobert Richter reg = <0 0x1c021000 0x0 0x1000>; 634ca5b3410SRobert Richter reg-shift = <2>; 635ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 636ca5b3410SRobert Richter interrupt-parent = <&gic>; 637ca5b3410SRobert Richter interrupts = <0x0 0x4d 0x4>; 638ca5b3410SRobert Richter }; 639ca5b3410SRobert Richter 640ca5b3410SRobert Richter serial2: serial@1c022000 { 641ca5b3410SRobert Richter status = "disabled"; 642ca5b3410SRobert Richter device_type = "serial"; 643ca5b3410SRobert Richter compatible = "ns16550a"; 644ca5b3410SRobert Richter reg = <0 0x1c022000 0x0 0x1000>; 645ca5b3410SRobert Richter reg-shift = <2>; 646ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 647ca5b3410SRobert Richter interrupt-parent = <&gic>; 648ca5b3410SRobert Richter interrupts = <0x0 0x4e 0x4>; 649ca5b3410SRobert Richter }; 650ca5b3410SRobert Richter 651ca5b3410SRobert Richter serial3: serial@1c023000 { 652ca5b3410SRobert Richter status = "disabled"; 653ca5b3410SRobert Richter device_type = "serial"; 654ca5b3410SRobert Richter compatible = "ns16550a"; 655ca5b3410SRobert Richter reg = <0 0x1c023000 0x0 0x1000>; 656ca5b3410SRobert Richter reg-shift = <2>; 657ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 658ca5b3410SRobert Richter interrupt-parent = <&gic>; 659ca5b3410SRobert Richter interrupts = <0x0 0x4f 0x4>; 660ca5b3410SRobert Richter }; 661ca5b3410SRobert Richter 662ca5b3410SRobert Richter phy1: phy@1f21a000 { 663ca5b3410SRobert Richter compatible = "apm,xgene-phy"; 664ca5b3410SRobert Richter reg = <0x0 0x1f21a000 0x0 0x100>; 665ca5b3410SRobert Richter #phy-cells = <1>; 666ca5b3410SRobert Richter clocks = <&sataphy1clk 0>; 667ca5b3410SRobert Richter status = "disabled"; 668ca5b3410SRobert Richter apm,tx-boost-gain = <30 30 30 30 30 30>; 669ca5b3410SRobert Richter apm,tx-eye-tuning = <2 10 10 2 10 10>; 670ca5b3410SRobert Richter }; 671ca5b3410SRobert Richter 672ca5b3410SRobert Richter phy2: phy@1f22a000 { 673ca5b3410SRobert Richter compatible = "apm,xgene-phy"; 674ca5b3410SRobert Richter reg = <0x0 0x1f22a000 0x0 0x100>; 675ca5b3410SRobert Richter #phy-cells = <1>; 676ca5b3410SRobert Richter clocks = <&sataphy2clk 0>; 677ca5b3410SRobert Richter status = "ok"; 678ca5b3410SRobert Richter apm,tx-boost-gain = <30 30 30 30 30 30>; 679ca5b3410SRobert Richter apm,tx-eye-tuning = <1 10 10 2 10 10>; 680ca5b3410SRobert Richter }; 681ca5b3410SRobert Richter 682ca5b3410SRobert Richter phy3: phy@1f23a000 { 683ca5b3410SRobert Richter compatible = "apm,xgene-phy"; 684ca5b3410SRobert Richter reg = <0x0 0x1f23a000 0x0 0x100>; 685ca5b3410SRobert Richter #phy-cells = <1>; 686ca5b3410SRobert Richter clocks = <&sataphy3clk 0>; 687ca5b3410SRobert Richter status = "ok"; 688ca5b3410SRobert Richter apm,tx-boost-gain = <31 31 31 31 31 31>; 689ca5b3410SRobert Richter apm,tx-eye-tuning = <2 10 10 2 10 10>; 690ca5b3410SRobert Richter }; 691ca5b3410SRobert Richter 692ca5b3410SRobert Richter sata1: sata@1a000000 { 693ca5b3410SRobert Richter compatible = "apm,xgene-ahci"; 694ca5b3410SRobert Richter reg = <0x0 0x1a000000 0x0 0x1000>, 695ca5b3410SRobert Richter <0x0 0x1f210000 0x0 0x1000>, 696ca5b3410SRobert Richter <0x0 0x1f21d000 0x0 0x1000>, 697ca5b3410SRobert Richter <0x0 0x1f21e000 0x0 0x1000>, 698ca5b3410SRobert Richter <0x0 0x1f217000 0x0 0x1000>; 699ca5b3410SRobert Richter interrupts = <0x0 0x86 0x4>; 700ca5b3410SRobert Richter dma-coherent; 701ca5b3410SRobert Richter status = "disabled"; 702ca5b3410SRobert Richter clocks = <&sata01clk 0>; 703ca5b3410SRobert Richter phys = <&phy1 0>; 704ca5b3410SRobert Richter phy-names = "sata-phy"; 705ca5b3410SRobert Richter }; 706ca5b3410SRobert Richter 707ca5b3410SRobert Richter sata2: sata@1a400000 { 708ca5b3410SRobert Richter compatible = "apm,xgene-ahci"; 709ca5b3410SRobert Richter reg = <0x0 0x1a400000 0x0 0x1000>, 710ca5b3410SRobert Richter <0x0 0x1f220000 0x0 0x1000>, 711ca5b3410SRobert Richter <0x0 0x1f22d000 0x0 0x1000>, 712ca5b3410SRobert Richter <0x0 0x1f22e000 0x0 0x1000>, 713ca5b3410SRobert Richter <0x0 0x1f227000 0x0 0x1000>; 714ca5b3410SRobert Richter interrupts = <0x0 0x87 0x4>; 715ca5b3410SRobert Richter dma-coherent; 716ca5b3410SRobert Richter status = "ok"; 717ca5b3410SRobert Richter clocks = <&sata23clk 0>; 718ca5b3410SRobert Richter phys = <&phy2 0>; 719ca5b3410SRobert Richter phy-names = "sata-phy"; 720ca5b3410SRobert Richter }; 721ca5b3410SRobert Richter 722ca5b3410SRobert Richter sata3: sata@1a800000 { 723ca5b3410SRobert Richter compatible = "apm,xgene-ahci"; 724ca5b3410SRobert Richter reg = <0x0 0x1a800000 0x0 0x1000>, 725ca5b3410SRobert Richter <0x0 0x1f230000 0x0 0x1000>, 726ca5b3410SRobert Richter <0x0 0x1f23d000 0x0 0x1000>, 727ca5b3410SRobert Richter <0x0 0x1f23e000 0x0 0x1000>; 728ca5b3410SRobert Richter interrupts = <0x0 0x88 0x4>; 729ca5b3410SRobert Richter dma-coherent; 730ca5b3410SRobert Richter status = "ok"; 731ca5b3410SRobert Richter clocks = <&sata45clk 0>; 732ca5b3410SRobert Richter phys = <&phy3 0>; 733ca5b3410SRobert Richter phy-names = "sata-phy"; 734ca5b3410SRobert Richter }; 735ca5b3410SRobert Richter 736ea21feb3SY Vo sbgpio: sbgpio@17001000{ 737ea21feb3SY Vo compatible = "apm,xgene-gpio-sb"; 738ea21feb3SY Vo reg = <0x0 0x17001000 0x0 0x400>; 739ea21feb3SY Vo #gpio-cells = <2>; 740ea21feb3SY Vo gpio-controller; 741ea21feb3SY Vo interrupts = <0x0 0x28 0x1>, 742ea21feb3SY Vo <0x0 0x29 0x1>, 743ea21feb3SY Vo <0x0 0x2a 0x1>, 744ea21feb3SY Vo <0x0 0x2b 0x1>, 745ea21feb3SY Vo <0x0 0x2c 0x1>, 746ea21feb3SY Vo <0x0 0x2d 0x1>; 747ea21feb3SY Vo }; 748ea21feb3SY Vo 749ca5b3410SRobert Richter rtc: rtc@10510000 { 750ca5b3410SRobert Richter compatible = "apm,xgene-rtc"; 751ca5b3410SRobert Richter reg = <0x0 0x10510000 0x0 0x400>; 752ca5b3410SRobert Richter interrupts = <0x0 0x46 0x4>; 753ca5b3410SRobert Richter #clock-cells = <1>; 754ca5b3410SRobert Richter clocks = <&rtcclk 0>; 755ca5b3410SRobert Richter }; 756ca5b3410SRobert Richter 757ca5b3410SRobert Richter menet: ethernet@17020000 { 758ca5b3410SRobert Richter compatible = "apm,xgene-enet"; 759ca5b3410SRobert Richter status = "disabled"; 760ca5b3410SRobert Richter reg = <0x0 0x17020000 0x0 0xd100>, 7616c9e9247SLinus Torvalds <0x0 0X17030000 0x0 0Xc300>, 762ca5b3410SRobert Richter <0x0 0X10000000 0x0 0X200>; 763ca5b3410SRobert Richter reg-names = "enet_csr", "ring_csr", "ring_cmd"; 764ca5b3410SRobert Richter interrupts = <0x0 0x3c 0x4>; 765ca5b3410SRobert Richter dma-coherent; 766ca5b3410SRobert Richter clocks = <&menetclk 0>; 767ca5b3410SRobert Richter /* mac address will be overwritten by the bootloader */ 768ca5b3410SRobert Richter local-mac-address = [00 00 00 00 00 00]; 769ca5b3410SRobert Richter phy-connection-type = "rgmii"; 770ca5b3410SRobert Richter phy-handle = <&menetphy>; 771ca5b3410SRobert Richter mdio { 772ca5b3410SRobert Richter compatible = "apm,xgene-mdio"; 773ca5b3410SRobert Richter #address-cells = <1>; 774ca5b3410SRobert Richter #size-cells = <0>; 775ca5b3410SRobert Richter menetphy: menetphy@3 { 776ca5b3410SRobert Richter compatible = "ethernet-phy-id001c.c915"; 777ca5b3410SRobert Richter reg = <0x3>; 778ca5b3410SRobert Richter }; 779ca5b3410SRobert Richter 780ca5b3410SRobert Richter }; 781ca5b3410SRobert Richter }; 782ca5b3410SRobert Richter 783ca5b3410SRobert Richter sgenet0: ethernet@1f210000 { 7842a91eb72SIyappan Subramanian compatible = "apm,xgene1-sgenet"; 785ca5b3410SRobert Richter status = "disabled"; 7866c9e9247SLinus Torvalds reg = <0x0 0x1f210000 0x0 0xd100>, 7876c9e9247SLinus Torvalds <0x0 0x1f200000 0x0 0Xc300>, 7886c9e9247SLinus Torvalds <0x0 0x1B000000 0x0 0X200>; 789ca5b3410SRobert Richter reg-names = "enet_csr", "ring_csr", "ring_cmd"; 790d3134649SIyappan Subramanian interrupts = <0x0 0xA0 0x4>, 791d3134649SIyappan Subramanian <0x0 0xA1 0x4>; 792ca5b3410SRobert Richter dma-coherent; 793ca5b3410SRobert Richter clocks = <&sge0clk 0>; 794ca5b3410SRobert Richter local-mac-address = [00 00 00 00 00 00]; 795ca5b3410SRobert Richter phy-connection-type = "sgmii"; 796ca5b3410SRobert Richter }; 797ca5b3410SRobert Richter 7982d33394eSKeyur Chudgar sgenet1: ethernet@1f210030 { 7992d33394eSKeyur Chudgar compatible = "apm,xgene1-sgenet"; 8002d33394eSKeyur Chudgar status = "disabled"; 8012d33394eSKeyur Chudgar reg = <0x0 0x1f210030 0x0 0xd100>, 8022d33394eSKeyur Chudgar <0x0 0x1f200000 0x0 0Xc300>, 8032d33394eSKeyur Chudgar <0x0 0x1B000000 0x0 0X8000>; 8042d33394eSKeyur Chudgar reg-names = "enet_csr", "ring_csr", "ring_cmd"; 805d3134649SIyappan Subramanian interrupts = <0x0 0xAC 0x4>, 806d3134649SIyappan Subramanian <0x0 0xAD 0x4>; 8072d33394eSKeyur Chudgar port-id = <1>; 8082d33394eSKeyur Chudgar dma-coherent; 8092d33394eSKeyur Chudgar clocks = <&sge1clk 0>; 8102d33394eSKeyur Chudgar local-mac-address = [00 00 00 00 00 00]; 8112d33394eSKeyur Chudgar phy-connection-type = "sgmii"; 8122d33394eSKeyur Chudgar }; 8132d33394eSKeyur Chudgar 814ca5b3410SRobert Richter xgenet: ethernet@1f610000 { 8152a91eb72SIyappan Subramanian compatible = "apm,xgene1-xgenet"; 816ca5b3410SRobert Richter status = "disabled"; 817ca5b3410SRobert Richter reg = <0x0 0x1f610000 0x0 0xd100>, 8186c9e9247SLinus Torvalds <0x0 0x1f600000 0x0 0Xc300>, 819ca5b3410SRobert Richter <0x0 0x18000000 0x0 0X200>; 820ca5b3410SRobert Richter reg-names = "enet_csr", "ring_csr", "ring_cmd"; 821d3134649SIyappan Subramanian interrupts = <0x0 0x60 0x4>, 822d3134649SIyappan Subramanian <0x0 0x61 0x4>; 823ca5b3410SRobert Richter dma-coherent; 824ca5b3410SRobert Richter clocks = <&xge0clk 0>; 825ca5b3410SRobert Richter /* mac address will be overwritten by the bootloader */ 826ca5b3410SRobert Richter local-mac-address = [00 00 00 00 00 00]; 827ca5b3410SRobert Richter phy-connection-type = "xgmii"; 828ca5b3410SRobert Richter }; 829ca5b3410SRobert Richter 830e63c7a09SIyappan Subramanian xgenet1: ethernet@1f620000 { 831e63c7a09SIyappan Subramanian compatible = "apm,xgene1-xgenet"; 832e63c7a09SIyappan Subramanian status = "disabled"; 833e63c7a09SIyappan Subramanian reg = <0x0 0x1f620000 0x0 0xd100>, 834e63c7a09SIyappan Subramanian <0x0 0x1f600000 0x0 0Xc300>, 835e63c7a09SIyappan Subramanian <0x0 0x18000000 0x0 0X8000>; 836e63c7a09SIyappan Subramanian reg-names = "enet_csr", "ring_csr", "ring_cmd"; 837e63c7a09SIyappan Subramanian interrupts = <0x0 0x6C 0x4>, 838e63c7a09SIyappan Subramanian <0x0 0x6D 0x4>; 839e63c7a09SIyappan Subramanian port-id = <1>; 840e63c7a09SIyappan Subramanian dma-coherent; 841e63c7a09SIyappan Subramanian clocks = <&xge1clk 0>; 842e63c7a09SIyappan Subramanian /* mac address will be overwritten by the bootloader */ 843e63c7a09SIyappan Subramanian local-mac-address = [00 00 00 00 00 00]; 844e63c7a09SIyappan Subramanian phy-connection-type = "xgmii"; 845e63c7a09SIyappan Subramanian }; 846e63c7a09SIyappan Subramanian 847ca5b3410SRobert Richter rng: rng@10520000 { 848ca5b3410SRobert Richter compatible = "apm,xgene-rng"; 849ca5b3410SRobert Richter reg = <0x0 0x10520000 0x0 0x100>; 850ca5b3410SRobert Richter interrupts = <0x0 0x41 0x4>; 851ca5b3410SRobert Richter clocks = <&rngpkaclk 0>; 852ca5b3410SRobert Richter }; 85374e353e1SRameshwar Prasad Sahu 85474e353e1SRameshwar Prasad Sahu dma: dma@1f270000 { 85574e353e1SRameshwar Prasad Sahu compatible = "apm,xgene-storm-dma"; 85674e353e1SRameshwar Prasad Sahu device_type = "dma"; 85774e353e1SRameshwar Prasad Sahu reg = <0x0 0x1f270000 0x0 0x10000>, 85874e353e1SRameshwar Prasad Sahu <0x0 0x1f200000 0x0 0x10000>, 859cda8e937SRameshwar Prasad Sahu <0x0 0x1b000000 0x0 0x400000>, 86074e353e1SRameshwar Prasad Sahu <0x0 0x1054a000 0x0 0x100>; 86174e353e1SRameshwar Prasad Sahu interrupts = <0x0 0x82 0x4>, 86274e353e1SRameshwar Prasad Sahu <0x0 0xb8 0x4>, 86374e353e1SRameshwar Prasad Sahu <0x0 0xb9 0x4>, 86474e353e1SRameshwar Prasad Sahu <0x0 0xba 0x4>, 86574e353e1SRameshwar Prasad Sahu <0x0 0xbb 0x4>; 86674e353e1SRameshwar Prasad Sahu dma-coherent; 86774e353e1SRameshwar Prasad Sahu clocks = <&dmaclk 0>; 86874e353e1SRameshwar Prasad Sahu }; 869ca5b3410SRobert Richter }; 870ca5b3410SRobert Richter}; 871