1ca5b3410SRobert Richter/* 2ca5b3410SRobert Richter * dts file for AppliedMicro (APM) X-Gene Storm SOC 3ca5b3410SRobert Richter * 4ca5b3410SRobert Richter * Copyright (C) 2013, Applied Micro Circuits Corporation 5ca5b3410SRobert Richter * 6ca5b3410SRobert Richter * This program is free software; you can redistribute it and/or 7ca5b3410SRobert Richter * modify it under the terms of the GNU General Public License as 8ca5b3410SRobert Richter * published by the Free Software Foundation; either version 2 of 9ca5b3410SRobert Richter * the License, or (at your option) any later version. 10ca5b3410SRobert Richter */ 11ca5b3410SRobert Richter 12ca5b3410SRobert Richter/ { 13ca5b3410SRobert Richter compatible = "apm,xgene-storm"; 14ca5b3410SRobert Richter interrupt-parent = <&gic>; 15ca5b3410SRobert Richter #address-cells = <2>; 16ca5b3410SRobert Richter #size-cells = <2>; 17ca5b3410SRobert Richter 18ca5b3410SRobert Richter cpus { 19ca5b3410SRobert Richter #address-cells = <2>; 20ca5b3410SRobert Richter #size-cells = <0>; 21ca5b3410SRobert Richter 22ca5b3410SRobert Richter cpu@000 { 23ca5b3410SRobert Richter device_type = "cpu"; 24ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 25ca5b3410SRobert Richter reg = <0x0 0x000>; 26ca5b3410SRobert Richter enable-method = "spin-table"; 27ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 288000bc3fSDuc Dang next-level-cache = <&xgene_L2_0>; 29ca5b3410SRobert Richter }; 30ca5b3410SRobert Richter cpu@001 { 31ca5b3410SRobert Richter device_type = "cpu"; 32ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 33ca5b3410SRobert Richter reg = <0x0 0x001>; 34ca5b3410SRobert Richter enable-method = "spin-table"; 35ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 368000bc3fSDuc Dang next-level-cache = <&xgene_L2_0>; 37ca5b3410SRobert Richter }; 38ca5b3410SRobert Richter cpu@100 { 39ca5b3410SRobert Richter device_type = "cpu"; 40ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 41ca5b3410SRobert Richter reg = <0x0 0x100>; 42ca5b3410SRobert Richter enable-method = "spin-table"; 43ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 448000bc3fSDuc Dang next-level-cache = <&xgene_L2_1>; 45ca5b3410SRobert Richter }; 46ca5b3410SRobert Richter cpu@101 { 47ca5b3410SRobert Richter device_type = "cpu"; 48ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 49ca5b3410SRobert Richter reg = <0x0 0x101>; 50ca5b3410SRobert Richter enable-method = "spin-table"; 51ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 528000bc3fSDuc Dang next-level-cache = <&xgene_L2_1>; 53ca5b3410SRobert Richter }; 54ca5b3410SRobert Richter cpu@200 { 55ca5b3410SRobert Richter device_type = "cpu"; 56ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 57ca5b3410SRobert Richter reg = <0x0 0x200>; 58ca5b3410SRobert Richter enable-method = "spin-table"; 59ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 608000bc3fSDuc Dang next-level-cache = <&xgene_L2_2>; 61ca5b3410SRobert Richter }; 62ca5b3410SRobert Richter cpu@201 { 63ca5b3410SRobert Richter device_type = "cpu"; 64ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 65ca5b3410SRobert Richter reg = <0x0 0x201>; 66ca5b3410SRobert Richter enable-method = "spin-table"; 67ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 688000bc3fSDuc Dang next-level-cache = <&xgene_L2_2>; 69ca5b3410SRobert Richter }; 70ca5b3410SRobert Richter cpu@300 { 71ca5b3410SRobert Richter device_type = "cpu"; 72ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 73ca5b3410SRobert Richter reg = <0x0 0x300>; 74ca5b3410SRobert Richter enable-method = "spin-table"; 75ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 768000bc3fSDuc Dang next-level-cache = <&xgene_L2_3>; 77ca5b3410SRobert Richter }; 78ca5b3410SRobert Richter cpu@301 { 79ca5b3410SRobert Richter device_type = "cpu"; 80ca5b3410SRobert Richter compatible = "apm,potenza", "arm,armv8"; 81ca5b3410SRobert Richter reg = <0x0 0x301>; 82ca5b3410SRobert Richter enable-method = "spin-table"; 83ca5b3410SRobert Richter cpu-release-addr = <0x1 0x0000fff8>; 848000bc3fSDuc Dang next-level-cache = <&xgene_L2_3>; 858000bc3fSDuc Dang }; 868000bc3fSDuc Dang xgene_L2_0: l2-cache-0 { 878000bc3fSDuc Dang compatible = "cache"; 888000bc3fSDuc Dang }; 898000bc3fSDuc Dang xgene_L2_1: l2-cache-1 { 908000bc3fSDuc Dang compatible = "cache"; 918000bc3fSDuc Dang }; 928000bc3fSDuc Dang xgene_L2_2: l2-cache-2 { 938000bc3fSDuc Dang compatible = "cache"; 948000bc3fSDuc Dang }; 958000bc3fSDuc Dang xgene_L2_3: l2-cache-3 { 968000bc3fSDuc Dang compatible = "cache"; 97ca5b3410SRobert Richter }; 98ca5b3410SRobert Richter }; 99ca5b3410SRobert Richter 100ca5b3410SRobert Richter gic: interrupt-controller@78010000 { 101ca5b3410SRobert Richter compatible = "arm,cortex-a15-gic"; 102ca5b3410SRobert Richter #interrupt-cells = <3>; 103ca5b3410SRobert Richter interrupt-controller; 104ca5b3410SRobert Richter reg = <0x0 0x78010000 0x0 0x1000>, /* GIC Dist */ 105ca5b3410SRobert Richter <0x0 0x78020000 0x0 0x1000>, /* GIC CPU */ 106ca5b3410SRobert Richter <0x0 0x78040000 0x0 0x2000>, /* GIC VCPU Control */ 107ca5b3410SRobert Richter <0x0 0x78060000 0x0 0x2000>; /* GIC VCPU */ 108ca5b3410SRobert Richter interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 109ca5b3410SRobert Richter }; 110ca5b3410SRobert Richter 111ca5b3410SRobert Richter timer { 112ca5b3410SRobert Richter compatible = "arm,armv8-timer"; 113ca5b3410SRobert Richter interrupts = <1 0 0xff01>, /* Secure Phys IRQ */ 114ca5b3410SRobert Richter <1 13 0xff01>, /* Non-secure Phys IRQ */ 115ca5b3410SRobert Richter <1 14 0xff01>, /* Virt IRQ */ 116ca5b3410SRobert Richter <1 15 0xff01>; /* Hyp IRQ */ 117ca5b3410SRobert Richter clock-frequency = <50000000>; 118ca5b3410SRobert Richter }; 119ca5b3410SRobert Richter 1207434f42bSFeng Kan pmu { 1217434f42bSFeng Kan compatible = "apm,potenza-pmu", "arm,armv8-pmuv3"; 1227434f42bSFeng Kan interrupts = <1 12 0xff04>; 1237434f42bSFeng Kan }; 1247434f42bSFeng Kan 125ca5b3410SRobert Richter soc { 126ca5b3410SRobert Richter compatible = "simple-bus"; 127ca5b3410SRobert Richter #address-cells = <2>; 128ca5b3410SRobert Richter #size-cells = <2>; 129ca5b3410SRobert Richter ranges; 13074e353e1SRameshwar Prasad Sahu dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>; 131ca5b3410SRobert Richter 132ca5b3410SRobert Richter clocks { 133ca5b3410SRobert Richter #address-cells = <2>; 134ca5b3410SRobert Richter #size-cells = <2>; 135ca5b3410SRobert Richter ranges; 136ca5b3410SRobert Richter refclk: refclk { 137ca5b3410SRobert Richter compatible = "fixed-clock"; 138ca5b3410SRobert Richter #clock-cells = <1>; 139ca5b3410SRobert Richter clock-frequency = <100000000>; 140ca5b3410SRobert Richter clock-output-names = "refclk"; 141ca5b3410SRobert Richter }; 142ca5b3410SRobert Richter 143ca5b3410SRobert Richter pcppll: pcppll@17000100 { 144ca5b3410SRobert Richter compatible = "apm,xgene-pcppll-clock"; 145ca5b3410SRobert Richter #clock-cells = <1>; 146ca5b3410SRobert Richter clocks = <&refclk 0>; 147ca5b3410SRobert Richter clock-names = "pcppll"; 148ca5b3410SRobert Richter reg = <0x0 0x17000100 0x0 0x1000>; 149ca5b3410SRobert Richter clock-output-names = "pcppll"; 150ca5b3410SRobert Richter type = <0>; 151ca5b3410SRobert Richter }; 152ca5b3410SRobert Richter 153ca5b3410SRobert Richter socpll: socpll@17000120 { 154ca5b3410SRobert Richter compatible = "apm,xgene-socpll-clock"; 155ca5b3410SRobert Richter #clock-cells = <1>; 156ca5b3410SRobert Richter clocks = <&refclk 0>; 157ca5b3410SRobert Richter clock-names = "socpll"; 158ca5b3410SRobert Richter reg = <0x0 0x17000120 0x0 0x1000>; 159ca5b3410SRobert Richter clock-output-names = "socpll"; 160ca5b3410SRobert Richter type = <1>; 161ca5b3410SRobert Richter }; 162ca5b3410SRobert Richter 163ca5b3410SRobert Richter socplldiv2: socplldiv2 { 164ca5b3410SRobert Richter compatible = "fixed-factor-clock"; 165ca5b3410SRobert Richter #clock-cells = <1>; 166ca5b3410SRobert Richter clocks = <&socpll 0>; 167ca5b3410SRobert Richter clock-names = "socplldiv2"; 168ca5b3410SRobert Richter clock-mult = <1>; 169ca5b3410SRobert Richter clock-div = <2>; 170ca5b3410SRobert Richter clock-output-names = "socplldiv2"; 171ca5b3410SRobert Richter }; 172ca5b3410SRobert Richter 173b0e7a85aSDuc Dang ahbclk: ahbclk@17000000 { 1748f74e861SSuman Tripathi compatible = "apm,xgene-device-clock"; 1758f74e861SSuman Tripathi #clock-cells = <1>; 1768f74e861SSuman Tripathi clocks = <&socplldiv2 0>; 177b0e7a85aSDuc Dang reg = <0x0 0x17000000 0x0 0x2000>; 178b0e7a85aSDuc Dang reg-names = "div-reg"; 1798f74e861SSuman Tripathi divider-offset = <0x164>; 1808f74e861SSuman Tripathi divider-width = <0x5>; 1818f74e861SSuman Tripathi divider-shift = <0x0>; 1828f74e861SSuman Tripathi clock-output-names = "ahbclk"; 1838f74e861SSuman Tripathi }; 1848f74e861SSuman Tripathi 1858f74e861SSuman Tripathi sdioclk: sdioclk@1f2ac000 { 1868f74e861SSuman Tripathi compatible = "apm,xgene-device-clock"; 1878f74e861SSuman Tripathi #clock-cells = <1>; 1888f74e861SSuman Tripathi clocks = <&socplldiv2 0>; 1898f74e861SSuman Tripathi reg = <0x0 0x1f2ac000 0x0 0x1000 1908f74e861SSuman Tripathi 0x0 0x17000000 0x0 0x2000>; 1918f74e861SSuman Tripathi reg-names = "csr-reg", "div-reg"; 1928f74e861SSuman Tripathi csr-offset = <0x0>; 1938f74e861SSuman Tripathi csr-mask = <0x2>; 1948f74e861SSuman Tripathi enable-offset = <0x8>; 1958f74e861SSuman Tripathi enable-mask = <0x2>; 1968f74e861SSuman Tripathi divider-offset = <0x178>; 1978f74e861SSuman Tripathi divider-width = <0x8>; 1988f74e861SSuman Tripathi divider-shift = <0x0>; 1998f74e861SSuman Tripathi clock-output-names = "sdioclk"; 2008f74e861SSuman Tripathi }; 2018f74e861SSuman Tripathi 202ca5b3410SRobert Richter ethclk: ethclk { 203ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 204ca5b3410SRobert Richter #clock-cells = <1>; 205ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 206ca5b3410SRobert Richter clock-names = "ethclk"; 207ca5b3410SRobert Richter reg = <0x0 0x17000000 0x0 0x1000>; 208ca5b3410SRobert Richter reg-names = "div-reg"; 209ca5b3410SRobert Richter divider-offset = <0x238>; 210ca5b3410SRobert Richter divider-width = <0x9>; 211ca5b3410SRobert Richter divider-shift = <0x0>; 212ca5b3410SRobert Richter clock-output-names = "ethclk"; 213ca5b3410SRobert Richter }; 214ca5b3410SRobert Richter 215ca5b3410SRobert Richter menetclk: menetclk { 216ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 217ca5b3410SRobert Richter #clock-cells = <1>; 218ca5b3410SRobert Richter clocks = <ðclk 0>; 219cafc4cd0SBjorn Helgaas reg = <0x0 0x1702c000 0x0 0x1000>; 220ca5b3410SRobert Richter reg-names = "csr-reg"; 221ca5b3410SRobert Richter clock-output-names = "menetclk"; 222ca5b3410SRobert Richter }; 223ca5b3410SRobert Richter 224ca5b3410SRobert Richter sge0clk: sge0clk@1f21c000 { 225ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 226ca5b3410SRobert Richter #clock-cells = <1>; 227ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 228ca5b3410SRobert Richter reg = <0x0 0x1f21c000 0x0 0x1000>; 229ca5b3410SRobert Richter reg-names = "csr-reg"; 2308e694cd2SIyappan Subramanian csr-mask = <0xa>; 2318e694cd2SIyappan Subramanian enable-mask = <0xf>; 232ca5b3410SRobert Richter clock-output-names = "sge0clk"; 233ca5b3410SRobert Richter }; 234ca5b3410SRobert Richter 235ca5b3410SRobert Richter xge0clk: xge0clk@1f61c000 { 236ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 237ca5b3410SRobert Richter #clock-cells = <1>; 238ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 239ca5b3410SRobert Richter reg = <0x0 0x1f61c000 0x0 0x1000>; 240ca5b3410SRobert Richter reg-names = "csr-reg"; 241ca5b3410SRobert Richter csr-mask = <0x3>; 242ca5b3410SRobert Richter clock-output-names = "xge0clk"; 243ca5b3410SRobert Richter }; 244ca5b3410SRobert Richter 245e63c7a09SIyappan Subramanian xge1clk: xge1clk@1f62c000 { 246e63c7a09SIyappan Subramanian compatible = "apm,xgene-device-clock"; 247e63c7a09SIyappan Subramanian status = "disabled"; 248e63c7a09SIyappan Subramanian #clock-cells = <1>; 249e63c7a09SIyappan Subramanian clocks = <&socplldiv2 0>; 250e63c7a09SIyappan Subramanian reg = <0x0 0x1f62c000 0x0 0x1000>; 251e63c7a09SIyappan Subramanian reg-names = "csr-reg"; 252e63c7a09SIyappan Subramanian csr-mask = <0x3>; 253e63c7a09SIyappan Subramanian clock-output-names = "xge1clk"; 254e63c7a09SIyappan Subramanian }; 255e63c7a09SIyappan Subramanian 256ca5b3410SRobert Richter sataphy1clk: sataphy1clk@1f21c000 { 257ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 258ca5b3410SRobert Richter #clock-cells = <1>; 259ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 260ca5b3410SRobert Richter reg = <0x0 0x1f21c000 0x0 0x1000>; 261ca5b3410SRobert Richter reg-names = "csr-reg"; 262ca5b3410SRobert Richter clock-output-names = "sataphy1clk"; 263ca5b3410SRobert Richter status = "disabled"; 264ca5b3410SRobert Richter csr-offset = <0x4>; 265ca5b3410SRobert Richter csr-mask = <0x00>; 266ca5b3410SRobert Richter enable-offset = <0x0>; 267ca5b3410SRobert Richter enable-mask = <0x06>; 268ca5b3410SRobert Richter }; 269ca5b3410SRobert Richter 270ca5b3410SRobert Richter sataphy2clk: sataphy1clk@1f22c000 { 271ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 272ca5b3410SRobert Richter #clock-cells = <1>; 273ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 274ca5b3410SRobert Richter reg = <0x0 0x1f22c000 0x0 0x1000>; 275ca5b3410SRobert Richter reg-names = "csr-reg"; 276ca5b3410SRobert Richter clock-output-names = "sataphy2clk"; 277ca5b3410SRobert Richter status = "ok"; 278ca5b3410SRobert Richter csr-offset = <0x4>; 279ca5b3410SRobert Richter csr-mask = <0x3a>; 280ca5b3410SRobert Richter enable-offset = <0x0>; 281ca5b3410SRobert Richter enable-mask = <0x06>; 282ca5b3410SRobert Richter }; 283ca5b3410SRobert Richter 284ca5b3410SRobert Richter sataphy3clk: sataphy1clk@1f23c000 { 285ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 286ca5b3410SRobert Richter #clock-cells = <1>; 287ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 288ca5b3410SRobert Richter reg = <0x0 0x1f23c000 0x0 0x1000>; 289ca5b3410SRobert Richter reg-names = "csr-reg"; 290ca5b3410SRobert Richter clock-output-names = "sataphy3clk"; 291ca5b3410SRobert Richter status = "ok"; 292ca5b3410SRobert Richter csr-offset = <0x4>; 293ca5b3410SRobert Richter csr-mask = <0x3a>; 294ca5b3410SRobert Richter enable-offset = <0x0>; 295ca5b3410SRobert Richter enable-mask = <0x06>; 296ca5b3410SRobert Richter }; 297ca5b3410SRobert Richter 298ca5b3410SRobert Richter sata01clk: sata01clk@1f21c000 { 299ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 300ca5b3410SRobert Richter #clock-cells = <1>; 301ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 302ca5b3410SRobert Richter reg = <0x0 0x1f21c000 0x0 0x1000>; 303ca5b3410SRobert Richter reg-names = "csr-reg"; 304ca5b3410SRobert Richter clock-output-names = "sata01clk"; 305ca5b3410SRobert Richter csr-offset = <0x4>; 306ca5b3410SRobert Richter csr-mask = <0x05>; 307ca5b3410SRobert Richter enable-offset = <0x0>; 308ca5b3410SRobert Richter enable-mask = <0x39>; 309ca5b3410SRobert Richter }; 310ca5b3410SRobert Richter 311ca5b3410SRobert Richter sata23clk: sata23clk@1f22c000 { 312ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 313ca5b3410SRobert Richter #clock-cells = <1>; 314ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 315ca5b3410SRobert Richter reg = <0x0 0x1f22c000 0x0 0x1000>; 316ca5b3410SRobert Richter reg-names = "csr-reg"; 317ca5b3410SRobert Richter clock-output-names = "sata23clk"; 318ca5b3410SRobert Richter csr-offset = <0x4>; 319ca5b3410SRobert Richter csr-mask = <0x05>; 320ca5b3410SRobert Richter enable-offset = <0x0>; 321ca5b3410SRobert Richter enable-mask = <0x39>; 322ca5b3410SRobert Richter }; 323ca5b3410SRobert Richter 324ca5b3410SRobert Richter sata45clk: sata45clk@1f23c000 { 325ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 326ca5b3410SRobert Richter #clock-cells = <1>; 327ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 328ca5b3410SRobert Richter reg = <0x0 0x1f23c000 0x0 0x1000>; 329ca5b3410SRobert Richter reg-names = "csr-reg"; 330ca5b3410SRobert Richter clock-output-names = "sata45clk"; 331ca5b3410SRobert Richter csr-offset = <0x4>; 332ca5b3410SRobert Richter csr-mask = <0x05>; 333ca5b3410SRobert Richter enable-offset = <0x0>; 334ca5b3410SRobert Richter enable-mask = <0x39>; 335ca5b3410SRobert Richter }; 336ca5b3410SRobert Richter 337ca5b3410SRobert Richter rtcclk: rtcclk@17000000 { 338ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 339ca5b3410SRobert Richter #clock-cells = <1>; 340ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 341ca5b3410SRobert Richter reg = <0x0 0x17000000 0x0 0x2000>; 342ca5b3410SRobert Richter reg-names = "csr-reg"; 343ca5b3410SRobert Richter csr-offset = <0xc>; 344ca5b3410SRobert Richter csr-mask = <0x2>; 345ca5b3410SRobert Richter enable-offset = <0x10>; 346ca5b3410SRobert Richter enable-mask = <0x2>; 347ca5b3410SRobert Richter clock-output-names = "rtcclk"; 348ca5b3410SRobert Richter }; 349ca5b3410SRobert Richter 350ca5b3410SRobert Richter rngpkaclk: rngpkaclk@17000000 { 351ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 352ca5b3410SRobert Richter #clock-cells = <1>; 353ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 354ca5b3410SRobert Richter reg = <0x0 0x17000000 0x0 0x2000>; 355ca5b3410SRobert Richter reg-names = "csr-reg"; 356ca5b3410SRobert Richter csr-offset = <0xc>; 357ca5b3410SRobert Richter csr-mask = <0x10>; 358ca5b3410SRobert Richter enable-offset = <0x10>; 359ca5b3410SRobert Richter enable-mask = <0x10>; 360ca5b3410SRobert Richter clock-output-names = "rngpkaclk"; 361ca5b3410SRobert Richter }; 362ca5b3410SRobert Richter 363ca5b3410SRobert Richter pcie0clk: pcie0clk@1f2bc000 { 364ca5b3410SRobert Richter status = "disabled"; 365ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 366ca5b3410SRobert Richter #clock-cells = <1>; 367ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 368ca5b3410SRobert Richter reg = <0x0 0x1f2bc000 0x0 0x1000>; 369ca5b3410SRobert Richter reg-names = "csr-reg"; 370ca5b3410SRobert Richter clock-output-names = "pcie0clk"; 371ca5b3410SRobert Richter }; 372ca5b3410SRobert Richter 373ca5b3410SRobert Richter pcie1clk: pcie1clk@1f2cc000 { 374ca5b3410SRobert Richter status = "disabled"; 375ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 376ca5b3410SRobert Richter #clock-cells = <1>; 377ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 378ca5b3410SRobert Richter reg = <0x0 0x1f2cc000 0x0 0x1000>; 379ca5b3410SRobert Richter reg-names = "csr-reg"; 380ca5b3410SRobert Richter clock-output-names = "pcie1clk"; 381ca5b3410SRobert Richter }; 382ca5b3410SRobert Richter 383ca5b3410SRobert Richter pcie2clk: pcie2clk@1f2dc000 { 384ca5b3410SRobert Richter status = "disabled"; 385ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 386ca5b3410SRobert Richter #clock-cells = <1>; 387ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 388ca5b3410SRobert Richter reg = <0x0 0x1f2dc000 0x0 0x1000>; 389ca5b3410SRobert Richter reg-names = "csr-reg"; 390ca5b3410SRobert Richter clock-output-names = "pcie2clk"; 391ca5b3410SRobert Richter }; 392ca5b3410SRobert Richter 393ca5b3410SRobert Richter pcie3clk: pcie3clk@1f50c000 { 394ca5b3410SRobert Richter status = "disabled"; 395ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 396ca5b3410SRobert Richter #clock-cells = <1>; 397ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 398ca5b3410SRobert Richter reg = <0x0 0x1f50c000 0x0 0x1000>; 399ca5b3410SRobert Richter reg-names = "csr-reg"; 400ca5b3410SRobert Richter clock-output-names = "pcie3clk"; 401ca5b3410SRobert Richter }; 402ca5b3410SRobert Richter 403ca5b3410SRobert Richter pcie4clk: pcie4clk@1f51c000 { 404ca5b3410SRobert Richter status = "disabled"; 405ca5b3410SRobert Richter compatible = "apm,xgene-device-clock"; 406ca5b3410SRobert Richter #clock-cells = <1>; 407ca5b3410SRobert Richter clocks = <&socplldiv2 0>; 408ca5b3410SRobert Richter reg = <0x0 0x1f51c000 0x0 0x1000>; 409ca5b3410SRobert Richter reg-names = "csr-reg"; 410ca5b3410SRobert Richter clock-output-names = "pcie4clk"; 411ca5b3410SRobert Richter }; 41274e353e1SRameshwar Prasad Sahu 41374e353e1SRameshwar Prasad Sahu dmaclk: dmaclk@1f27c000 { 41474e353e1SRameshwar Prasad Sahu compatible = "apm,xgene-device-clock"; 41574e353e1SRameshwar Prasad Sahu #clock-cells = <1>; 41674e353e1SRameshwar Prasad Sahu clocks = <&socplldiv2 0>; 41774e353e1SRameshwar Prasad Sahu reg = <0x0 0x1f27c000 0x0 0x1000>; 41874e353e1SRameshwar Prasad Sahu reg-names = "csr-reg"; 41974e353e1SRameshwar Prasad Sahu clock-output-names = "dmaclk"; 42074e353e1SRameshwar Prasad Sahu }; 421ca5b3410SRobert Richter }; 422ca5b3410SRobert Richter 423e1e6e5c4SDuc Dang msi: msi@79000000 { 424e1e6e5c4SDuc Dang compatible = "apm,xgene1-msi"; 425e1e6e5c4SDuc Dang msi-controller; 426e1e6e5c4SDuc Dang reg = <0x00 0x79000000 0x0 0x900000>; 427e1e6e5c4SDuc Dang interrupts = < 0x0 0x10 0x4 428e1e6e5c4SDuc Dang 0x0 0x11 0x4 429e1e6e5c4SDuc Dang 0x0 0x12 0x4 430e1e6e5c4SDuc Dang 0x0 0x13 0x4 431e1e6e5c4SDuc Dang 0x0 0x14 0x4 432e1e6e5c4SDuc Dang 0x0 0x15 0x4 433e1e6e5c4SDuc Dang 0x0 0x16 0x4 434e1e6e5c4SDuc Dang 0x0 0x17 0x4 435e1e6e5c4SDuc Dang 0x0 0x18 0x4 436e1e6e5c4SDuc Dang 0x0 0x19 0x4 437e1e6e5c4SDuc Dang 0x0 0x1a 0x4 438e1e6e5c4SDuc Dang 0x0 0x1b 0x4 439e1e6e5c4SDuc Dang 0x0 0x1c 0x4 440e1e6e5c4SDuc Dang 0x0 0x1d 0x4 441e1e6e5c4SDuc Dang 0x0 0x1e 0x4 442e1e6e5c4SDuc Dang 0x0 0x1f 0x4>; 443e1e6e5c4SDuc Dang }; 444e1e6e5c4SDuc Dang 4455c3a87e3SFeng Kan scu: system-clk-controller@17000000 { 4465c3a87e3SFeng Kan compatible = "apm,xgene-scu","syscon"; 4475c3a87e3SFeng Kan reg = <0x0 0x17000000 0x0 0x400>; 4485c3a87e3SFeng Kan }; 4495c3a87e3SFeng Kan 4505c3a87e3SFeng Kan reboot: reboot@17000014 { 4515c3a87e3SFeng Kan compatible = "syscon-reboot"; 4525c3a87e3SFeng Kan regmap = <&scu>; 4535c3a87e3SFeng Kan offset = <0x14>; 4545c3a87e3SFeng Kan mask = <0x1>; 4555c3a87e3SFeng Kan }; 4565c3a87e3SFeng Kan 4578f2ae6f3SLoc Ho csw: csw@7e200000 { 4588f2ae6f3SLoc Ho compatible = "apm,xgene-csw", "syscon"; 4598f2ae6f3SLoc Ho reg = <0x0 0x7e200000 0x0 0x1000>; 4608f2ae6f3SLoc Ho }; 4618f2ae6f3SLoc Ho 4628f2ae6f3SLoc Ho mcba: mcba@7e700000 { 4638f2ae6f3SLoc Ho compatible = "apm,xgene-mcb", "syscon"; 4648f2ae6f3SLoc Ho reg = <0x0 0x7e700000 0x0 0x1000>; 4658f2ae6f3SLoc Ho }; 4668f2ae6f3SLoc Ho 4678f2ae6f3SLoc Ho mcbb: mcbb@7e720000 { 4688f2ae6f3SLoc Ho compatible = "apm,xgene-mcb", "syscon"; 4698f2ae6f3SLoc Ho reg = <0x0 0x7e720000 0x0 0x1000>; 4708f2ae6f3SLoc Ho }; 4718f2ae6f3SLoc Ho 4728f2ae6f3SLoc Ho efuse: efuse@1054a000 { 4738f2ae6f3SLoc Ho compatible = "apm,xgene-efuse", "syscon"; 4748f2ae6f3SLoc Ho reg = <0x0 0x1054a000 0x0 0x20>; 4758f2ae6f3SLoc Ho }; 4768f2ae6f3SLoc Ho 477f5793c97SLoc Ho rb: rb@7e000000 { 478f5793c97SLoc Ho compatible = "apm,xgene-rb", "syscon"; 479f5793c97SLoc Ho reg = <0x0 0x7e000000 0x0 0x10>; 480f5793c97SLoc Ho }; 481f5793c97SLoc Ho 4828f2ae6f3SLoc Ho edac@78800000 { 4838f2ae6f3SLoc Ho compatible = "apm,xgene-edac"; 4848f2ae6f3SLoc Ho #address-cells = <2>; 4858f2ae6f3SLoc Ho #size-cells = <2>; 4868f2ae6f3SLoc Ho ranges; 4878f2ae6f3SLoc Ho regmap-csw = <&csw>; 4888f2ae6f3SLoc Ho regmap-mcba = <&mcba>; 4898f2ae6f3SLoc Ho regmap-mcbb = <&mcbb>; 4908f2ae6f3SLoc Ho regmap-efuse = <&efuse>; 491f5793c97SLoc Ho regmap-rb = <&rb>; 4928f2ae6f3SLoc Ho reg = <0x0 0x78800000 0x0 0x100>; 4938f2ae6f3SLoc Ho interrupts = <0x0 0x20 0x4>, 4948f2ae6f3SLoc Ho <0x0 0x21 0x4>, 4958f2ae6f3SLoc Ho <0x0 0x27 0x4>; 4968f2ae6f3SLoc Ho 4978f2ae6f3SLoc Ho edacmc@7e800000 { 4988f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 4998f2ae6f3SLoc Ho reg = <0x0 0x7e800000 0x0 0x1000>; 5008f2ae6f3SLoc Ho memory-controller = <0>; 5018f2ae6f3SLoc Ho }; 5028f2ae6f3SLoc Ho 5038f2ae6f3SLoc Ho edacmc@7e840000 { 5048f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 5058f2ae6f3SLoc Ho reg = <0x0 0x7e840000 0x0 0x1000>; 5068f2ae6f3SLoc Ho memory-controller = <1>; 5078f2ae6f3SLoc Ho }; 5088f2ae6f3SLoc Ho 5098f2ae6f3SLoc Ho edacmc@7e880000 { 5108f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 5118f2ae6f3SLoc Ho reg = <0x0 0x7e880000 0x0 0x1000>; 5128f2ae6f3SLoc Ho memory-controller = <2>; 5138f2ae6f3SLoc Ho }; 5148f2ae6f3SLoc Ho 5158f2ae6f3SLoc Ho edacmc@7e8c0000 { 5168f2ae6f3SLoc Ho compatible = "apm,xgene-edac-mc"; 5178f2ae6f3SLoc Ho reg = <0x0 0x7e8c0000 0x0 0x1000>; 5188f2ae6f3SLoc Ho memory-controller = <3>; 5198f2ae6f3SLoc Ho }; 5208f2ae6f3SLoc Ho 5218f2ae6f3SLoc Ho edacpmd@7c000000 { 5228f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 5238f2ae6f3SLoc Ho reg = <0x0 0x7c000000 0x0 0x200000>; 5248f2ae6f3SLoc Ho pmd-controller = <0>; 5258f2ae6f3SLoc Ho }; 5268f2ae6f3SLoc Ho 5278f2ae6f3SLoc Ho edacpmd@7c200000 { 5288f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 5298f2ae6f3SLoc Ho reg = <0x0 0x7c200000 0x0 0x200000>; 5308f2ae6f3SLoc Ho pmd-controller = <1>; 5318f2ae6f3SLoc Ho }; 5328f2ae6f3SLoc Ho 5338f2ae6f3SLoc Ho edacpmd@7c400000 { 5348f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 5358f2ae6f3SLoc Ho reg = <0x0 0x7c400000 0x0 0x200000>; 5368f2ae6f3SLoc Ho pmd-controller = <2>; 5378f2ae6f3SLoc Ho }; 5388f2ae6f3SLoc Ho 5398f2ae6f3SLoc Ho edacpmd@7c600000 { 5408f2ae6f3SLoc Ho compatible = "apm,xgene-edac-pmd"; 5418f2ae6f3SLoc Ho reg = <0x0 0x7c600000 0x0 0x200000>; 5428f2ae6f3SLoc Ho pmd-controller = <3>; 5438f2ae6f3SLoc Ho }; 544043cba96SLoc Ho 545043cba96SLoc Ho edacl3@7e600000 { 546043cba96SLoc Ho compatible = "apm,xgene-edac-l3"; 547043cba96SLoc Ho reg = <0x0 0x7e600000 0x0 0x1000>; 548043cba96SLoc Ho }; 549043cba96SLoc Ho 550043cba96SLoc Ho edacsoc@7e930000 { 551043cba96SLoc Ho compatible = "apm,xgene-edac-soc-v1"; 552043cba96SLoc Ho reg = <0x0 0x7e930000 0x0 0x1000>; 553043cba96SLoc Ho }; 5548f2ae6f3SLoc Ho }; 5558f2ae6f3SLoc Ho 5560317cd52STai Nguyen pmu: pmu@78810000 { 5570317cd52STai Nguyen compatible = "apm,xgene-pmu-v2"; 5580317cd52STai Nguyen #address-cells = <2>; 5590317cd52STai Nguyen #size-cells = <2>; 5600317cd52STai Nguyen ranges; 5610317cd52STai Nguyen regmap-csw = <&csw>; 5620317cd52STai Nguyen regmap-mcba = <&mcba>; 5630317cd52STai Nguyen regmap-mcbb = <&mcbb>; 5640317cd52STai Nguyen reg = <0x0 0x78810000 0x0 0x1000>; 5650317cd52STai Nguyen interrupts = <0x0 0x22 0x4>; 5660317cd52STai Nguyen 5670317cd52STai Nguyen pmul3c@7e610000 { 5680317cd52STai Nguyen compatible = "apm,xgene-pmu-l3c"; 5690317cd52STai Nguyen reg = <0x0 0x7e610000 0x0 0x1000>; 5700317cd52STai Nguyen }; 5710317cd52STai Nguyen 5720317cd52STai Nguyen pmuiob@7e940000 { 5730317cd52STai Nguyen compatible = "apm,xgene-pmu-iob"; 5740317cd52STai Nguyen reg = <0x0 0x7e940000 0x0 0x1000>; 5750317cd52STai Nguyen }; 5760317cd52STai Nguyen 5770317cd52STai Nguyen pmucmcb@7e710000 { 5780317cd52STai Nguyen compatible = "apm,xgene-pmu-mcb"; 5790317cd52STai Nguyen reg = <0x0 0x7e710000 0x0 0x1000>; 5800317cd52STai Nguyen enable-bit-index = <0>; 5810317cd52STai Nguyen }; 5820317cd52STai Nguyen 5830317cd52STai Nguyen pmucmcb@7e730000 { 5840317cd52STai Nguyen compatible = "apm,xgene-pmu-mcb"; 5850317cd52STai Nguyen reg = <0x0 0x7e730000 0x0 0x1000>; 5860317cd52STai Nguyen enable-bit-index = <1>; 5870317cd52STai Nguyen }; 5880317cd52STai Nguyen 5890317cd52STai Nguyen pmucmc@7e810000 { 5900317cd52STai Nguyen compatible = "apm,xgene-pmu-mc"; 5910317cd52STai Nguyen reg = <0x0 0x7e810000 0x0 0x1000>; 5920317cd52STai Nguyen enable-bit-index = <0>; 5930317cd52STai Nguyen }; 5940317cd52STai Nguyen 5950317cd52STai Nguyen pmucmc@7e850000 { 5960317cd52STai Nguyen compatible = "apm,xgene-pmu-mc"; 5970317cd52STai Nguyen reg = <0x0 0x7e850000 0x0 0x1000>; 5980317cd52STai Nguyen enable-bit-index = <1>; 5990317cd52STai Nguyen }; 6000317cd52STai Nguyen 6010317cd52STai Nguyen pmucmc@7e890000 { 6020317cd52STai Nguyen compatible = "apm,xgene-pmu-mc"; 6030317cd52STai Nguyen reg = <0x0 0x7e890000 0x0 0x1000>; 6040317cd52STai Nguyen enable-bit-index = <2>; 6050317cd52STai Nguyen }; 6060317cd52STai Nguyen 6070317cd52STai Nguyen pmucmc@7e8d0000 { 6080317cd52STai Nguyen compatible = "apm,xgene-pmu-mc"; 6090317cd52STai Nguyen reg = <0x0 0x7e8d0000 0x0 0x1000>; 6100317cd52STai Nguyen enable-bit-index = <3>; 6110317cd52STai Nguyen }; 6120317cd52STai Nguyen }; 6130317cd52STai Nguyen 614ca5b3410SRobert Richter pcie0: pcie@1f2b0000 { 615ca5b3410SRobert Richter status = "disabled"; 616ca5b3410SRobert Richter device_type = "pci"; 617ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 618ca5b3410SRobert Richter #interrupt-cells = <1>; 619ca5b3410SRobert Richter #size-cells = <2>; 620ca5b3410SRobert Richter #address-cells = <3>; 621ca5b3410SRobert Richter reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 622ca5b3410SRobert Richter 0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 623ca5b3410SRobert Richter reg-names = "csr", "cfg"; 624ca5b3410SRobert Richter ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ 62580bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000 /* mem */ 62680bb3edaSDuc Dang 0x43000000 0xf0 0x00000000 0xf0 0x00000000 0x10 0x00000000>; /* mem */ 627ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 628ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 629ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 6307c7b08bfSDuc Dang interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4 6317c7b08bfSDuc Dang 0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x4 6327c7b08bfSDuc Dang 0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x4 6337c7b08bfSDuc Dang 0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x4>; 634ca5b3410SRobert Richter dma-coherent; 635ca5b3410SRobert Richter clocks = <&pcie0clk 0>; 636e1e6e5c4SDuc Dang msi-parent = <&msi>; 637ca5b3410SRobert Richter }; 638ca5b3410SRobert Richter 639ca5b3410SRobert Richter pcie1: pcie@1f2c0000 { 640ca5b3410SRobert Richter status = "disabled"; 641ca5b3410SRobert Richter device_type = "pci"; 642ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 643ca5b3410SRobert Richter #interrupt-cells = <1>; 644ca5b3410SRobert Richter #size-cells = <2>; 645ca5b3410SRobert Richter #address-cells = <3>; 646ca5b3410SRobert Richter reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ 647ca5b3410SRobert Richter 0xd0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 648ca5b3410SRobert Richter reg-names = "csr", "cfg"; 64980bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0xd0 0x10000000 0x00 0x00010000 /* io */ 65080bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xd1 0x80000000 0x00 0x80000000 /* mem */ 65180bb3edaSDuc Dang 0x43000000 0xd8 0x00000000 0xd8 0x00000000 0x08 0x00000000>; /* mem */ 652ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 653ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 654ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 6557c7b08bfSDuc Dang interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4 6567c7b08bfSDuc Dang 0x0 0x0 0x0 0x2 &gic 0x0 0xc9 0x4 6577c7b08bfSDuc Dang 0x0 0x0 0x0 0x3 &gic 0x0 0xca 0x4 6587c7b08bfSDuc Dang 0x0 0x0 0x0 0x4 &gic 0x0 0xcb 0x4>; 659ca5b3410SRobert Richter dma-coherent; 660ca5b3410SRobert Richter clocks = <&pcie1clk 0>; 661e1e6e5c4SDuc Dang msi-parent = <&msi>; 662ca5b3410SRobert Richter }; 663ca5b3410SRobert Richter 664ca5b3410SRobert Richter pcie2: pcie@1f2d0000 { 665ca5b3410SRobert Richter status = "disabled"; 666ca5b3410SRobert Richter device_type = "pci"; 667ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 668ca5b3410SRobert Richter #interrupt-cells = <1>; 669ca5b3410SRobert Richter #size-cells = <2>; 670ca5b3410SRobert Richter #address-cells = <3>; 671ca5b3410SRobert Richter reg = < 0x00 0x1f2d0000 0x0 0x00010000 /* Controller registers */ 672ca5b3410SRobert Richter 0x90 0xd0000000 0x0 0x00040000>; /* PCI config space */ 673ca5b3410SRobert Richter reg-names = "csr", "cfg"; 67480bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0x90 0x10000000 0x00 0x00010000 /* io */ 67580bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0x91 0x80000000 0x00 0x80000000 /* mem */ 67680bb3edaSDuc Dang 0x43000000 0x94 0x00000000 0x94 0x00000000 0x04 0x00000000>; /* mem */ 677ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 678ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 679ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 6807c7b08bfSDuc Dang interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4 6817c7b08bfSDuc Dang 0x0 0x0 0x0 0x2 &gic 0x0 0xcf 0x4 6827c7b08bfSDuc Dang 0x0 0x0 0x0 0x3 &gic 0x0 0xd0 0x4 6837c7b08bfSDuc Dang 0x0 0x0 0x0 0x4 &gic 0x0 0xd1 0x4>; 684ca5b3410SRobert Richter dma-coherent; 685ca5b3410SRobert Richter clocks = <&pcie2clk 0>; 686e1e6e5c4SDuc Dang msi-parent = <&msi>; 687ca5b3410SRobert Richter }; 688ca5b3410SRobert Richter 689ca5b3410SRobert Richter pcie3: pcie@1f500000 { 690ca5b3410SRobert Richter status = "disabled"; 691ca5b3410SRobert Richter device_type = "pci"; 692ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 693ca5b3410SRobert Richter #interrupt-cells = <1>; 694ca5b3410SRobert Richter #size-cells = <2>; 695ca5b3410SRobert Richter #address-cells = <3>; 696ca5b3410SRobert Richter reg = < 0x00 0x1f500000 0x0 0x00010000 /* Controller registers */ 697ca5b3410SRobert Richter 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 698ca5b3410SRobert Richter reg-names = "csr", "cfg"; 69980bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ 70080bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xa1 0x80000000 0x00 0x80000000 /* mem */ 70180bb3edaSDuc Dang 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ 702ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 703ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 704ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 7057c7b08bfSDuc Dang interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4 7067c7b08bfSDuc Dang 0x0 0x0 0x0 0x2 &gic 0x0 0xd5 0x4 7077c7b08bfSDuc Dang 0x0 0x0 0x0 0x3 &gic 0x0 0xd6 0x4 7087c7b08bfSDuc Dang 0x0 0x0 0x0 0x4 &gic 0x0 0xd7 0x4>; 709ca5b3410SRobert Richter dma-coherent; 710ca5b3410SRobert Richter clocks = <&pcie3clk 0>; 711e1e6e5c4SDuc Dang msi-parent = <&msi>; 712ca5b3410SRobert Richter }; 713ca5b3410SRobert Richter 714ca5b3410SRobert Richter pcie4: pcie@1f510000 { 715ca5b3410SRobert Richter status = "disabled"; 716ca5b3410SRobert Richter device_type = "pci"; 717ca5b3410SRobert Richter compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; 718ca5b3410SRobert Richter #interrupt-cells = <1>; 719ca5b3410SRobert Richter #size-cells = <2>; 720ca5b3410SRobert Richter #address-cells = <3>; 721ca5b3410SRobert Richter reg = < 0x00 0x1f510000 0x0 0x00010000 /* Controller registers */ 722ca5b3410SRobert Richter 0xc0 0xd0000000 0x0 0x00200000>; /* PCI config space */ 723ca5b3410SRobert Richter reg-names = "csr", "cfg"; 72480bb3edaSDuc Dang ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ 72580bb3edaSDuc Dang 0x02000000 0x00 0x80000000 0xc1 0x80000000 0x00 0x80000000 /* mem */ 72680bb3edaSDuc Dang 0x43000000 0xc8 0x00000000 0xc8 0x00000000 0x08 0x00000000>; /* mem */ 727ca5b3410SRobert Richter dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 728ca5b3410SRobert Richter 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 729ca5b3410SRobert Richter interrupt-map-mask = <0x0 0x0 0x0 0x7>; 7307c7b08bfSDuc Dang interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4 7317c7b08bfSDuc Dang 0x0 0x0 0x0 0x2 &gic 0x0 0xdb 0x4 7327c7b08bfSDuc Dang 0x0 0x0 0x0 0x3 &gic 0x0 0xdc 0x4 7337c7b08bfSDuc Dang 0x0 0x0 0x0 0x4 &gic 0x0 0xdd 0x4>; 734ca5b3410SRobert Richter dma-coherent; 735ca5b3410SRobert Richter clocks = <&pcie4clk 0>; 736e1e6e5c4SDuc Dang msi-parent = <&msi>; 737ca5b3410SRobert Richter }; 738ca5b3410SRobert Richter 739b0e4563cSDuc Dang mailbox: mailbox@10540000 { 740b0e4563cSDuc Dang compatible = "apm,xgene-slimpro-mbox"; 741b0e4563cSDuc Dang reg = <0x0 0x10540000 0x0 0xa000>; 742b0e4563cSDuc Dang #mbox-cells = <1>; 743b0e4563cSDuc Dang interrupts = <0x0 0x0 0x4>, 744b0e4563cSDuc Dang <0x0 0x1 0x4>, 745b0e4563cSDuc Dang <0x0 0x2 0x4>, 746b0e4563cSDuc Dang <0x0 0x3 0x4>, 747b0e4563cSDuc Dang <0x0 0x4 0x4>, 748b0e4563cSDuc Dang <0x0 0x5 0x4>, 749b0e4563cSDuc Dang <0x0 0x6 0x4>, 750b0e4563cSDuc Dang <0x0 0x7 0x4>; 751b0e4563cSDuc Dang }; 752b0e4563cSDuc Dang 753778b5cbcSDuc Dang i2cslimpro { 754778b5cbcSDuc Dang compatible = "apm,xgene-slimpro-i2c"; 755778b5cbcSDuc Dang mboxes = <&mailbox 0>; 756778b5cbcSDuc Dang }; 757778b5cbcSDuc Dang 758c6d62be5Shotran hwmonslimpro { 759c6d62be5Shotran compatible = "apm,xgene-slimpro-hwmon"; 760c6d62be5Shotran mboxes = <&mailbox 7>; 761c6d62be5Shotran }; 762c6d62be5Shotran 763ca5b3410SRobert Richter serial0: serial@1c020000 { 764ca5b3410SRobert Richter status = "disabled"; 765ca5b3410SRobert Richter device_type = "serial"; 766ca5b3410SRobert Richter compatible = "ns16550a"; 767ca5b3410SRobert Richter reg = <0 0x1c020000 0x0 0x1000>; 768ca5b3410SRobert Richter reg-shift = <2>; 769ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 770ca5b3410SRobert Richter interrupt-parent = <&gic>; 771ca5b3410SRobert Richter interrupts = <0x0 0x4c 0x4>; 772ca5b3410SRobert Richter }; 773ca5b3410SRobert Richter 774ca5b3410SRobert Richter serial1: serial@1c021000 { 775ca5b3410SRobert Richter status = "disabled"; 776ca5b3410SRobert Richter device_type = "serial"; 777ca5b3410SRobert Richter compatible = "ns16550a"; 778ca5b3410SRobert Richter reg = <0 0x1c021000 0x0 0x1000>; 779ca5b3410SRobert Richter reg-shift = <2>; 780ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 781ca5b3410SRobert Richter interrupt-parent = <&gic>; 782ca5b3410SRobert Richter interrupts = <0x0 0x4d 0x4>; 783ca5b3410SRobert Richter }; 784ca5b3410SRobert Richter 785ca5b3410SRobert Richter serial2: serial@1c022000 { 786ca5b3410SRobert Richter status = "disabled"; 787ca5b3410SRobert Richter device_type = "serial"; 788ca5b3410SRobert Richter compatible = "ns16550a"; 789ca5b3410SRobert Richter reg = <0 0x1c022000 0x0 0x1000>; 790ca5b3410SRobert Richter reg-shift = <2>; 791ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 792ca5b3410SRobert Richter interrupt-parent = <&gic>; 793ca5b3410SRobert Richter interrupts = <0x0 0x4e 0x4>; 794ca5b3410SRobert Richter }; 795ca5b3410SRobert Richter 796ca5b3410SRobert Richter serial3: serial@1c023000 { 797ca5b3410SRobert Richter status = "disabled"; 798ca5b3410SRobert Richter device_type = "serial"; 799ca5b3410SRobert Richter compatible = "ns16550a"; 800ca5b3410SRobert Richter reg = <0 0x1c023000 0x0 0x1000>; 801ca5b3410SRobert Richter reg-shift = <2>; 802ca5b3410SRobert Richter clock-frequency = <10000000>; /* Updated by bootloader */ 803ca5b3410SRobert Richter interrupt-parent = <&gic>; 804ca5b3410SRobert Richter interrupts = <0x0 0x4f 0x4>; 805ca5b3410SRobert Richter }; 806ca5b3410SRobert Richter 8078f74e861SSuman Tripathi mmc0: mmc@1c000000 { 8088f74e861SSuman Tripathi compatible = "arasan,sdhci-4.9a"; 8098f74e861SSuman Tripathi reg = <0x0 0x1c000000 0x0 0x100>; 8108f74e861SSuman Tripathi interrupts = <0x0 0x49 0x4>; 8118f74e861SSuman Tripathi dma-coherent; 8128f74e861SSuman Tripathi no-1-8-v; 8138f74e861SSuman Tripathi clock-names = "clk_xin", "clk_ahb"; 8148f74e861SSuman Tripathi clocks = <&sdioclk 0>, <&ahbclk 0>; 8158f74e861SSuman Tripathi }; 8168f74e861SSuman Tripathi 81793beff2cSDuc Dang gfcgpio: gpio0@1701c000 { 8180a09223fSDuc Dang compatible = "apm,xgene-gpio"; 8190a09223fSDuc Dang reg = <0x0 0x1701c000 0x0 0x40>; 8200a09223fSDuc Dang gpio-controller; 8210a09223fSDuc Dang #gpio-cells = <2>; 8220a09223fSDuc Dang }; 8230a09223fSDuc Dang 82493beff2cSDuc Dang dwgpio: gpio@1c024000 { 825e38ec5b9SDuc Dang compatible = "snps,dw-apb-gpio"; 826e38ec5b9SDuc Dang reg = <0x0 0x1c024000 0x0 0x1000>; 827e38ec5b9SDuc Dang reg-io-width = <4>; 828e38ec5b9SDuc Dang #address-cells = <1>; 829e38ec5b9SDuc Dang #size-cells = <0>; 830e38ec5b9SDuc Dang 831e38ec5b9SDuc Dang porta: gpio-controller@0 { 832e38ec5b9SDuc Dang compatible = "snps,dw-apb-gpio-port"; 833e38ec5b9SDuc Dang gpio-controller; 834e38ec5b9SDuc Dang snps,nr-gpios = <32>; 835e38ec5b9SDuc Dang reg = <0>; 836e38ec5b9SDuc Dang }; 837e38ec5b9SDuc Dang }; 838e38ec5b9SDuc Dang 83993beff2cSDuc Dang i2c0: i2c@10512000 { 84062ff9683SDuc Dang status = "disabled"; 84162ff9683SDuc Dang #address-cells = <1>; 84262ff9683SDuc Dang #size-cells = <0>; 84362ff9683SDuc Dang compatible = "snps,designware-i2c"; 84462ff9683SDuc Dang reg = <0x0 0x10512000 0x0 0x1000>; 84562ff9683SDuc Dang interrupts = <0 0x44 0x4>; 84662ff9683SDuc Dang #clock-cells = <1>; 8470fe8588fSDuc Dang clocks = <&ahbclk 0>; 84862ff9683SDuc Dang bus_num = <0>; 84962ff9683SDuc Dang }; 85062ff9683SDuc Dang 851ca5b3410SRobert Richter phy1: phy@1f21a000 { 852ca5b3410SRobert Richter compatible = "apm,xgene-phy"; 853ca5b3410SRobert Richter reg = <0x0 0x1f21a000 0x0 0x100>; 854ca5b3410SRobert Richter #phy-cells = <1>; 855ca5b3410SRobert Richter clocks = <&sataphy1clk 0>; 856ca5b3410SRobert Richter status = "disabled"; 857ca5b3410SRobert Richter apm,tx-boost-gain = <30 30 30 30 30 30>; 858ca5b3410SRobert Richter apm,tx-eye-tuning = <2 10 10 2 10 10>; 859ca5b3410SRobert Richter }; 860ca5b3410SRobert Richter 861ca5b3410SRobert Richter phy2: phy@1f22a000 { 862ca5b3410SRobert Richter compatible = "apm,xgene-phy"; 863ca5b3410SRobert Richter reg = <0x0 0x1f22a000 0x0 0x100>; 864ca5b3410SRobert Richter #phy-cells = <1>; 865ca5b3410SRobert Richter clocks = <&sataphy2clk 0>; 866ca5b3410SRobert Richter status = "ok"; 867ca5b3410SRobert Richter apm,tx-boost-gain = <30 30 30 30 30 30>; 868ca5b3410SRobert Richter apm,tx-eye-tuning = <1 10 10 2 10 10>; 869ca5b3410SRobert Richter }; 870ca5b3410SRobert Richter 871ca5b3410SRobert Richter phy3: phy@1f23a000 { 872ca5b3410SRobert Richter compatible = "apm,xgene-phy"; 873ca5b3410SRobert Richter reg = <0x0 0x1f23a000 0x0 0x100>; 874ca5b3410SRobert Richter #phy-cells = <1>; 875ca5b3410SRobert Richter clocks = <&sataphy3clk 0>; 876ca5b3410SRobert Richter status = "ok"; 877ca5b3410SRobert Richter apm,tx-boost-gain = <31 31 31 31 31 31>; 878ca5b3410SRobert Richter apm,tx-eye-tuning = <2 10 10 2 10 10>; 879ca5b3410SRobert Richter }; 880ca5b3410SRobert Richter 881ca5b3410SRobert Richter sata1: sata@1a000000 { 882ca5b3410SRobert Richter compatible = "apm,xgene-ahci"; 883ca5b3410SRobert Richter reg = <0x0 0x1a000000 0x0 0x1000>, 884ca5b3410SRobert Richter <0x0 0x1f210000 0x0 0x1000>, 885ca5b3410SRobert Richter <0x0 0x1f21d000 0x0 0x1000>, 886ca5b3410SRobert Richter <0x0 0x1f21e000 0x0 0x1000>, 887ca5b3410SRobert Richter <0x0 0x1f217000 0x0 0x1000>; 888ca5b3410SRobert Richter interrupts = <0x0 0x86 0x4>; 889ca5b3410SRobert Richter dma-coherent; 890ca5b3410SRobert Richter status = "disabled"; 891ca5b3410SRobert Richter clocks = <&sata01clk 0>; 892ca5b3410SRobert Richter phys = <&phy1 0>; 893ca5b3410SRobert Richter phy-names = "sata-phy"; 894ca5b3410SRobert Richter }; 895ca5b3410SRobert Richter 896ca5b3410SRobert Richter sata2: sata@1a400000 { 897ca5b3410SRobert Richter compatible = "apm,xgene-ahci"; 898ca5b3410SRobert Richter reg = <0x0 0x1a400000 0x0 0x1000>, 899ca5b3410SRobert Richter <0x0 0x1f220000 0x0 0x1000>, 900ca5b3410SRobert Richter <0x0 0x1f22d000 0x0 0x1000>, 901ca5b3410SRobert Richter <0x0 0x1f22e000 0x0 0x1000>, 902ca5b3410SRobert Richter <0x0 0x1f227000 0x0 0x1000>; 903ca5b3410SRobert Richter interrupts = <0x0 0x87 0x4>; 904ca5b3410SRobert Richter dma-coherent; 905ca5b3410SRobert Richter status = "ok"; 906ca5b3410SRobert Richter clocks = <&sata23clk 0>; 907ca5b3410SRobert Richter phys = <&phy2 0>; 908ca5b3410SRobert Richter phy-names = "sata-phy"; 909ca5b3410SRobert Richter }; 910ca5b3410SRobert Richter 911ca5b3410SRobert Richter sata3: sata@1a800000 { 912ca5b3410SRobert Richter compatible = "apm,xgene-ahci"; 913ca5b3410SRobert Richter reg = <0x0 0x1a800000 0x0 0x1000>, 914ca5b3410SRobert Richter <0x0 0x1f230000 0x0 0x1000>, 915ca5b3410SRobert Richter <0x0 0x1f23d000 0x0 0x1000>, 916ca5b3410SRobert Richter <0x0 0x1f23e000 0x0 0x1000>; 917ca5b3410SRobert Richter interrupts = <0x0 0x88 0x4>; 918ca5b3410SRobert Richter dma-coherent; 919ca5b3410SRobert Richter status = "ok"; 920ca5b3410SRobert Richter clocks = <&sata45clk 0>; 921ca5b3410SRobert Richter phys = <&phy3 0>; 922ca5b3410SRobert Richter phy-names = "sata-phy"; 923ca5b3410SRobert Richter }; 924ca5b3410SRobert Richter 925bd410233SDuc Dang /* Do not change dwusb name, coded for backward compatibility */ 926bd410233SDuc Dang usb0: dwusb@19000000 { 927bd410233SDuc Dang status = "disabled"; 928bd410233SDuc Dang compatible = "snps,dwc3"; 929bd410233SDuc Dang reg = <0x0 0x19000000 0x0 0x100000>; 930bd410233SDuc Dang interrupts = <0x0 0x89 0x4>; 931bd410233SDuc Dang dma-coherent; 932bd410233SDuc Dang dr_mode = "host"; 933bd410233SDuc Dang }; 934bd410233SDuc Dang 935bd410233SDuc Dang usb1: dwusb@19800000 { 936bd410233SDuc Dang status = "disabled"; 937bd410233SDuc Dang compatible = "snps,dwc3"; 938bd410233SDuc Dang reg = <0x0 0x19800000 0x0 0x100000>; 939bd410233SDuc Dang interrupts = <0x0 0x8a 0x4>; 940bd410233SDuc Dang dma-coherent; 941bd410233SDuc Dang dr_mode = "host"; 942bd410233SDuc Dang }; 943bd410233SDuc Dang 94493beff2cSDuc Dang sbgpio: gpio@17001000{ 945ea21feb3SY Vo compatible = "apm,xgene-gpio-sb"; 946ea21feb3SY Vo reg = <0x0 0x17001000 0x0 0x400>; 947ea21feb3SY Vo #gpio-cells = <2>; 948ea21feb3SY Vo gpio-controller; 949ea21feb3SY Vo interrupts = <0x0 0x28 0x1>, 950ea21feb3SY Vo <0x0 0x29 0x1>, 951ea21feb3SY Vo <0x0 0x2a 0x1>, 952ea21feb3SY Vo <0x0 0x2b 0x1>, 953ea21feb3SY Vo <0x0 0x2c 0x1>, 954ea21feb3SY Vo <0x0 0x2d 0x1>; 95547f134a2SQuan Nguyen interrupt-parent = <&gic>; 95647f134a2SQuan Nguyen #interrupt-cells = <2>; 95747f134a2SQuan Nguyen interrupt-controller; 958ea21feb3SY Vo }; 959ea21feb3SY Vo 960ca5b3410SRobert Richter rtc: rtc@10510000 { 961ca5b3410SRobert Richter compatible = "apm,xgene-rtc"; 962ca5b3410SRobert Richter reg = <0x0 0x10510000 0x0 0x400>; 963ca5b3410SRobert Richter interrupts = <0x0 0x46 0x4>; 964ca5b3410SRobert Richter #clock-cells = <1>; 965ca5b3410SRobert Richter clocks = <&rtcclk 0>; 966ca5b3410SRobert Richter }; 967ca5b3410SRobert Richter 9688e694cd2SIyappan Subramanian mdio: mdio@17020000 { 9698e694cd2SIyappan Subramanian compatible = "apm,xgene-mdio-rgmii"; 9708e694cd2SIyappan Subramanian #address-cells = <1>; 9718e694cd2SIyappan Subramanian #size-cells = <0>; 9728e694cd2SIyappan Subramanian reg = <0x0 0x17020000 0x0 0xd100>; 9738e694cd2SIyappan Subramanian clocks = <&menetclk 0>; 9748e694cd2SIyappan Subramanian }; 9758e694cd2SIyappan Subramanian 976ca5b3410SRobert Richter menet: ethernet@17020000 { 977ca5b3410SRobert Richter compatible = "apm,xgene-enet"; 978ca5b3410SRobert Richter status = "disabled"; 979ca5b3410SRobert Richter reg = <0x0 0x17020000 0x0 0xd100>, 980cafc4cd0SBjorn Helgaas <0x0 0x17030000 0x0 0xc300>, 981cafc4cd0SBjorn Helgaas <0x0 0x10000000 0x0 0x200>; 982ca5b3410SRobert Richter reg-names = "enet_csr", "ring_csr", "ring_cmd"; 983ca5b3410SRobert Richter interrupts = <0x0 0x3c 0x4>; 984ca5b3410SRobert Richter dma-coherent; 985ca5b3410SRobert Richter clocks = <&menetclk 0>; 986ca5b3410SRobert Richter /* mac address will be overwritten by the bootloader */ 987ca5b3410SRobert Richter local-mac-address = [00 00 00 00 00 00]; 988ca5b3410SRobert Richter phy-connection-type = "rgmii"; 9898e694cd2SIyappan Subramanian phy-handle = <&menet0phy>,<&menetphy>; 990ca5b3410SRobert Richter mdio { 991ca5b3410SRobert Richter compatible = "apm,xgene-mdio"; 992ca5b3410SRobert Richter #address-cells = <1>; 993ca5b3410SRobert Richter #size-cells = <0>; 994ca5b3410SRobert Richter menetphy: menetphy@3 { 995ca5b3410SRobert Richter compatible = "ethernet-phy-id001c.c915"; 996ca5b3410SRobert Richter reg = <0x3>; 997ca5b3410SRobert Richter }; 998ca5b3410SRobert Richter 999ca5b3410SRobert Richter }; 1000ca5b3410SRobert Richter }; 1001ca5b3410SRobert Richter 1002ca5b3410SRobert Richter sgenet0: ethernet@1f210000 { 10032a91eb72SIyappan Subramanian compatible = "apm,xgene1-sgenet"; 1004ca5b3410SRobert Richter status = "disabled"; 10056c9e9247SLinus Torvalds reg = <0x0 0x1f210000 0x0 0xd100>, 1006cafc4cd0SBjorn Helgaas <0x0 0x1f200000 0x0 0xc300>, 1007cafc4cd0SBjorn Helgaas <0x0 0x1b000000 0x0 0x200>; 1008ca5b3410SRobert Richter reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1009cafc4cd0SBjorn Helgaas interrupts = <0x0 0xa0 0x4>, 1010cafc4cd0SBjorn Helgaas <0x0 0xa1 0x4>; 1011ca5b3410SRobert Richter dma-coherent; 1012ca5b3410SRobert Richter clocks = <&sge0clk 0>; 1013ca5b3410SRobert Richter local-mac-address = [00 00 00 00 00 00]; 1014ca5b3410SRobert Richter phy-connection-type = "sgmii"; 10158e694cd2SIyappan Subramanian phy-handle = <&sgenet0phy>; 1016ca5b3410SRobert Richter }; 1017ca5b3410SRobert Richter 10182d33394eSKeyur Chudgar sgenet1: ethernet@1f210030 { 10192d33394eSKeyur Chudgar compatible = "apm,xgene1-sgenet"; 10202d33394eSKeyur Chudgar status = "disabled"; 10212d33394eSKeyur Chudgar reg = <0x0 0x1f210030 0x0 0xd100>, 1022cafc4cd0SBjorn Helgaas <0x0 0x1f200000 0x0 0xc300>, 1023cafc4cd0SBjorn Helgaas <0x0 0x1b000000 0x0 0x8000>; 10242d33394eSKeyur Chudgar reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1025cafc4cd0SBjorn Helgaas interrupts = <0x0 0xac 0x4>, 1026cafc4cd0SBjorn Helgaas <0x0 0xad 0x4>; 10272d33394eSKeyur Chudgar port-id = <1>; 10282d33394eSKeyur Chudgar dma-coherent; 10292d33394eSKeyur Chudgar local-mac-address = [00 00 00 00 00 00]; 10302d33394eSKeyur Chudgar phy-connection-type = "sgmii"; 10318e694cd2SIyappan Subramanian phy-handle = <&sgenet1phy>; 10322d33394eSKeyur Chudgar }; 10332d33394eSKeyur Chudgar 1034ca5b3410SRobert Richter xgenet: ethernet@1f610000 { 10352a91eb72SIyappan Subramanian compatible = "apm,xgene1-xgenet"; 1036ca5b3410SRobert Richter status = "disabled"; 1037ca5b3410SRobert Richter reg = <0x0 0x1f610000 0x0 0xd100>, 1038cafc4cd0SBjorn Helgaas <0x0 0x1f600000 0x0 0xc300>, 1039cafc4cd0SBjorn Helgaas <0x0 0x18000000 0x0 0x200>; 1040ca5b3410SRobert Richter reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1041d3134649SIyappan Subramanian interrupts = <0x0 0x60 0x4>, 10420d2c2515SIyappan Subramanian <0x0 0x61 0x4>, 10430d2c2515SIyappan Subramanian <0x0 0x62 0x4>, 10440d2c2515SIyappan Subramanian <0x0 0x63 0x4>, 10450d2c2515SIyappan Subramanian <0x0 0x64 0x4>, 10460d2c2515SIyappan Subramanian <0x0 0x65 0x4>, 10470d2c2515SIyappan Subramanian <0x0 0x66 0x4>, 10480d2c2515SIyappan Subramanian <0x0 0x67 0x4>; 10496619ac5aSIyappan Subramanian channel = <0>; 1050ca5b3410SRobert Richter dma-coherent; 1051ca5b3410SRobert Richter clocks = <&xge0clk 0>; 1052ca5b3410SRobert Richter /* mac address will be overwritten by the bootloader */ 1053ca5b3410SRobert Richter local-mac-address = [00 00 00 00 00 00]; 1054ca5b3410SRobert Richter phy-connection-type = "xgmii"; 1055ca5b3410SRobert Richter }; 1056ca5b3410SRobert Richter 1057e63c7a09SIyappan Subramanian xgenet1: ethernet@1f620000 { 1058e63c7a09SIyappan Subramanian compatible = "apm,xgene1-xgenet"; 1059e63c7a09SIyappan Subramanian status = "disabled"; 1060e63c7a09SIyappan Subramanian reg = <0x0 0x1f620000 0x0 0xd100>, 1061cafc4cd0SBjorn Helgaas <0x0 0x1f600000 0x0 0xc300>, 1062cafc4cd0SBjorn Helgaas <0x0 0x18000000 0x0 0x8000>; 1063e63c7a09SIyappan Subramanian reg-names = "enet_csr", "ring_csr", "ring_cmd"; 1064cafc4cd0SBjorn Helgaas interrupts = <0x0 0x6c 0x4>, 1065cafc4cd0SBjorn Helgaas <0x0 0x6d 0x4>; 1066e63c7a09SIyappan Subramanian port-id = <1>; 1067e63c7a09SIyappan Subramanian dma-coherent; 1068e63c7a09SIyappan Subramanian clocks = <&xge1clk 0>; 1069e63c7a09SIyappan Subramanian /* mac address will be overwritten by the bootloader */ 1070e63c7a09SIyappan Subramanian local-mac-address = [00 00 00 00 00 00]; 1071e63c7a09SIyappan Subramanian phy-connection-type = "xgmii"; 1072e63c7a09SIyappan Subramanian }; 1073e63c7a09SIyappan Subramanian 1074ca5b3410SRobert Richter rng: rng@10520000 { 1075ca5b3410SRobert Richter compatible = "apm,xgene-rng"; 1076ca5b3410SRobert Richter reg = <0x0 0x10520000 0x0 0x100>; 1077ca5b3410SRobert Richter interrupts = <0x0 0x41 0x4>; 1078ca5b3410SRobert Richter clocks = <&rngpkaclk 0>; 1079ca5b3410SRobert Richter }; 108074e353e1SRameshwar Prasad Sahu 108174e353e1SRameshwar Prasad Sahu dma: dma@1f270000 { 108274e353e1SRameshwar Prasad Sahu compatible = "apm,xgene-storm-dma"; 108374e353e1SRameshwar Prasad Sahu device_type = "dma"; 108474e353e1SRameshwar Prasad Sahu reg = <0x0 0x1f270000 0x0 0x10000>, 108574e353e1SRameshwar Prasad Sahu <0x0 0x1f200000 0x0 0x10000>, 1086cda8e937SRameshwar Prasad Sahu <0x0 0x1b000000 0x0 0x400000>, 108774e353e1SRameshwar Prasad Sahu <0x0 0x1054a000 0x0 0x100>; 108874e353e1SRameshwar Prasad Sahu interrupts = <0x0 0x82 0x4>, 108974e353e1SRameshwar Prasad Sahu <0x0 0xb8 0x4>, 109074e353e1SRameshwar Prasad Sahu <0x0 0xb9 0x4>, 109174e353e1SRameshwar Prasad Sahu <0x0 0xba 0x4>, 109274e353e1SRameshwar Prasad Sahu <0x0 0xbb 0x4>; 109374e353e1SRameshwar Prasad Sahu dma-coherent; 109474e353e1SRameshwar Prasad Sahu clocks = <&dmaclk 0>; 109574e353e1SRameshwar Prasad Sahu }; 1096ca5b3410SRobert Richter }; 1097ca5b3410SRobert Richter}; 1098