1/* 2 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC 3 * 4 * Copyright (C) 2015, Applied Micro Circuits Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12/ { 13 compatible = "apm,xgene-shadowcat"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu@000 { 23 device_type = "cpu"; 24 compatible = "apm,strega", "arm,armv8"; 25 reg = <0x0 0x000>; 26 enable-method = "spin-table"; 27 cpu-release-addr = <0x1 0x0000fff8>; 28 }; 29 cpu@001 { 30 device_type = "cpu"; 31 compatible = "apm,strega", "arm,armv8"; 32 reg = <0x0 0x001>; 33 enable-method = "spin-table"; 34 cpu-release-addr = <0x1 0x0000fff8>; 35 }; 36 cpu@100 { 37 device_type = "cpu"; 38 compatible = "apm,strega", "arm,armv8"; 39 reg = <0x0 0x100>; 40 enable-method = "spin-table"; 41 cpu-release-addr = <0x1 0x0000fff8>; 42 }; 43 cpu@101 { 44 device_type = "cpu"; 45 compatible = "apm,strega", "arm,armv8"; 46 reg = <0x0 0x101>; 47 enable-method = "spin-table"; 48 cpu-release-addr = <0x1 0x0000fff8>; 49 }; 50 cpu@200 { 51 device_type = "cpu"; 52 compatible = "apm,strega", "arm,armv8"; 53 reg = <0x0 0x200>; 54 enable-method = "spin-table"; 55 cpu-release-addr = <0x1 0x0000fff8>; 56 }; 57 cpu@201 { 58 device_type = "cpu"; 59 compatible = "apm,strega", "arm,armv8"; 60 reg = <0x0 0x201>; 61 enable-method = "spin-table"; 62 cpu-release-addr = <0x1 0x0000fff8>; 63 }; 64 cpu@300 { 65 device_type = "cpu"; 66 compatible = "apm,strega", "arm,armv8"; 67 reg = <0x0 0x300>; 68 enable-method = "spin-table"; 69 cpu-release-addr = <0x1 0x0000fff8>; 70 }; 71 cpu@301 { 72 device_type = "cpu"; 73 compatible = "apm,strega", "arm,armv8"; 74 reg = <0x0 0x301>; 75 enable-method = "spin-table"; 76 cpu-release-addr = <0x1 0x0000fff8>; 77 }; 78 }; 79 80 gic: interrupt-controller@78090000 { 81 compatible = "arm,cortex-a15-gic"; 82 #interrupt-cells = <3>; 83 #address-cells = <2>; 84 #size-cells = <2>; 85 interrupt-controller; 86 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 87 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */ 88 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ 89 <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */ 90 <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */ 91 <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */ 92 }; 93 94 pmu { 95 compatible = "arm,armv8-pmuv3"; 96 interrupts = <1 12 0xff04>; 97 }; 98 99 timer { 100 compatible = "arm,armv8-timer"; 101 interrupts = <1 0 0xff04>, /* Secure Phys IRQ */ 102 <1 13 0xff04>, /* Non-secure Phys IRQ */ 103 <1 14 0xff04>, /* Virt IRQ */ 104 <1 15 0xff04>; /* Hyp IRQ */ 105 clock-frequency = <50000000>; 106 }; 107 108 soc { 109 compatible = "simple-bus"; 110 #address-cells = <2>; 111 #size-cells = <2>; 112 ranges; 113 114 clocks { 115 #address-cells = <2>; 116 #size-cells = <2>; 117 ranges; 118 119 refclk: refclk { 120 compatible = "fixed-clock"; 121 #clock-cells = <1>; 122 clock-frequency = <100000000>; 123 clock-output-names = "refclk"; 124 }; 125 126 socpll: socpll@17000120 { 127 compatible = "apm,xgene-socpll-clock"; 128 #clock-cells = <1>; 129 clocks = <&refclk 0>; 130 reg = <0x0 0x17000120 0x0 0x1000>; 131 clock-output-names = "socpll"; 132 }; 133 134 socplldiv2: socplldiv2 { 135 compatible = "fixed-factor-clock"; 136 #clock-cells = <1>; 137 clocks = <&socpll 0>; 138 clock-mult = <1>; 139 clock-div = <2>; 140 clock-output-names = "socplldiv2"; 141 }; 142 143 pcie0clk: pcie0clk@1f2bc000 { 144 compatible = "apm,xgene-device-clock"; 145 #clock-cells = <1>; 146 clocks = <&socplldiv2 0>; 147 reg = <0x0 0x1f2bc000 0x0 0x1000>; 148 reg-names = "csr-reg"; 149 clock-output-names = "pcie0clk"; 150 }; 151 152 xge0clk: xge0clk@1f61c000 { 153 compatible = "apm,xgene-device-clock"; 154 #clock-cells = <1>; 155 clocks = <&socplldiv2 0>; 156 reg = <0x0 0x1f61c000 0x0 0x1000>; 157 reg-names = "csr-reg"; 158 enable-mask = <0x3>; 159 csr-mask = <0x3>; 160 clock-output-names = "xge0clk"; 161 }; 162 163 xge1clk: xge1clk@1f62c000 { 164 compatible = "apm,xgene-device-clock"; 165 #clock-cells = <1>; 166 clocks = <&socplldiv2 0>; 167 reg = <0x0 0x1f62c000 0x0 0x1000>; 168 reg-names = "csr-reg"; 169 enable-mask = <0x3>; 170 csr-mask = <0x3>; 171 clock-output-names = "xge1clk"; 172 }; 173 }; 174 175 scu: system-clk-controller@17000000 { 176 compatible = "apm,xgene-scu","syscon"; 177 reg = <0x0 0x17000000 0x0 0x400>; 178 }; 179 180 reboot: reboot@17000014 { 181 compatible = "syscon-reboot"; 182 regmap = <&scu>; 183 offset = <0x14>; 184 mask = <0x1>; 185 }; 186 187 serial0: serial@10600000 { 188 device_type = "serial"; 189 compatible = "ns16550"; 190 reg = <0 0x10600000 0x0 0x1000>; 191 reg-shift = <2>; 192 clock-frequency = <10000000>; 193 interrupt-parent = <&gic>; 194 interrupts = <0x0 0x4c 0x4>; 195 }; 196 197 sata1: sata@1a000000 { 198 compatible = "apm,xgene-ahci"; 199 reg = <0x0 0x1a000000 0x0 0x1000>, 200 <0x0 0x1f200000 0x0 0x1000>, 201 <0x0 0x1f20d000 0x0 0x1000>, 202 <0x0 0x1f20e000 0x0 0x1000>; 203 interrupts = <0x0 0x5a 0x4>; 204 dma-coherent; 205 }; 206 207 sata2: sata@1a200000 { 208 compatible = "apm,xgene-ahci"; 209 reg = <0x0 0x1a200000 0x0 0x1000>, 210 <0x0 0x1f210000 0x0 0x1000>, 211 <0x0 0x1f21d000 0x0 0x1000>, 212 <0x0 0x1f21e000 0x0 0x1000>; 213 interrupts = <0x0 0x5b 0x4>; 214 dma-coherent; 215 }; 216 217 sata3: sata@1a400000 { 218 compatible = "apm,xgene-ahci"; 219 reg = <0x0 0x1a400000 0x0 0x1000>, 220 <0x0 0x1f220000 0x0 0x1000>, 221 <0x0 0x1f22d000 0x0 0x1000>, 222 <0x0 0x1f22e000 0x0 0x1000>; 223 interrupts = <0x0 0x5c 0x4>; 224 dma-coherent; 225 }; 226 227 sbgpio: sbgpio@17001000{ 228 compatible = "apm,xgene-gpio-sb"; 229 reg = <0x0 0x17001000 0x0 0x400>; 230 #gpio-cells = <2>; 231 gpio-controller; 232 interrupts = <0x0 0x28 0x1>, 233 <0x0 0x29 0x1>, 234 <0x0 0x2a 0x1>, 235 <0x0 0x2b 0x1>, 236 <0x0 0x2c 0x1>, 237 <0x0 0x2d 0x1>, 238 <0x0 0x2e 0x1>, 239 <0x0 0x2f 0x1>; 240 }; 241 242 sgenet0: ethernet@1f610000 { 243 compatible = "apm,xgene2-sgenet"; 244 status = "disabled"; 245 reg = <0x0 0x1f610000 0x0 0x10000>, 246 <0x0 0x1f600000 0x0 0Xd100>, 247 <0x0 0x20000000 0x0 0X20000>; 248 interrupts = <0 96 4>, 249 <0 97 4>; 250 dma-coherent; 251 clocks = <&xge0clk 0>; 252 local-mac-address = [00 01 73 00 00 01]; 253 phy-connection-type = "sgmii"; 254 }; 255 256 xgenet1: ethernet@1f620000 { 257 compatible = "apm,xgene2-xgenet"; 258 status = "disabled"; 259 reg = <0x0 0x1f620000 0x0 0x10000>, 260 <0x0 0x1f600000 0x0 0Xd100>, 261 <0x0 0x20000000 0x0 0X220000>; 262 interrupts = <0 108 4>, 263 <0 109 4>; 264 port-id = <1>; 265 dma-coherent; 266 clocks = <&xge1clk 0>; 267 local-mac-address = [00 01 73 00 00 02]; 268 phy-connection-type = "xgmii"; 269 }; 270 }; 271}; 272