1/* 2 * dts file for AppliedMicro (APM) X-Gene Shadowcat SOC 3 * 4 * Copyright (C) 2015, Applied Micro Circuits Corporation 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12/ { 13 compatible = "apm,xgene-shadowcat"; 14 interrupt-parent = <&gic>; 15 #address-cells = <2>; 16 #size-cells = <2>; 17 18 cpus { 19 #address-cells = <2>; 20 #size-cells = <0>; 21 22 cpu@000 { 23 device_type = "cpu"; 24 compatible = "apm,strega", "arm,armv8"; 25 reg = <0x0 0x000>; 26 enable-method = "spin-table"; 27 cpu-release-addr = <0x1 0x0000fff8>; 28 next-level-cache = <&xgene_L2_0>; 29 }; 30 cpu@001 { 31 device_type = "cpu"; 32 compatible = "apm,strega", "arm,armv8"; 33 reg = <0x0 0x001>; 34 enable-method = "spin-table"; 35 cpu-release-addr = <0x1 0x0000fff8>; 36 next-level-cache = <&xgene_L2_0>; 37 }; 38 cpu@100 { 39 device_type = "cpu"; 40 compatible = "apm,strega", "arm,armv8"; 41 reg = <0x0 0x100>; 42 enable-method = "spin-table"; 43 cpu-release-addr = <0x1 0x0000fff8>; 44 next-level-cache = <&xgene_L2_1>; 45 }; 46 cpu@101 { 47 device_type = "cpu"; 48 compatible = "apm,strega", "arm,armv8"; 49 reg = <0x0 0x101>; 50 enable-method = "spin-table"; 51 cpu-release-addr = <0x1 0x0000fff8>; 52 next-level-cache = <&xgene_L2_1>; 53 }; 54 cpu@200 { 55 device_type = "cpu"; 56 compatible = "apm,strega", "arm,armv8"; 57 reg = <0x0 0x200>; 58 enable-method = "spin-table"; 59 cpu-release-addr = <0x1 0x0000fff8>; 60 next-level-cache = <&xgene_L2_2>; 61 }; 62 cpu@201 { 63 device_type = "cpu"; 64 compatible = "apm,strega", "arm,armv8"; 65 reg = <0x0 0x201>; 66 enable-method = "spin-table"; 67 cpu-release-addr = <0x1 0x0000fff8>; 68 next-level-cache = <&xgene_L2_2>; 69 }; 70 cpu@300 { 71 device_type = "cpu"; 72 compatible = "apm,strega", "arm,armv8"; 73 reg = <0x0 0x300>; 74 enable-method = "spin-table"; 75 cpu-release-addr = <0x1 0x0000fff8>; 76 next-level-cache = <&xgene_L2_3>; 77 }; 78 cpu@301 { 79 device_type = "cpu"; 80 compatible = "apm,strega", "arm,armv8"; 81 reg = <0x0 0x301>; 82 enable-method = "spin-table"; 83 cpu-release-addr = <0x1 0x0000fff8>; 84 next-level-cache = <&xgene_L2_3>; 85 }; 86 xgene_L2_0: l2-cache-0 { 87 compatible = "cache"; 88 }; 89 xgene_L2_1: l2-cache-1 { 90 compatible = "cache"; 91 }; 92 xgene_L2_2: l2-cache-2 { 93 compatible = "cache"; 94 }; 95 xgene_L2_3: l2-cache-3 { 96 compatible = "cache"; 97 }; 98 }; 99 100 gic: interrupt-controller@78090000 { 101 compatible = "arm,cortex-a15-gic"; 102 #interrupt-cells = <3>; 103 #address-cells = <2>; 104 #size-cells = <2>; 105 interrupt-controller; 106 interrupts = <1 9 0xf04>; /* GIC Maintenence IRQ */ 107 ranges = <0 0 0 0x79000000 0x0 0x800000>; /* MSI Range */ 108 reg = <0x0 0x78090000 0x0 0x10000>, /* GIC Dist */ 109 <0x0 0x780A0000 0x0 0x20000>, /* GIC CPU */ 110 <0x0 0x780C0000 0x0 0x10000>, /* GIC VCPU Control */ 111 <0x0 0x780E0000 0x0 0x20000>; /* GIC VCPU */ 112 v2m0: v2m@0x00000 { 113 compatible = "arm,gic-v2m-frame"; 114 msi-controller; 115 reg = <0x0 0x0 0x0 0x1000>; 116 }; 117 v2m1: v2m@0x10000 { 118 compatible = "arm,gic-v2m-frame"; 119 msi-controller; 120 reg = <0x0 0x10000 0x0 0x1000>; 121 }; 122 v2m2: v2m@0x20000 { 123 compatible = "arm,gic-v2m-frame"; 124 msi-controller; 125 reg = <0x0 0x20000 0x0 0x1000>; 126 }; 127 v2m3: v2m@0x30000 { 128 compatible = "arm,gic-v2m-frame"; 129 msi-controller; 130 reg = <0x0 0x30000 0x0 0x1000>; 131 }; 132 v2m4: v2m@0x40000 { 133 compatible = "arm,gic-v2m-frame"; 134 msi-controller; 135 reg = <0x0 0x40000 0x0 0x1000>; 136 }; 137 v2m5: v2m@0x50000 { 138 compatible = "arm,gic-v2m-frame"; 139 msi-controller; 140 reg = <0x0 0x50000 0x0 0x1000>; 141 }; 142 v2m6: v2m@0x60000 { 143 compatible = "arm,gic-v2m-frame"; 144 msi-controller; 145 reg = <0x0 0x60000 0x0 0x1000>; 146 }; 147 v2m7: v2m@0x70000 { 148 compatible = "arm,gic-v2m-frame"; 149 msi-controller; 150 reg = <0x0 0x70000 0x0 0x1000>; 151 }; 152 v2m8: v2m@0x80000 { 153 compatible = "arm,gic-v2m-frame"; 154 msi-controller; 155 reg = <0x0 0x80000 0x0 0x1000>; 156 }; 157 v2m9: v2m@0x90000 { 158 compatible = "arm,gic-v2m-frame"; 159 msi-controller; 160 reg = <0x0 0x90000 0x0 0x1000>; 161 }; 162 v2m10: v2m@0xA0000 { 163 compatible = "arm,gic-v2m-frame"; 164 msi-controller; 165 reg = <0x0 0xA0000 0x0 0x1000>; 166 }; 167 v2m11: v2m@0xB0000 { 168 compatible = "arm,gic-v2m-frame"; 169 msi-controller; 170 reg = <0x0 0xB0000 0x0 0x1000>; 171 }; 172 v2m12: v2m@0xC0000 { 173 compatible = "arm,gic-v2m-frame"; 174 msi-controller; 175 reg = <0x0 0xC0000 0x0 0x1000>; 176 }; 177 v2m13: v2m@0xD0000 { 178 compatible = "arm,gic-v2m-frame"; 179 msi-controller; 180 reg = <0x0 0xD0000 0x0 0x1000>; 181 }; 182 v2m14: v2m@0xE0000 { 183 compatible = "arm,gic-v2m-frame"; 184 msi-controller; 185 reg = <0x0 0xE0000 0x0 0x1000>; 186 }; 187 v2m15: v2m@0xF0000 { 188 compatible = "arm,gic-v2m-frame"; 189 msi-controller; 190 reg = <0x0 0xF0000 0x0 0x1000>; 191 }; 192 }; 193 194 pmu { 195 compatible = "arm,armv8-pmuv3"; 196 interrupts = <1 12 0xff04>; 197 }; 198 199 timer { 200 compatible = "arm,armv8-timer"; 201 interrupts = <1 0 0xff04>, /* Secure Phys IRQ */ 202 <1 13 0xff04>, /* Non-secure Phys IRQ */ 203 <1 14 0xff04>, /* Virt IRQ */ 204 <1 15 0xff04>; /* Hyp IRQ */ 205 clock-frequency = <50000000>; 206 }; 207 208 soc { 209 compatible = "simple-bus"; 210 #address-cells = <2>; 211 #size-cells = <2>; 212 ranges; 213 214 clocks { 215 #address-cells = <2>; 216 #size-cells = <2>; 217 ranges; 218 219 refclk: refclk { 220 compatible = "fixed-clock"; 221 #clock-cells = <1>; 222 clock-frequency = <100000000>; 223 clock-output-names = "refclk"; 224 }; 225 226 socpll: socpll@17000120 { 227 compatible = "apm,xgene-socpll-v2-clock"; 228 #clock-cells = <1>; 229 clocks = <&refclk 0>; 230 reg = <0x0 0x17000120 0x0 0x1000>; 231 clock-output-names = "socpll"; 232 }; 233 234 socplldiv2: socplldiv2 { 235 compatible = "fixed-factor-clock"; 236 #clock-cells = <1>; 237 clocks = <&socpll 0>; 238 clock-mult = <1>; 239 clock-div = <2>; 240 clock-output-names = "socplldiv2"; 241 }; 242 243 ahbclk: ahbclk@17000000 { 244 compatible = "apm,xgene-device-clock"; 245 #clock-cells = <1>; 246 clocks = <&socplldiv2 0>; 247 reg = <0x0 0x17000000 0x0 0x2000>; 248 reg-names = "div-reg"; 249 divider-offset = <0x164>; 250 divider-width = <0x5>; 251 divider-shift = <0x0>; 252 clock-output-names = "ahbclk"; 253 }; 254 255 sbapbclk: sbapbclk@1704c000 { 256 compatible = "apm,xgene-device-clock"; 257 #clock-cells = <1>; 258 clocks = <&ahbclk 0>; 259 reg = <0x0 0x1704c000 0x0 0x2000>; 260 reg-names = "div-reg"; 261 divider-offset = <0x10>; 262 divider-width = <0x2>; 263 divider-shift = <0x0>; 264 clock-output-names = "sbapbclk"; 265 }; 266 267 sdioclk: sdioclk@1f2ac000 { 268 compatible = "apm,xgene-device-clock"; 269 #clock-cells = <1>; 270 clocks = <&socplldiv2 0>; 271 reg = <0x0 0x1f2ac000 0x0 0x1000 272 0x0 0x17000000 0x0 0x2000>; 273 reg-names = "csr-reg", "div-reg"; 274 csr-offset = <0x0>; 275 csr-mask = <0x2>; 276 enable-offset = <0x8>; 277 enable-mask = <0x2>; 278 divider-offset = <0x178>; 279 divider-width = <0x8>; 280 divider-shift = <0x0>; 281 clock-output-names = "sdioclk"; 282 }; 283 284 pcie0clk: pcie0clk@1f2bc000 { 285 compatible = "apm,xgene-device-clock"; 286 #clock-cells = <1>; 287 clocks = <&socplldiv2 0>; 288 reg = <0x0 0x1f2bc000 0x0 0x1000>; 289 reg-names = "csr-reg"; 290 clock-output-names = "pcie0clk"; 291 }; 292 293 pcie1clk: pcie1clk@1f2cc000 { 294 compatible = "apm,xgene-device-clock"; 295 #clock-cells = <1>; 296 clocks = <&socplldiv2 0>; 297 reg = <0x0 0x1f2cc000 0x0 0x1000>; 298 reg-names = "csr-reg"; 299 clock-output-names = "pcie1clk"; 300 }; 301 302 xge0clk: xge0clk@1f61c000 { 303 compatible = "apm,xgene-device-clock"; 304 #clock-cells = <1>; 305 clocks = <&socplldiv2 0>; 306 reg = <0x0 0x1f61c000 0x0 0x1000>; 307 reg-names = "csr-reg"; 308 enable-mask = <0x3>; 309 csr-mask = <0x3>; 310 clock-output-names = "xge0clk"; 311 }; 312 313 xge1clk: xge1clk@1f62c000 { 314 compatible = "apm,xgene-device-clock"; 315 #clock-cells = <1>; 316 clocks = <&socplldiv2 0>; 317 reg = <0x0 0x1f62c000 0x0 0x1000>; 318 reg-names = "csr-reg"; 319 enable-mask = <0x3>; 320 csr-mask = <0x3>; 321 clock-output-names = "xge1clk"; 322 }; 323 324 rngpkaclk: rngpkaclk@17000000 { 325 compatible = "apm,xgene-device-clock"; 326 #clock-cells = <1>; 327 clocks = <&socplldiv2 0>; 328 reg = <0x0 0x17000000 0x0 0x2000>; 329 reg-names = "csr-reg"; 330 csr-offset = <0xc>; 331 csr-mask = <0x10>; 332 enable-offset = <0x10>; 333 enable-mask = <0x10>; 334 clock-output-names = "rngpkaclk"; 335 }; 336 337 i2c4clk: i2c4clk@1704c000 { 338 compatible = "apm,xgene-device-clock"; 339 #clock-cells = <1>; 340 clocks = <&sbapbclk 0>; 341 reg = <0x0 0x1704c000 0x0 0x1000>; 342 reg-names = "csr-reg"; 343 csr-offset = <0x0>; 344 csr-mask = <0x40>; 345 enable-offset = <0x8>; 346 enable-mask = <0x40>; 347 clock-output-names = "i2c4clk"; 348 }; 349 }; 350 351 scu: system-clk-controller@17000000 { 352 compatible = "apm,xgene-scu","syscon"; 353 reg = <0x0 0x17000000 0x0 0x400>; 354 }; 355 356 reboot: reboot@17000014 { 357 compatible = "syscon-reboot"; 358 regmap = <&scu>; 359 offset = <0x14>; 360 mask = <0x1>; 361 }; 362 363 csw: csw@7e200000 { 364 compatible = "apm,xgene-csw", "syscon"; 365 reg = <0x0 0x7e200000 0x0 0x1000>; 366 }; 367 368 mcba: mcba@7e700000 { 369 compatible = "apm,xgene-mcb", "syscon"; 370 reg = <0x0 0x7e700000 0x0 0x1000>; 371 }; 372 373 mcbb: mcbb@7e720000 { 374 compatible = "apm,xgene-mcb", "syscon"; 375 reg = <0x0 0x7e720000 0x0 0x1000>; 376 }; 377 378 efuse: efuse@1054a000 { 379 compatible = "apm,xgene-efuse", "syscon"; 380 reg = <0x0 0x1054a000 0x0 0x20>; 381 }; 382 383 edac@78800000 { 384 compatible = "apm,xgene-edac"; 385 #address-cells = <2>; 386 #size-cells = <2>; 387 ranges; 388 regmap-csw = <&csw>; 389 regmap-mcba = <&mcba>; 390 regmap-mcbb = <&mcbb>; 391 regmap-efuse = <&efuse>; 392 reg = <0x0 0x78800000 0x0 0x100>; 393 interrupts = <0x0 0x20 0x4>, 394 <0x0 0x21 0x4>, 395 <0x0 0x27 0x4>; 396 397 edacmc@7e800000 { 398 compatible = "apm,xgene-edac-mc"; 399 reg = <0x0 0x7e800000 0x0 0x1000>; 400 memory-controller = <0>; 401 }; 402 403 edacmc@7e840000 { 404 compatible = "apm,xgene-edac-mc"; 405 reg = <0x0 0x7e840000 0x0 0x1000>; 406 memory-controller = <1>; 407 }; 408 409 edacmc@7e880000 { 410 compatible = "apm,xgene-edac-mc"; 411 reg = <0x0 0x7e880000 0x0 0x1000>; 412 memory-controller = <2>; 413 }; 414 415 edacmc@7e8c0000 { 416 compatible = "apm,xgene-edac-mc"; 417 reg = <0x0 0x7e8c0000 0x0 0x1000>; 418 memory-controller = <3>; 419 }; 420 421 edacpmd@7c000000 { 422 compatible = "apm,xgene-edac-pmd"; 423 reg = <0x0 0x7c000000 0x0 0x200000>; 424 pmd-controller = <0>; 425 }; 426 427 edacpmd@7c200000 { 428 compatible = "apm,xgene-edac-pmd"; 429 reg = <0x0 0x7c200000 0x0 0x200000>; 430 pmd-controller = <1>; 431 }; 432 433 edacpmd@7c400000 { 434 compatible = "apm,xgene-edac-pmd"; 435 reg = <0x0 0x7c400000 0x0 0x200000>; 436 pmd-controller = <2>; 437 }; 438 439 edacpmd@7c600000 { 440 compatible = "apm,xgene-edac-pmd"; 441 reg = <0x0 0x7c600000 0x0 0x200000>; 442 pmd-controller = <3>; 443 }; 444 445 edacl3@7e600000 { 446 compatible = "apm,xgene-edac-l3-v2"; 447 reg = <0x0 0x7e600000 0x0 0x1000>; 448 }; 449 450 edacsoc@7e930000 { 451 compatible = "apm,xgene-edac-soc"; 452 reg = <0x0 0x7e930000 0x0 0x1000>; 453 }; 454 }; 455 456 mailbox: mailbox@10540000 { 457 compatible = "apm,xgene-slimpro-mbox"; 458 reg = <0x0 0x10540000 0x0 0x8000>; 459 #mbox-cells = <1>; 460 interrupts = <0x0 0x0 0x4 461 0x0 0x1 0x4 462 0x0 0x2 0x4 463 0x0 0x3 0x4 464 0x0 0x4 0x4 465 0x0 0x5 0x4 466 0x0 0x6 0x4 467 0x0 0x7 0x4>; 468 }; 469 470 i2cslimpro { 471 compatible = "apm,xgene-slimpro-i2c"; 472 mboxes = <&mailbox 0>; 473 }; 474 475 serial0: serial@10600000 { 476 device_type = "serial"; 477 compatible = "ns16550"; 478 reg = <0 0x10600000 0x0 0x1000>; 479 reg-shift = <2>; 480 clock-frequency = <10000000>; 481 interrupt-parent = <&gic>; 482 interrupts = <0x0 0x4c 0x4>; 483 }; 484 485 /* Do not change dwusb name, coded for backward compatibility */ 486 usb0: dwusb@19000000 { 487 status = "disabled"; 488 compatible = "snps,dwc3"; 489 reg = <0x0 0x19000000 0x0 0x100000>; 490 interrupts = <0x0 0x5d 0x4>; 491 dma-coherent; 492 dr_mode = "host"; 493 }; 494 495 pcie0: pcie@1f2b0000 { 496 status = "disabled"; 497 device_type = "pci"; 498 compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; 499 #interrupt-cells = <1>; 500 #size-cells = <2>; 501 #address-cells = <3>; 502 reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ 503 0xc0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 504 reg-names = "csr", "cfg"; 505 ranges = <0x01000000 0x00 0x00000000 0xc0 0x10000000 0x00 0x00010000 /* io */ 506 0x02000000 0x00 0x20000000 0xc1 0x20000000 0x00 0x20000000 /* mem */ 507 0x43000000 0xe0 0x00000000 0xe0 0x00000000 0x20 0x00000000>; /* mem */ 508 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 509 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 510 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 511 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x10 0x1 512 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x11 0x1 513 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x12 0x1 514 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x13 0x1>; 515 dma-coherent; 516 clocks = <&pcie0clk 0>; 517 msi-parent = <&v2m0>; 518 }; 519 520 pcie1: pcie@1f2c0000 { 521 status = "disabled"; 522 device_type = "pci"; 523 compatible = "apm,xgene-pcie", "apm,xgene2-pcie"; 524 #interrupt-cells = <1>; 525 #size-cells = <2>; 526 #address-cells = <3>; 527 reg = < 0x00 0x1f2c0000 0x0 0x00010000 /* Controller registers */ 528 0xa0 0xd0000000 0x0 0x00040000>; /* PCI config space */ 529 reg-names = "csr", "cfg"; 530 ranges = <0x01000000 0x00 0x00000000 0xa0 0x10000000 0x00 0x00010000 /* io */ 531 0x02000000 0x00 0x20000000 0xa1 0x20000000 0x00 0x20000000 /* mem */ 532 0x43000000 0xb0 0x00000000 0xb0 0x00000000 0x10 0x00000000>; /* mem */ 533 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 534 0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; 535 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 536 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 0x16 0x1 537 0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 0x17 0x1 538 0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 0x18 0x1 539 0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 0x19 0x1>; 540 dma-coherent; 541 clocks = <&pcie1clk 0>; 542 msi-parent = <&v2m0>; 543 }; 544 545 sata1: sata@1a000000 { 546 compatible = "apm,xgene-ahci-v2"; 547 reg = <0x0 0x1a000000 0x0 0x1000>, 548 <0x0 0x1f200000 0x0 0x1000>, 549 <0x0 0x1f20d000 0x0 0x1000>, 550 <0x0 0x1f20e000 0x0 0x1000>; 551 interrupts = <0x0 0x5a 0x4>; 552 dma-coherent; 553 }; 554 555 sata2: sata@1a200000 { 556 compatible = "apm,xgene-ahci-v2"; 557 reg = <0x0 0x1a200000 0x0 0x1000>, 558 <0x0 0x1f210000 0x0 0x1000>, 559 <0x0 0x1f21d000 0x0 0x1000>, 560 <0x0 0x1f21e000 0x0 0x1000>; 561 interrupts = <0x0 0x5b 0x4>; 562 dma-coherent; 563 }; 564 565 sata3: sata@1a400000 { 566 compatible = "apm,xgene-ahci-v2"; 567 reg = <0x0 0x1a400000 0x0 0x1000>, 568 <0x0 0x1f220000 0x0 0x1000>, 569 <0x0 0x1f22d000 0x0 0x1000>, 570 <0x0 0x1f22e000 0x0 0x1000>; 571 interrupts = <0x0 0x5c 0x4>; 572 dma-coherent; 573 }; 574 575 mmc0: mmc@1c000000 { 576 compatible = "arasan,sdhci-4.9a"; 577 reg = <0x0 0x1c000000 0x0 0x100>; 578 interrupts = <0x0 0x49 0x4>; 579 dma-coherent; 580 no-1-8-v; 581 clock-names = "clk_xin", "clk_ahb"; 582 clocks = <&sdioclk 0>, <&ahbclk 0>; 583 }; 584 585 gfcgpio: gpio@1f63c000 { 586 compatible = "apm,xgene-gpio"; 587 reg = <0x0 0x1f63c000 0x0 0x40>; 588 gpio-controller; 589 #gpio-cells = <2>; 590 }; 591 592 dwgpio: gpio@1c024000 { 593 compatible = "snps,dw-apb-gpio"; 594 reg = <0x0 0x1c024000 0x0 0x1000>; 595 reg-io-width = <4>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 599 porta: gpio-controller@0 { 600 compatible = "snps,dw-apb-gpio-port"; 601 gpio-controller; 602 snps,nr-gpios = <32>; 603 reg = <0>; 604 }; 605 }; 606 607 sbgpio: gpio@17001000{ 608 compatible = "apm,xgene-gpio-sb"; 609 reg = <0x0 0x17001000 0x0 0x400>; 610 #gpio-cells = <2>; 611 gpio-controller; 612 interrupts = <0x0 0x28 0x1>, 613 <0x0 0x29 0x1>, 614 <0x0 0x2a 0x1>, 615 <0x0 0x2b 0x1>, 616 <0x0 0x2c 0x1>, 617 <0x0 0x2d 0x1>, 618 <0x0 0x2e 0x1>, 619 <0x0 0x2f 0x1>; 620 interrupt-parent = <&gic>; 621 #interrupt-cells = <2>; 622 interrupt-controller; 623 apm,nr-gpios = <22>; 624 apm,nr-irqs = <8>; 625 apm,irq-start = <8>; 626 }; 627 628 sgenet0: ethernet@1f610000 { 629 compatible = "apm,xgene2-sgenet"; 630 status = "disabled"; 631 reg = <0x0 0x1f610000 0x0 0x10000>, 632 <0x0 0x1f600000 0x0 0Xd100>, 633 <0x0 0x20000000 0x0 0X20000>; 634 interrupts = <0 96 4>, 635 <0 97 4>; 636 dma-coherent; 637 clocks = <&xge0clk 0>; 638 local-mac-address = [00 01 73 00 00 01]; 639 phy-connection-type = "sgmii"; 640 }; 641 642 xgenet1: ethernet@1f620000 { 643 compatible = "apm,xgene2-xgenet"; 644 status = "disabled"; 645 reg = <0x0 0x1f620000 0x0 0x10000>, 646 <0x0 0x1f600000 0x0 0Xd100>, 647 <0x0 0x20000000 0x0 0X220000>; 648 interrupts = <0 108 4>, 649 <0 109 4>, 650 <0 110 4>, 651 <0 111 4>, 652 <0 112 4>, 653 <0 113 4>, 654 <0 114 4>, 655 <0 115 4>; 656 channel = <12>; 657 port-id = <1>; 658 dma-coherent; 659 clocks = <&xge1clk 0>; 660 local-mac-address = [00 01 73 00 00 02]; 661 phy-connection-type = "xgmii"; 662 }; 663 664 rng: rng@10520000 { 665 compatible = "apm,xgene-rng"; 666 reg = <0x0 0x10520000 0x0 0x100>; 667 interrupts = <0x0 0x41 0x4>; 668 clocks = <&rngpkaclk 0>; 669 }; 670 671 i2c1: i2c@10511000 { 672 #address-cells = <1>; 673 #size-cells = <0>; 674 compatible = "snps,designware-i2c"; 675 reg = <0x0 0x10511000 0x0 0x1000>; 676 interrupts = <0 0x45 0x4>; 677 #clock-cells = <1>; 678 clocks = <&sbapbclk 0>; 679 bus_num = <1>; 680 }; 681 682 i2c4: i2c@10640000 { 683 #address-cells = <1>; 684 #size-cells = <0>; 685 compatible = "snps,designware-i2c"; 686 reg = <0x0 0x10640000 0x0 0x1000>; 687 interrupts = <0 0x3A 0x4>; 688 clocks = <&i2c4clk 0>; 689 bus_num = <4>; 690 }; 691 }; 692}; 693