1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This library is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of the
13 *     License, or (at your option) any later version.
14 *
15 *     This library is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 *  b) Permission is hereby granted, free of charge, to any person
23 *     obtaining a copy of this software and associated documentation
24 *     files (the "Software"), to deal in the Software without
25 *     restriction, including without limitation the rights to use,
26 *     copy, modify, merge, publish, distribute, sublicense, and/or
27 *     sell copies of the Software, and to permit persons to whom the
28 *     Software is furnished to do so, subject to the following
29 *     conditions:
30 *
31 *     The above copyright notice and this permission notice shall be
32 *     included in all copies or substantial portions of the Software.
33 *
34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 *     OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gx.dtsi"
45#include <dt-bindings/clock/gxbb-clkc.h>
46#include <dt-bindings/gpio/meson-gxl-gpio.h>
47
48/ {
49	compatible = "amlogic,meson-gxl";
50};
51
52&ethmac {
53	reg = <0x0 0xc9410000 0x0 0x10000
54	       0x0 0xc8834540 0x0 0x4>;
55
56	clocks = <&clkc CLKID_ETH>,
57		 <&clkc CLKID_FCLK_DIV2>,
58		 <&clkc CLKID_MPLL2>;
59	clock-names = "stmmaceth", "clkin0", "clkin1";
60
61	mdio0: mdio {
62		#address-cells = <1>;
63		#size-cells = <0>;
64		compatible = "snps,dwmac-mdio";
65	};
66};
67
68&aobus {
69	pinctrl_aobus: pinctrl@14 {
70		compatible = "amlogic,meson-gxl-aobus-pinctrl";
71		#address-cells = <2>;
72		#size-cells = <2>;
73		ranges;
74
75		gpio_ao: bank@14 {
76			reg = <0x0 0x00014 0x0 0x8>,
77			      <0x0 0x0002c 0x0 0x4>,
78			      <0x0 0x00024 0x0 0x8>;
79			reg-names = "mux", "pull", "gpio";
80			gpio-controller;
81			#gpio-cells = <2>;
82		};
83
84		uart_ao_a_pins: uart_ao_a {
85			mux {
86				groups = "uart_tx_ao_a", "uart_rx_ao_a";
87				function = "uart_ao";
88			};
89		};
90
91		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
92			mux {
93				groups = "uart_cts_ao_a",
94				       "uart_rts_ao_a";
95				function = "uart_ao";
96			};
97		};
98
99		uart_ao_b_pins: uart_ao_b {
100			mux {
101				groups = "uart_tx_ao_b", "uart_rx_ao_b";
102				function = "uart_ao_b";
103			};
104		};
105
106		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
107			mux {
108				groups = "uart_cts_ao_b",
109				       "uart_rts_ao_b";
110				function = "uart_ao_b";
111			};
112		};
113
114		remote_input_ao_pins: remote_input_ao {
115			mux {
116				groups = "remote_input_ao";
117				function = "remote_input_ao";
118			};
119		};
120
121		pwm_ao_b_pins: pwm_ao_b {
122			mux {
123				groups = "pwm_ao_b";
124				function = "pwm_ao_b";
125			};
126		};
127	};
128};
129
130&periphs {
131	pinctrl_periphs: pinctrl@4b0 {
132		compatible = "amlogic,meson-gxl-periphs-pinctrl";
133		#address-cells = <2>;
134		#size-cells = <2>;
135		ranges;
136
137		gpio: bank@4b0 {
138			reg = <0x0 0x004b0 0x0 0x28>,
139			      <0x0 0x004e8 0x0 0x14>,
140			      <0x0 0x00120 0x0 0x14>,
141			      <0x0 0x00430 0x0 0x40>;
142			reg-names = "mux", "pull", "pull-enable", "gpio";
143			gpio-controller;
144			#gpio-cells = <2>;
145		};
146
147		emmc_pins: emmc {
148			mux {
149				groups = "emmc_nand_d07",
150				       "emmc_cmd",
151				       "emmc_clk",
152				       "emmc_ds";
153				function = "emmc";
154			};
155		};
156
157		sdcard_pins: sdcard {
158			mux {
159				groups = "sdcard_d0",
160				       "sdcard_d1",
161				       "sdcard_d2",
162				       "sdcard_d3",
163				       "sdcard_cmd",
164				       "sdcard_clk";
165				function = "sdcard";
166			};
167		};
168
169		sdio_pins: sdio {
170			mux {
171				groups = "sdio_d0",
172				       "sdio_d1",
173				       "sdio_d2",
174				       "sdio_d3",
175				       "sdio_cmd",
176				       "sdio_clk";
177				function = "sdio";
178			};
179		};
180
181		sdio_irq_pins: sdio_irq {
182			mux {
183				groups = "sdio_irq";
184				function = "sdio";
185			};
186		};
187
188		uart_a_pins: uart_a {
189			mux {
190				groups = "uart_tx_a",
191				       "uart_rx_a";
192				function = "uart_a";
193			};
194		};
195
196		uart_a_cts_rts_pins: uart_a_cts_rts {
197			mux {
198				groups = "uart_cts_a",
199				       "uart_rts_a";
200				function = "uart_a";
201			};
202		};
203
204		uart_b_pins: uart_b {
205			mux {
206				groups = "uart_tx_b",
207				       "uart_rx_b";
208				function = "uart_b";
209			};
210		};
211
212		uart_b_cts_rts_pins: uart_b_cts_rts {
213			mux {
214				groups = "uart_cts_b",
215				       "uart_rts_b";
216				function = "uart_b";
217			};
218		};
219
220		uart_c_pins: uart_c {
221			mux {
222				groups = "uart_tx_c",
223				       "uart_rx_c";
224				function = "uart_c";
225			};
226		};
227
228		uart_c_cts_rts_pins: uart_c_cts_rts {
229			mux {
230				groups = "uart_cts_c",
231				       "uart_rts_c";
232				function = "uart_c";
233			};
234		};
235
236		i2c_a_pins: i2c_a {
237			mux {
238				groups = "i2c_sck_a",
239				     "i2c_sda_a";
240				function = "i2c_a";
241			};
242		};
243
244		i2c_b_pins: i2c_b {
245			mux {
246				groups = "i2c_sck_b",
247				      "i2c_sda_b";
248				function = "i2c_b";
249			};
250		};
251
252		i2c_c_pins: i2c_c {
253			mux {
254				groups = "i2c_sck_c",
255				      "i2c_sda_c";
256				function = "i2c_c";
257			};
258		};
259
260		eth_pins: eth_c {
261			mux {
262				groups = "eth_mdio",
263				       "eth_mdc",
264				       "eth_clk_rx_clk",
265				       "eth_rx_dv",
266				       "eth_rxd0",
267				       "eth_rxd1",
268				       "eth_rxd2",
269				       "eth_rxd3",
270				       "eth_rgmii_tx_clk",
271				       "eth_tx_en",
272				       "eth_txd0",
273				       "eth_txd1",
274				       "eth_txd2",
275				       "eth_txd3";
276				function = "eth";
277			};
278		};
279
280		pwm_e_pins: pwm_e {
281			mux {
282				groups = "pwm_e";
283				function = "pwm_e";
284			};
285		};
286
287		hdmi_hpd_pins: hdmi_hpd {
288			mux {
289				groups = "hdmi_hpd";
290				function = "hdmi_hpd";
291			};
292		};
293
294		hdmi_i2c_pins: hdmi_i2c {
295			mux {
296				groups = "hdmi_sda", "hdmi_scl";
297				function = "hdmi_i2c";
298			};
299		};
300	};
301
302	eth-phy-mux {
303		compatible = "mdio-mux-mmioreg", "mdio-mux";
304		#address-cells = <1>;
305		#size-cells = <0>;
306		reg = <0x0 0x55c 0x0 0x4>;
307		mux-mask = <0xffffffff>;
308		mdio-parent-bus = <&mdio0>;
309
310		internal_mdio: mdio@e40908ff {
311			reg = <0xe40908ff>;
312			#address-cells = <1>;
313			#size-cells = <0>;
314
315			internal_phy: ethernet-phy@8 {
316				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
317				reg = <8>;
318				max-speed = <100>;
319			};
320		};
321
322		external_mdio: mdio@2009087f {
323			reg = <0x2009087f>;
324			#address-cells = <1>;
325			#size-cells = <0>;
326		};
327	};
328};
329
330&hiubus {
331	clkc: clock-controller@0 {
332		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
333		#clock-cells = <1>;
334		reg = <0x0 0x0 0x0 0x3db>;
335	};
336};
337
338&i2c_A {
339	clocks = <&clkc CLKID_I2C>;
340};
341
342&i2c_B {
343	clocks = <&clkc CLKID_I2C>;
344};
345
346&i2c_C {
347	clocks = <&clkc CLKID_I2C>;
348};
349
350&saradc {
351	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
352	clocks = <&xtal>,
353		 <&clkc CLKID_SAR_ADC>,
354		 <&clkc CLKID_SANA>,
355		 <&clkc CLKID_SAR_ADC_CLK>,
356		 <&clkc CLKID_SAR_ADC_SEL>;
357	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
358};
359
360&sd_emmc_a {
361	clocks = <&clkc CLKID_SD_EMMC_A>,
362		 <&xtal>,
363		 <&clkc CLKID_FCLK_DIV2>;
364	clock-names = "core", "clkin0", "clkin1";
365};
366
367&sd_emmc_b {
368	clocks = <&clkc CLKID_SD_EMMC_B>,
369		 <&xtal>,
370		 <&clkc CLKID_FCLK_DIV2>;
371       clock-names = "core", "clkin0", "clkin1";
372};
373
374&sd_emmc_c {
375	clocks = <&clkc CLKID_SD_EMMC_C>,
376		 <&xtal>,
377		 <&clkc CLKID_FCLK_DIV2>;
378	clock-names = "core", "clkin0", "clkin1";
379};
380
381&vpu {
382	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
383};
384