1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This library is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of the
13 *     License, or (at your option) any later version.
14 *
15 *     This library is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 *  b) Permission is hereby granted, free of charge, to any person
23 *     obtaining a copy of this software and associated documentation
24 *     files (the "Software"), to deal in the Software without
25 *     restriction, including without limitation the rights to use,
26 *     copy, modify, merge, publish, distribute, sublicense, and/or
27 *     sell copies of the Software, and to permit persons to whom the
28 *     Software is furnished to do so, subject to the following
29 *     conditions:
30 *
31 *     The above copyright notice and this permission notice shall be
32 *     included in all copies or substantial portions of the Software.
33 *
34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 *     OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gx.dtsi"
45#include <dt-bindings/clock/gxbb-clkc.h>
46#include <dt-bindings/gpio/meson-gxl-gpio.h>
47#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
48
49/ {
50	compatible = "amlogic,meson-gxl";
51};
52
53&ethmac {
54	reg = <0x0 0xc9410000 0x0 0x10000
55	       0x0 0xc8834540 0x0 0x4>;
56
57	clocks = <&clkc CLKID_ETH>,
58		 <&clkc CLKID_FCLK_DIV2>,
59		 <&clkc CLKID_MPLL2>;
60	clock-names = "stmmaceth", "clkin0", "clkin1";
61
62	mdio0: mdio {
63		#address-cells = <1>;
64		#size-cells = <0>;
65		compatible = "snps,dwmac-mdio";
66	};
67};
68
69&aobus {
70	pinctrl_aobus: pinctrl@14 {
71		compatible = "amlogic,meson-gxl-aobus-pinctrl";
72		#address-cells = <2>;
73		#size-cells = <2>;
74		ranges;
75
76		gpio_ao: bank@14 {
77			reg = <0x0 0x00014 0x0 0x8>,
78			      <0x0 0x0002c 0x0 0x4>,
79			      <0x0 0x00024 0x0 0x8>;
80			reg-names = "mux", "pull", "gpio";
81			gpio-controller;
82			#gpio-cells = <2>;
83			gpio-ranges = <&pinctrl_aobus 0 0 14>;
84		};
85
86		uart_ao_a_pins: uart_ao_a {
87			mux {
88				groups = "uart_tx_ao_a", "uart_rx_ao_a";
89				function = "uart_ao";
90			};
91		};
92
93		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
94			mux {
95				groups = "uart_cts_ao_a",
96				       "uart_rts_ao_a";
97				function = "uart_ao";
98			};
99		};
100
101		uart_ao_b_pins: uart_ao_b {
102			mux {
103				groups = "uart_tx_ao_b", "uart_rx_ao_b";
104				function = "uart_ao_b";
105			};
106		};
107
108		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
109			mux {
110				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
111				function = "uart_ao_b";
112			};
113		};
114
115		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
116			mux {
117				groups = "uart_cts_ao_b",
118				       "uart_rts_ao_b";
119				function = "uart_ao_b";
120			};
121		};
122
123		remote_input_ao_pins: remote_input_ao {
124			mux {
125				groups = "remote_input_ao";
126				function = "remote_input_ao";
127			};
128		};
129
130		i2c_ao_pins: i2c_ao {
131			mux {
132				groups = "i2c_sck_ao",
133				       "i2c_sda_ao";
134				function = "i2c_ao";
135			};
136		};
137
138		pwm_ao_a_3_pins: pwm_ao_a_3 {
139			mux {
140				groups = "pwm_ao_a_3";
141				function = "pwm_ao_a";
142			};
143		};
144
145		pwm_ao_a_8_pins: pwm_ao_a_8 {
146			mux {
147				groups = "pwm_ao_a_8";
148				function = "pwm_ao_a";
149			};
150		};
151
152		pwm_ao_b_pins: pwm_ao_b {
153			mux {
154				groups = "pwm_ao_b";
155				function = "pwm_ao_b";
156			};
157		};
158
159		pwm_ao_b_6_pins: pwm_ao_b_6 {
160			mux {
161				groups = "pwm_ao_b_6";
162				function = "pwm_ao_b";
163			};
164		};
165
166		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
167			mux {
168				groups = "i2s_out_ch23_ao";
169				function = "i2s_out_ao";
170			};
171		};
172
173		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
174			mux {
175				groups = "i2s_out_ch45_ao";
176				function = "i2s_out_ao";
177			};
178		};
179
180		spdif_out_ao_6_pins: spdif_out_ao_6 {
181			mux {
182				groups = "spdif_out_ao_6";
183				function = "spdif_out_ao";
184			};
185		};
186
187		spdif_out_ao_9_pins: spdif_out_ao_9 {
188			mux {
189				groups = "spdif_out_ao_9";
190				function = "spdif_out_ao";
191			};
192		};
193	};
194};
195
196&hdmi_tx {
197	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
198	resets = <&reset RESET_HDMITX_CAPB3>,
199		 <&reset RESET_HDMI_SYSTEM_RESET>,
200		 <&reset RESET_HDMI_TX>;
201	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
202	clocks = <&clkc CLKID_HDMI_PCLK>,
203		 <&clkc CLKID_CLK81>,
204		 <&clkc CLKID_GCLK_VENCI_INT0>;
205	clock-names = "isfr", "iahb", "venci";
206};
207
208&hiubus {
209	clkc: clock-controller@0 {
210		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
211		#clock-cells = <1>;
212		reg = <0x0 0x0 0x0 0x3db>;
213	};
214};
215
216&i2c_A {
217	clocks = <&clkc CLKID_I2C>;
218};
219
220&i2c_AO {
221	clocks = <&clkc CLKID_AO_I2C>;
222};
223
224&i2c_B {
225	clocks = <&clkc CLKID_I2C>;
226};
227
228&i2c_C {
229	clocks = <&clkc CLKID_I2C>;
230};
231
232&periphs {
233	pinctrl_periphs: pinctrl@4b0 {
234		compatible = "amlogic,meson-gxl-periphs-pinctrl";
235		#address-cells = <2>;
236		#size-cells = <2>;
237		ranges;
238
239		gpio: bank@4b0 {
240			reg = <0x0 0x004b0 0x0 0x28>,
241			      <0x0 0x004e8 0x0 0x14>,
242			      <0x0 0x00520 0x0 0x14>,
243			      <0x0 0x00430 0x0 0x40>;
244			reg-names = "mux", "pull", "pull-enable", "gpio";
245			gpio-controller;
246			#gpio-cells = <2>;
247			gpio-ranges = <&pinctrl_periphs 0 10 101>;
248		};
249
250		emmc_pins: emmc {
251			mux {
252				groups = "emmc_nand_d07",
253				       "emmc_cmd",
254				       "emmc_clk",
255				       "emmc_ds";
256				function = "emmc";
257			};
258		};
259
260		nor_pins: nor {
261			mux {
262				groups = "nor_d",
263				       "nor_q",
264				       "nor_c",
265				       "nor_cs";
266				function = "nor";
267			};
268		};
269
270		sdcard_pins: sdcard {
271			mux {
272				groups = "sdcard_d0",
273				       "sdcard_d1",
274				       "sdcard_d2",
275				       "sdcard_d3",
276				       "sdcard_cmd",
277				       "sdcard_clk";
278				function = "sdcard";
279			};
280		};
281
282		sdio_pins: sdio {
283			mux {
284				groups = "sdio_d0",
285				       "sdio_d1",
286				       "sdio_d2",
287				       "sdio_d3",
288				       "sdio_cmd",
289				       "sdio_clk";
290				function = "sdio";
291			};
292		};
293
294		sdio_irq_pins: sdio_irq {
295			mux {
296				groups = "sdio_irq";
297				function = "sdio";
298			};
299		};
300
301		uart_a_pins: uart_a {
302			mux {
303				groups = "uart_tx_a",
304				       "uart_rx_a";
305				function = "uart_a";
306			};
307		};
308
309		uart_a_cts_rts_pins: uart_a_cts_rts {
310			mux {
311				groups = "uart_cts_a",
312				       "uart_rts_a";
313				function = "uart_a";
314			};
315		};
316
317		uart_b_pins: uart_b {
318			mux {
319				groups = "uart_tx_b",
320				       "uart_rx_b";
321				function = "uart_b";
322			};
323		};
324
325		uart_b_cts_rts_pins: uart_b_cts_rts {
326			mux {
327				groups = "uart_cts_b",
328				       "uart_rts_b";
329				function = "uart_b";
330			};
331		};
332
333		uart_c_pins: uart_c {
334			mux {
335				groups = "uart_tx_c",
336				       "uart_rx_c";
337				function = "uart_c";
338			};
339		};
340
341		uart_c_cts_rts_pins: uart_c_cts_rts {
342			mux {
343				groups = "uart_cts_c",
344				       "uart_rts_c";
345				function = "uart_c";
346			};
347		};
348
349		i2c_a_pins: i2c_a {
350			mux {
351				groups = "i2c_sck_a",
352				     "i2c_sda_a";
353				function = "i2c_a";
354			};
355		};
356
357		i2c_b_pins: i2c_b {
358			mux {
359				groups = "i2c_sck_b",
360				      "i2c_sda_b";
361				function = "i2c_b";
362			};
363		};
364
365		i2c_c_pins: i2c_c {
366			mux {
367				groups = "i2c_sck_c",
368				      "i2c_sda_c";
369				function = "i2c_c";
370			};
371		};
372
373		eth_pins: eth_c {
374			mux {
375				groups = "eth_mdio",
376				       "eth_mdc",
377				       "eth_clk_rx_clk",
378				       "eth_rx_dv",
379				       "eth_rxd0",
380				       "eth_rxd1",
381				       "eth_rxd2",
382				       "eth_rxd3",
383				       "eth_rgmii_tx_clk",
384				       "eth_tx_en",
385				       "eth_txd0",
386				       "eth_txd1",
387				       "eth_txd2",
388				       "eth_txd3";
389				function = "eth";
390			};
391		};
392
393		pwm_a_pins: pwm_a {
394			mux {
395				groups = "pwm_a";
396				function = "pwm_a";
397			};
398		};
399
400		pwm_b_pins: pwm_b {
401			mux {
402				groups = "pwm_b";
403				function = "pwm_b";
404			};
405		};
406
407		pwm_c_pins: pwm_c {
408			mux {
409				groups = "pwm_c";
410				function = "pwm_c";
411			};
412		};
413
414		pwm_d_pins: pwm_d {
415			mux {
416				groups = "pwm_d";
417				function = "pwm_d";
418			};
419		};
420
421		pwm_e_pins: pwm_e {
422			mux {
423				groups = "pwm_e";
424				function = "pwm_e";
425			};
426		};
427
428		pwm_f_clk_pins: pwm_f_clk {
429			mux {
430				groups = "pwm_f_clk";
431				function = "pwm_f";
432			};
433		};
434
435		pwm_f_x_pins: pwm_f_x {
436			mux {
437				groups = "pwm_f_x";
438				function = "pwm_f";
439			};
440		};
441
442		hdmi_hpd_pins: hdmi_hpd {
443			mux {
444				groups = "hdmi_hpd";
445				function = "hdmi_hpd";
446			};
447		};
448
449		hdmi_i2c_pins: hdmi_i2c {
450			mux {
451				groups = "hdmi_sda", "hdmi_scl";
452				function = "hdmi_i2c";
453			};
454		};
455
456		i2s_am_clk_pins: i2s_am_clk {
457			mux {
458				groups = "i2s_am_clk";
459				function = "i2s_out";
460			};
461		};
462
463		i2s_out_ao_clk_pins: i2s_out_ao_clk {
464			mux {
465				groups = "i2s_out_ao_clk";
466				function = "i2s_out";
467			};
468		};
469
470		i2s_out_lr_clk_pins: i2s_out_lr_clk {
471			mux {
472				groups = "i2s_out_lr_clk";
473				function = "i2s_out";
474			};
475		};
476
477		i2s_out_ch01_pins: i2s_out_ch01 {
478			mux {
479				groups = "i2s_out_ch01";
480				function = "i2s_out";
481			};
482		};
483		i2sout_ch23_z_pins: i2sout_ch23_z {
484			mux {
485				groups = "i2sout_ch23_z";
486				function = "i2s_out";
487			};
488		};
489
490		i2sout_ch45_z_pins: i2sout_ch45_z {
491			mux {
492				groups = "i2sout_ch45_z";
493				function = "i2s_out";
494			};
495		};
496
497		i2sout_ch67_z_pins: i2sout_ch67_z {
498			mux {
499				groups = "i2sout_ch67_z";
500				function = "i2s_out";
501			};
502		};
503
504		spdif_out_h_pins: spdif_out_ao_h {
505			mux {
506				groups = "spdif_out_h";
507				function = "spdif_out";
508			};
509		};
510	};
511
512	eth-phy-mux {
513		compatible = "mdio-mux-mmioreg", "mdio-mux";
514		#address-cells = <1>;
515		#size-cells = <0>;
516		reg = <0x0 0x55c 0x0 0x4>;
517		mux-mask = <0xffffffff>;
518		mdio-parent-bus = <&mdio0>;
519
520		internal_mdio: mdio@e40908ff {
521			reg = <0xe40908ff>;
522			#address-cells = <1>;
523			#size-cells = <0>;
524
525			internal_phy: ethernet-phy@8 {
526				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
527				reg = <8>;
528				max-speed = <100>;
529			};
530		};
531
532		external_mdio: mdio@2009087f {
533			reg = <0x2009087f>;
534			#address-cells = <1>;
535			#size-cells = <0>;
536		};
537	};
538};
539
540&saradc {
541	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
542	clocks = <&xtal>,
543		 <&clkc CLKID_SAR_ADC>,
544		 <&clkc CLKID_SANA>,
545		 <&clkc CLKID_SAR_ADC_CLK>,
546		 <&clkc CLKID_SAR_ADC_SEL>;
547	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
548};
549
550&sd_emmc_a {
551	clocks = <&clkc CLKID_SD_EMMC_A>,
552		 <&xtal>,
553		 <&clkc CLKID_FCLK_DIV2>;
554	clock-names = "core", "clkin0", "clkin1";
555};
556
557&sd_emmc_b {
558	clocks = <&clkc CLKID_SD_EMMC_B>,
559		 <&xtal>,
560		 <&clkc CLKID_FCLK_DIV2>;
561       clock-names = "core", "clkin0", "clkin1";
562};
563
564&sd_emmc_c {
565	clocks = <&clkc CLKID_SD_EMMC_C>,
566		 <&xtal>,
567		 <&clkc CLKID_FCLK_DIV2>;
568	clock-names = "core", "clkin0", "clkin1";
569};
570
571&spifc {
572	clocks = <&clkc CLKID_SPI>;
573};
574
575&vpu {
576	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
577};
578