1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This library is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of the
13 *     License, or (at your option) any later version.
14 *
15 *     This library is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 *  b) Permission is hereby granted, free of charge, to any person
23 *     obtaining a copy of this software and associated documentation
24 *     files (the "Software"), to deal in the Software without
25 *     restriction, including without limitation the rights to use,
26 *     copy, modify, merge, publish, distribute, sublicense, and/or
27 *     sell copies of the Software, and to permit persons to whom the
28 *     Software is furnished to do so, subject to the following
29 *     conditions:
30 *
31 *     The above copyright notice and this permission notice shall be
32 *     included in all copies or substantial portions of the Software.
33 *
34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 *     OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gx.dtsi"
45#include <dt-bindings/clock/gxbb-clkc.h>
46#include <dt-bindings/gpio/meson-gxl-gpio.h>
47
48/ {
49	compatible = "amlogic,meson-gxl";
50};
51
52&ethmac {
53	reg = <0x0 0xc9410000 0x0 0x10000
54	       0x0 0xc8834540 0x0 0x4>;
55
56	clocks = <&clkc CLKID_ETH>,
57		 <&clkc CLKID_FCLK_DIV2>,
58		 <&clkc CLKID_MPLL2>;
59	clock-names = "stmmaceth", "clkin0", "clkin1";
60
61	mdio0: mdio {
62		#address-cells = <1>;
63		#size-cells = <0>;
64		compatible = "snps,dwmac-mdio";
65	};
66};
67
68&aobus {
69	pinctrl_aobus: pinctrl@14 {
70		compatible = "amlogic,meson-gxl-aobus-pinctrl";
71		#address-cells = <2>;
72		#size-cells = <2>;
73		ranges;
74
75		gpio_ao: bank@14 {
76			reg = <0x0 0x00014 0x0 0x8>,
77			      <0x0 0x0002c 0x0 0x4>,
78			      <0x0 0x00024 0x0 0x8>;
79			reg-names = "mux", "pull", "gpio";
80			gpio-controller;
81			#gpio-cells = <2>;
82		};
83
84		uart_ao_a_pins: uart_ao_a {
85			mux {
86				groups = "uart_tx_ao_a", "uart_rx_ao_a";
87				function = "uart_ao";
88			};
89		};
90
91		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
92			mux {
93				groups = "uart_cts_ao_a",
94				       "uart_rts_ao_a";
95				function = "uart_ao";
96			};
97		};
98
99		uart_ao_b_pins: uart_ao_b {
100			mux {
101				groups = "uart_tx_ao_b", "uart_rx_ao_b";
102				function = "uart_ao_b";
103			};
104		};
105
106		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
107			mux {
108				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
109				function = "uart_ao_b";
110			};
111		};
112
113		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
114			mux {
115				groups = "uart_cts_ao_b",
116				       "uart_rts_ao_b";
117				function = "uart_ao_b";
118			};
119		};
120
121		remote_input_ao_pins: remote_input_ao {
122			mux {
123				groups = "remote_input_ao";
124				function = "remote_input_ao";
125			};
126		};
127
128		i2c_ao_pins: i2c_ao {
129			mux {
130				groups = "i2c_sck_ao",
131				       "i2c_sda_ao";
132				function = "i2c_ao";
133			};
134		};
135
136		pwm_ao_a_3_pins: pwm_ao_a_3 {
137			mux {
138				groups = "pwm_ao_a_3";
139				function = "pwm_ao_a";
140			};
141		};
142
143		pwm_ao_a_8_pins: pwm_ao_a_8 {
144			mux {
145				groups = "pwm_ao_a_8";
146				function = "pwm_ao_a";
147			};
148		};
149
150		pwm_ao_b_pins: pwm_ao_b {
151			mux {
152				groups = "pwm_ao_b";
153				function = "pwm_ao_b";
154			};
155		};
156
157		pwm_ao_b_6_pins: pwm_ao_b_6 {
158			mux {
159				groups = "pwm_ao_b_6";
160				function = "pwm_ao_b";
161			};
162		};
163	};
164};
165
166&periphs {
167	pinctrl_periphs: pinctrl@4b0 {
168		compatible = "amlogic,meson-gxl-periphs-pinctrl";
169		#address-cells = <2>;
170		#size-cells = <2>;
171		ranges;
172
173		gpio: bank@4b0 {
174			reg = <0x0 0x004b0 0x0 0x28>,
175			      <0x0 0x004e8 0x0 0x14>,
176			      <0x0 0x00120 0x0 0x14>,
177			      <0x0 0x00430 0x0 0x40>;
178			reg-names = "mux", "pull", "pull-enable", "gpio";
179			gpio-controller;
180			#gpio-cells = <2>;
181		};
182
183		emmc_pins: emmc {
184			mux {
185				groups = "emmc_nand_d07",
186				       "emmc_cmd",
187				       "emmc_clk",
188				       "emmc_ds";
189				function = "emmc";
190			};
191		};
192
193		nor_pins: nor {
194			mux {
195				groups = "nor_d",
196				       "nor_q",
197				       "nor_c",
198				       "nor_cs";
199				function = "nor";
200			};
201		};
202
203		sdcard_pins: sdcard {
204			mux {
205				groups = "sdcard_d0",
206				       "sdcard_d1",
207				       "sdcard_d2",
208				       "sdcard_d3",
209				       "sdcard_cmd",
210				       "sdcard_clk";
211				function = "sdcard";
212			};
213		};
214
215		sdio_pins: sdio {
216			mux {
217				groups = "sdio_d0",
218				       "sdio_d1",
219				       "sdio_d2",
220				       "sdio_d3",
221				       "sdio_cmd",
222				       "sdio_clk";
223				function = "sdio";
224			};
225		};
226
227		sdio_irq_pins: sdio_irq {
228			mux {
229				groups = "sdio_irq";
230				function = "sdio";
231			};
232		};
233
234		uart_a_pins: uart_a {
235			mux {
236				groups = "uart_tx_a",
237				       "uart_rx_a";
238				function = "uart_a";
239			};
240		};
241
242		uart_a_cts_rts_pins: uart_a_cts_rts {
243			mux {
244				groups = "uart_cts_a",
245				       "uart_rts_a";
246				function = "uart_a";
247			};
248		};
249
250		uart_b_pins: uart_b {
251			mux {
252				groups = "uart_tx_b",
253				       "uart_rx_b";
254				function = "uart_b";
255			};
256		};
257
258		uart_b_cts_rts_pins: uart_b_cts_rts {
259			mux {
260				groups = "uart_cts_b",
261				       "uart_rts_b";
262				function = "uart_b";
263			};
264		};
265
266		uart_c_pins: uart_c {
267			mux {
268				groups = "uart_tx_c",
269				       "uart_rx_c";
270				function = "uart_c";
271			};
272		};
273
274		uart_c_cts_rts_pins: uart_c_cts_rts {
275			mux {
276				groups = "uart_cts_c",
277				       "uart_rts_c";
278				function = "uart_c";
279			};
280		};
281
282		i2c_a_pins: i2c_a {
283			mux {
284				groups = "i2c_sck_a",
285				     "i2c_sda_a";
286				function = "i2c_a";
287			};
288		};
289
290		i2c_b_pins: i2c_b {
291			mux {
292				groups = "i2c_sck_b",
293				      "i2c_sda_b";
294				function = "i2c_b";
295			};
296		};
297
298		i2c_c_pins: i2c_c {
299			mux {
300				groups = "i2c_sck_c",
301				      "i2c_sda_c";
302				function = "i2c_c";
303			};
304		};
305
306		eth_pins: eth_c {
307			mux {
308				groups = "eth_mdio",
309				       "eth_mdc",
310				       "eth_clk_rx_clk",
311				       "eth_rx_dv",
312				       "eth_rxd0",
313				       "eth_rxd1",
314				       "eth_rxd2",
315				       "eth_rxd3",
316				       "eth_rgmii_tx_clk",
317				       "eth_tx_en",
318				       "eth_txd0",
319				       "eth_txd1",
320				       "eth_txd2",
321				       "eth_txd3";
322				function = "eth";
323			};
324		};
325
326		pwm_a_pins: pwm_a {
327			mux {
328				groups = "pwm_a";
329				function = "pwm_a";
330			};
331		};
332
333		pwm_b_pins: pwm_b {
334			mux {
335				groups = "pwm_b";
336				function = "pwm_b";
337			};
338		};
339
340		pwm_c_pins: pwm_c {
341			mux {
342				groups = "pwm_c";
343				function = "pwm_c";
344			};
345		};
346
347		pwm_d_pins: pwm_d {
348			mux {
349				groups = "pwm_d";
350				function = "pwm_d";
351			};
352		};
353
354		pwm_e_pins: pwm_e {
355			mux {
356				groups = "pwm_e";
357				function = "pwm_e";
358			};
359		};
360
361		pwm_f_clk_pins: pwm_f_clk {
362			mux {
363				groups = "pwm_f_clk";
364				function = "pwm_f";
365			};
366		};
367
368		pwm_f_x_pins: pwm_f_x {
369			mux {
370				groups = "pwm_f_x";
371				function = "pwm_f";
372			};
373		};
374
375		hdmi_hpd_pins: hdmi_hpd {
376			mux {
377				groups = "hdmi_hpd";
378				function = "hdmi_hpd";
379			};
380		};
381
382		hdmi_i2c_pins: hdmi_i2c {
383			mux {
384				groups = "hdmi_sda", "hdmi_scl";
385				function = "hdmi_i2c";
386			};
387		};
388	};
389
390	eth-phy-mux {
391		compatible = "mdio-mux-mmioreg", "mdio-mux";
392		#address-cells = <1>;
393		#size-cells = <0>;
394		reg = <0x0 0x55c 0x0 0x4>;
395		mux-mask = <0xffffffff>;
396		mdio-parent-bus = <&mdio0>;
397
398		internal_mdio: mdio@e40908ff {
399			reg = <0xe40908ff>;
400			#address-cells = <1>;
401			#size-cells = <0>;
402
403			internal_phy: ethernet-phy@8 {
404				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
405				reg = <8>;
406				max-speed = <100>;
407			};
408		};
409
410		external_mdio: mdio@2009087f {
411			reg = <0x2009087f>;
412			#address-cells = <1>;
413			#size-cells = <0>;
414		};
415	};
416};
417
418&hiubus {
419	clkc: clock-controller@0 {
420		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
421		#clock-cells = <1>;
422		reg = <0x0 0x0 0x0 0x3db>;
423	};
424};
425
426&i2c_A {
427	clocks = <&clkc CLKID_I2C>;
428};
429
430&i2c_AO {
431	clocks = <&clkc CLKID_AO_I2C>;
432};
433
434&i2c_B {
435	clocks = <&clkc CLKID_I2C>;
436};
437
438&i2c_C {
439	clocks = <&clkc CLKID_I2C>;
440};
441
442&saradc {
443	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
444	clocks = <&xtal>,
445		 <&clkc CLKID_SAR_ADC>,
446		 <&clkc CLKID_SANA>,
447		 <&clkc CLKID_SAR_ADC_CLK>,
448		 <&clkc CLKID_SAR_ADC_SEL>;
449	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
450};
451
452&sd_emmc_a {
453	clocks = <&clkc CLKID_SD_EMMC_A>,
454		 <&xtal>,
455		 <&clkc CLKID_FCLK_DIV2>;
456	clock-names = "core", "clkin0", "clkin1";
457};
458
459&sd_emmc_b {
460	clocks = <&clkc CLKID_SD_EMMC_B>,
461		 <&xtal>,
462		 <&clkc CLKID_FCLK_DIV2>;
463       clock-names = "core", "clkin0", "clkin1";
464};
465
466&sd_emmc_c {
467	clocks = <&clkc CLKID_SD_EMMC_C>,
468		 <&xtal>,
469		 <&clkc CLKID_FCLK_DIV2>;
470	clock-names = "core", "clkin0", "clkin1";
471};
472
473&spifc {
474	clocks = <&clkc CLKID_SPI>;
475};
476
477&vpu {
478	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
479};
480