1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This library is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of the
13 *     License, or (at your option) any later version.
14 *
15 *     This library is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 *  b) Permission is hereby granted, free of charge, to any person
23 *     obtaining a copy of this software and associated documentation
24 *     files (the "Software"), to deal in the Software without
25 *     restriction, including without limitation the rights to use,
26 *     copy, modify, merge, publish, distribute, sublicense, and/or
27 *     sell copies of the Software, and to permit persons to whom the
28 *     Software is furnished to do so, subject to the following
29 *     conditions:
30 *
31 *     The above copyright notice and this permission notice shall be
32 *     included in all copies or substantial portions of the Software.
33 *
34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 *     OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gx.dtsi"
45#include <dt-bindings/clock/gxbb-clkc.h>
46#include <dt-bindings/clock/gxbb-aoclkc.h>
47#include <dt-bindings/gpio/meson-gxl-gpio.h>
48#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
49
50/ {
51	compatible = "amlogic,meson-gxl";
52};
53
54&ethmac {
55	reg = <0x0 0xc9410000 0x0 0x10000
56	       0x0 0xc8834540 0x0 0x4>;
57
58	clocks = <&clkc CLKID_ETH>,
59		 <&clkc CLKID_FCLK_DIV2>,
60		 <&clkc CLKID_MPLL2>;
61	clock-names = "stmmaceth", "clkin0", "clkin1";
62
63	mdio0: mdio {
64		#address-cells = <1>;
65		#size-cells = <0>;
66		compatible = "snps,dwmac-mdio";
67	};
68};
69
70&aobus {
71	pinctrl_aobus: pinctrl@14 {
72		compatible = "amlogic,meson-gxl-aobus-pinctrl";
73		#address-cells = <2>;
74		#size-cells = <2>;
75		ranges;
76
77		gpio_ao: bank@14 {
78			reg = <0x0 0x00014 0x0 0x8>,
79			      <0x0 0x0002c 0x0 0x4>,
80			      <0x0 0x00024 0x0 0x8>;
81			reg-names = "mux", "pull", "gpio";
82			gpio-controller;
83			#gpio-cells = <2>;
84			gpio-ranges = <&pinctrl_aobus 0 0 14>;
85		};
86
87		uart_ao_a_pins: uart_ao_a {
88			mux {
89				groups = "uart_tx_ao_a", "uart_rx_ao_a";
90				function = "uart_ao";
91			};
92		};
93
94		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
95			mux {
96				groups = "uart_cts_ao_a",
97				       "uart_rts_ao_a";
98				function = "uart_ao";
99			};
100		};
101
102		uart_ao_b_pins: uart_ao_b {
103			mux {
104				groups = "uart_tx_ao_b", "uart_rx_ao_b";
105				function = "uart_ao_b";
106			};
107		};
108
109		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
110			mux {
111				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
112				function = "uart_ao_b";
113			};
114		};
115
116		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
117			mux {
118				groups = "uart_cts_ao_b",
119				       "uart_rts_ao_b";
120				function = "uart_ao_b";
121			};
122		};
123
124		remote_input_ao_pins: remote_input_ao {
125			mux {
126				groups = "remote_input_ao";
127				function = "remote_input_ao";
128			};
129		};
130
131		i2c_ao_pins: i2c_ao {
132			mux {
133				groups = "i2c_sck_ao",
134				       "i2c_sda_ao";
135				function = "i2c_ao";
136			};
137		};
138
139		pwm_ao_a_3_pins: pwm_ao_a_3 {
140			mux {
141				groups = "pwm_ao_a_3";
142				function = "pwm_ao_a";
143			};
144		};
145
146		pwm_ao_a_8_pins: pwm_ao_a_8 {
147			mux {
148				groups = "pwm_ao_a_8";
149				function = "pwm_ao_a";
150			};
151		};
152
153		pwm_ao_b_pins: pwm_ao_b {
154			mux {
155				groups = "pwm_ao_b";
156				function = "pwm_ao_b";
157			};
158		};
159
160		pwm_ao_b_6_pins: pwm_ao_b_6 {
161			mux {
162				groups = "pwm_ao_b_6";
163				function = "pwm_ao_b";
164			};
165		};
166
167		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
168			mux {
169				groups = "i2s_out_ch23_ao";
170				function = "i2s_out_ao";
171			};
172		};
173
174		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
175			mux {
176				groups = "i2s_out_ch45_ao";
177				function = "i2s_out_ao";
178			};
179		};
180
181		spdif_out_ao_6_pins: spdif_out_ao_6 {
182			mux {
183				groups = "spdif_out_ao_6";
184				function = "spdif_out_ao";
185			};
186		};
187
188		spdif_out_ao_9_pins: spdif_out_ao_9 {
189			mux {
190				groups = "spdif_out_ao_9";
191				function = "spdif_out_ao";
192			};
193		};
194
195		ao_cec_pins: ao_cec {
196			mux {
197				groups = "ao_cec";
198				function = "cec_ao";
199			};
200		};
201
202		ee_cec_pins: ee_cec {
203			mux {
204				groups = "ee_cec";
205				function = "cec_ao";
206			};
207		};
208	};
209};
210
211&cec_AO {
212	clocks = <&clkc_AO CLKID_AO_CEC_32K>;
213	clock-names = "core";
214};
215
216&clkc_AO {
217	compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
218};
219
220&hdmi_tx {
221	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
222	resets = <&reset RESET_HDMITX_CAPB3>,
223		 <&reset RESET_HDMI_SYSTEM_RESET>,
224		 <&reset RESET_HDMI_TX>;
225	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
226	clocks = <&clkc CLKID_HDMI_PCLK>,
227		 <&clkc CLKID_CLK81>,
228		 <&clkc CLKID_GCLK_VENCI_INT0>;
229	clock-names = "isfr", "iahb", "venci";
230};
231
232&hiubus {
233	clkc: clock-controller@0 {
234		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
235		#clock-cells = <1>;
236		reg = <0x0 0x0 0x0 0x3db>;
237	};
238};
239
240&i2c_A {
241	clocks = <&clkc CLKID_I2C>;
242};
243
244&i2c_AO {
245	clocks = <&clkc CLKID_AO_I2C>;
246};
247
248&i2c_B {
249	clocks = <&clkc CLKID_I2C>;
250};
251
252&i2c_C {
253	clocks = <&clkc CLKID_I2C>;
254};
255
256&periphs {
257	pinctrl_periphs: pinctrl@4b0 {
258		compatible = "amlogic,meson-gxl-periphs-pinctrl";
259		#address-cells = <2>;
260		#size-cells = <2>;
261		ranges;
262
263		gpio: bank@4b0 {
264			reg = <0x0 0x004b0 0x0 0x28>,
265			      <0x0 0x004e8 0x0 0x14>,
266			      <0x0 0x00520 0x0 0x14>,
267			      <0x0 0x00430 0x0 0x40>;
268			reg-names = "mux", "pull", "pull-enable", "gpio";
269			gpio-controller;
270			#gpio-cells = <2>;
271			gpio-ranges = <&pinctrl_periphs 0 10 101>;
272		};
273
274		emmc_pins: emmc {
275			mux {
276				groups = "emmc_nand_d07",
277				       "emmc_cmd",
278				       "emmc_clk",
279				       "emmc_ds";
280				function = "emmc";
281			};
282		};
283
284		nor_pins: nor {
285			mux {
286				groups = "nor_d",
287				       "nor_q",
288				       "nor_c",
289				       "nor_cs";
290				function = "nor";
291			};
292		};
293
294		spi_pins: spi {
295			mux {
296				groups = "spi_miso",
297					"spi_mosi",
298					"spi_sclk";
299				function = "spi";
300			};
301		};
302
303		spi_ss0_pins: spi-ss0 {
304			mux {
305				groups = "spi_ss0";
306				function = "spi";
307			};
308		};
309
310		sdcard_pins: sdcard {
311			mux {
312				groups = "sdcard_d0",
313				       "sdcard_d1",
314				       "sdcard_d2",
315				       "sdcard_d3",
316				       "sdcard_cmd",
317				       "sdcard_clk";
318				function = "sdcard";
319			};
320		};
321
322		sdio_pins: sdio {
323			mux {
324				groups = "sdio_d0",
325				       "sdio_d1",
326				       "sdio_d2",
327				       "sdio_d3",
328				       "sdio_cmd",
329				       "sdio_clk";
330				function = "sdio";
331			};
332		};
333
334		sdio_irq_pins: sdio_irq {
335			mux {
336				groups = "sdio_irq";
337				function = "sdio";
338			};
339		};
340
341		uart_a_pins: uart_a {
342			mux {
343				groups = "uart_tx_a",
344				       "uart_rx_a";
345				function = "uart_a";
346			};
347		};
348
349		uart_a_cts_rts_pins: uart_a_cts_rts {
350			mux {
351				groups = "uart_cts_a",
352				       "uart_rts_a";
353				function = "uart_a";
354			};
355		};
356
357		uart_b_pins: uart_b {
358			mux {
359				groups = "uart_tx_b",
360				       "uart_rx_b";
361				function = "uart_b";
362			};
363		};
364
365		uart_b_cts_rts_pins: uart_b_cts_rts {
366			mux {
367				groups = "uart_cts_b",
368				       "uart_rts_b";
369				function = "uart_b";
370			};
371		};
372
373		uart_c_pins: uart_c {
374			mux {
375				groups = "uart_tx_c",
376				       "uart_rx_c";
377				function = "uart_c";
378			};
379		};
380
381		uart_c_cts_rts_pins: uart_c_cts_rts {
382			mux {
383				groups = "uart_cts_c",
384				       "uart_rts_c";
385				function = "uart_c";
386			};
387		};
388
389		i2c_a_pins: i2c_a {
390			mux {
391				groups = "i2c_sck_a",
392				     "i2c_sda_a";
393				function = "i2c_a";
394			};
395		};
396
397		i2c_b_pins: i2c_b {
398			mux {
399				groups = "i2c_sck_b",
400				      "i2c_sda_b";
401				function = "i2c_b";
402			};
403		};
404
405		i2c_c_pins: i2c_c {
406			mux {
407				groups = "i2c_sck_c",
408				      "i2c_sda_c";
409				function = "i2c_c";
410			};
411		};
412
413		eth_pins: eth_c {
414			mux {
415				groups = "eth_mdio",
416				       "eth_mdc",
417				       "eth_clk_rx_clk",
418				       "eth_rx_dv",
419				       "eth_rxd0",
420				       "eth_rxd1",
421				       "eth_rxd2",
422				       "eth_rxd3",
423				       "eth_rgmii_tx_clk",
424				       "eth_tx_en",
425				       "eth_txd0",
426				       "eth_txd1",
427				       "eth_txd2",
428				       "eth_txd3";
429				function = "eth";
430			};
431		};
432
433		eth_link_led_pins: eth_link_led {
434			mux {
435				groups = "eth_link_led";
436				function = "eth_led";
437			};
438		};
439
440		eth_act_led_pins: eth_act_led {
441			mux {
442				groups = "eth_act_led";
443				function = "eth_led";
444			};
445		};
446
447		pwm_a_pins: pwm_a {
448			mux {
449				groups = "pwm_a";
450				function = "pwm_a";
451			};
452		};
453
454		pwm_b_pins: pwm_b {
455			mux {
456				groups = "pwm_b";
457				function = "pwm_b";
458			};
459		};
460
461		pwm_c_pins: pwm_c {
462			mux {
463				groups = "pwm_c";
464				function = "pwm_c";
465			};
466		};
467
468		pwm_d_pins: pwm_d {
469			mux {
470				groups = "pwm_d";
471				function = "pwm_d";
472			};
473		};
474
475		pwm_e_pins: pwm_e {
476			mux {
477				groups = "pwm_e";
478				function = "pwm_e";
479			};
480		};
481
482		pwm_f_clk_pins: pwm_f_clk {
483			mux {
484				groups = "pwm_f_clk";
485				function = "pwm_f";
486			};
487		};
488
489		pwm_f_x_pins: pwm_f_x {
490			mux {
491				groups = "pwm_f_x";
492				function = "pwm_f";
493			};
494		};
495
496		hdmi_hpd_pins: hdmi_hpd {
497			mux {
498				groups = "hdmi_hpd";
499				function = "hdmi_hpd";
500			};
501		};
502
503		hdmi_i2c_pins: hdmi_i2c {
504			mux {
505				groups = "hdmi_sda", "hdmi_scl";
506				function = "hdmi_i2c";
507			};
508		};
509
510		i2s_am_clk_pins: i2s_am_clk {
511			mux {
512				groups = "i2s_am_clk";
513				function = "i2s_out";
514			};
515		};
516
517		i2s_out_ao_clk_pins: i2s_out_ao_clk {
518			mux {
519				groups = "i2s_out_ao_clk";
520				function = "i2s_out";
521			};
522		};
523
524		i2s_out_lr_clk_pins: i2s_out_lr_clk {
525			mux {
526				groups = "i2s_out_lr_clk";
527				function = "i2s_out";
528			};
529		};
530
531		i2s_out_ch01_pins: i2s_out_ch01 {
532			mux {
533				groups = "i2s_out_ch01";
534				function = "i2s_out";
535			};
536		};
537		i2sout_ch23_z_pins: i2sout_ch23_z {
538			mux {
539				groups = "i2sout_ch23_z";
540				function = "i2s_out";
541			};
542		};
543
544		i2sout_ch45_z_pins: i2sout_ch45_z {
545			mux {
546				groups = "i2sout_ch45_z";
547				function = "i2s_out";
548			};
549		};
550
551		i2sout_ch67_z_pins: i2sout_ch67_z {
552			mux {
553				groups = "i2sout_ch67_z";
554				function = "i2s_out";
555			};
556		};
557
558		spdif_out_h_pins: spdif_out_ao_h {
559			mux {
560				groups = "spdif_out_h";
561				function = "spdif_out";
562			};
563		};
564	};
565
566	eth-phy-mux {
567		compatible = "mdio-mux-mmioreg", "mdio-mux";
568		#address-cells = <1>;
569		#size-cells = <0>;
570		reg = <0x0 0x55c 0x0 0x4>;
571		mux-mask = <0xffffffff>;
572		mdio-parent-bus = <&mdio0>;
573
574		internal_mdio: mdio@e40908ff {
575			reg = <0xe40908ff>;
576			#address-cells = <1>;
577			#size-cells = <0>;
578
579			internal_phy: ethernet-phy@8 {
580				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
581				reg = <8>;
582				max-speed = <100>;
583			};
584		};
585
586		external_mdio: mdio@2009087f {
587			reg = <0x2009087f>;
588			#address-cells = <1>;
589			#size-cells = <0>;
590		};
591	};
592};
593
594&saradc {
595	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
596	clocks = <&xtal>,
597		 <&clkc CLKID_SAR_ADC>,
598		 <&clkc CLKID_SANA>,
599		 <&clkc CLKID_SAR_ADC_CLK>,
600		 <&clkc CLKID_SAR_ADC_SEL>;
601	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
602};
603
604&sd_emmc_a {
605	clocks = <&clkc CLKID_SD_EMMC_A>,
606		 <&clkc CLKID_SD_EMMC_A_CLK0>,
607		 <&clkc CLKID_FCLK_DIV2>;
608	clock-names = "core", "clkin0", "clkin1";
609};
610
611&sd_emmc_b {
612	clocks = <&clkc CLKID_SD_EMMC_B>,
613		 <&clkc CLKID_SD_EMMC_B_CLK0>,
614		 <&clkc CLKID_FCLK_DIV2>;
615       clock-names = "core", "clkin0", "clkin1";
616};
617
618&sd_emmc_c {
619	clocks = <&clkc CLKID_SD_EMMC_C>,
620		 <&clkc CLKID_SD_EMMC_C_CLK0>,
621		 <&clkc CLKID_FCLK_DIV2>;
622	clock-names = "core", "clkin0", "clkin1";
623};
624
625&spicc {
626	clocks = <&clkc CLKID_SPICC>;
627	clock-names = "core";
628	resets = <&reset RESET_PERIPHS_SPICC>;
629	num-cs = <1>;
630};
631
632&spifc {
633	clocks = <&clkc CLKID_SPI>;
634};
635
636&uart_A {
637	clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
638	clock-names = "xtal", "core", "baud";
639};
640
641&uart_AO {
642	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
643	clock-names = "xtal", "pclk", "baud";
644};
645
646&uart_AO_B {
647	clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
648	clock-names = "xtal", "pclk", "baud";
649};
650
651&uart_B {
652	clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
653	clock-names = "xtal", "core", "baud";
654};
655
656&uart_C {
657	clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
658	clock-names = "xtal", "core", "baud";
659};
660
661&vpu {
662	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
663};
664