1/* 2 * Copyright (c) 2016 Endless Computers, Inc. 3 * Author: Carlo Caione <carlo@endlessm.com> 4 * 5 * This file is dual-licensed: you can use it either under the terms 6 * of the GPL or the X11 license, at your option. Note that this dual 7 * licensing only applies to this file, and not this project as a 8 * whole. 9 * 10 * a) This library is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of the 13 * License, or (at your option) any later version. 14 * 15 * This library is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * Or, alternatively, 21 * 22 * b) Permission is hereby granted, free of charge, to any person 23 * obtaining a copy of this software and associated documentation 24 * files (the "Software"), to deal in the Software without 25 * restriction, including without limitation the rights to use, 26 * copy, modify, merge, publish, distribute, sublicense, and/or 27 * sell copies of the Software, and to permit persons to whom the 28 * Software is furnished to do so, subject to the following 29 * conditions: 30 * 31 * The above copyright notice and this permission notice shall be 32 * included in all copies or substantial portions of the Software. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 36 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 38 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 39 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 40 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 41 * OTHER DEALINGS IN THE SOFTWARE. 42 */ 43 44#include "meson-gx.dtsi" 45#include <dt-bindings/clock/gxbb-clkc.h> 46#include <dt-bindings/clock/gxbb-aoclkc.h> 47#include <dt-bindings/gpio/meson-gxl-gpio.h> 48#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> 49 50/ { 51 compatible = "amlogic,meson-gxl"; 52 53 reserved-memory { 54 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 55 secmon_reserved_alt: secmon@05000000 { 56 reg = <0x0 0x05000000 0x0 0x300000>; 57 no-map; 58 }; 59 }; 60}; 61 62ðmac { 63 reg = <0x0 0xc9410000 0x0 0x10000 64 0x0 0xc8834540 0x0 0x4>; 65 66 clocks = <&clkc CLKID_ETH>, 67 <&clkc CLKID_FCLK_DIV2>, 68 <&clkc CLKID_MPLL2>; 69 clock-names = "stmmaceth", "clkin0", "clkin1"; 70 71 mdio0: mdio { 72 #address-cells = <1>; 73 #size-cells = <0>; 74 compatible = "snps,dwmac-mdio"; 75 }; 76}; 77 78&aobus { 79 pinctrl_aobus: pinctrl@14 { 80 compatible = "amlogic,meson-gxl-aobus-pinctrl"; 81 #address-cells = <2>; 82 #size-cells = <2>; 83 ranges; 84 85 gpio_ao: bank@14 { 86 reg = <0x0 0x00014 0x0 0x8>, 87 <0x0 0x0002c 0x0 0x4>, 88 <0x0 0x00024 0x0 0x8>; 89 reg-names = "mux", "pull", "gpio"; 90 gpio-controller; 91 #gpio-cells = <2>; 92 gpio-ranges = <&pinctrl_aobus 0 0 14>; 93 }; 94 95 uart_ao_a_pins: uart_ao_a { 96 mux { 97 groups = "uart_tx_ao_a", "uart_rx_ao_a"; 98 function = "uart_ao"; 99 }; 100 }; 101 102 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 103 mux { 104 groups = "uart_cts_ao_a", 105 "uart_rts_ao_a"; 106 function = "uart_ao"; 107 }; 108 }; 109 110 uart_ao_b_pins: uart_ao_b { 111 mux { 112 groups = "uart_tx_ao_b", "uart_rx_ao_b"; 113 function = "uart_ao_b"; 114 }; 115 }; 116 117 uart_ao_b_0_1_pins: uart_ao_b_0_1 { 118 mux { 119 groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1"; 120 function = "uart_ao_b"; 121 }; 122 }; 123 124 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 125 mux { 126 groups = "uart_cts_ao_b", 127 "uart_rts_ao_b"; 128 function = "uart_ao_b"; 129 }; 130 }; 131 132 remote_input_ao_pins: remote_input_ao { 133 mux { 134 groups = "remote_input_ao"; 135 function = "remote_input_ao"; 136 }; 137 }; 138 139 i2c_ao_pins: i2c_ao { 140 mux { 141 groups = "i2c_sck_ao", 142 "i2c_sda_ao"; 143 function = "i2c_ao"; 144 }; 145 }; 146 147 pwm_ao_a_3_pins: pwm_ao_a_3 { 148 mux { 149 groups = "pwm_ao_a_3"; 150 function = "pwm_ao_a"; 151 }; 152 }; 153 154 pwm_ao_a_8_pins: pwm_ao_a_8 { 155 mux { 156 groups = "pwm_ao_a_8"; 157 function = "pwm_ao_a"; 158 }; 159 }; 160 161 pwm_ao_b_pins: pwm_ao_b { 162 mux { 163 groups = "pwm_ao_b"; 164 function = "pwm_ao_b"; 165 }; 166 }; 167 168 pwm_ao_b_6_pins: pwm_ao_b_6 { 169 mux { 170 groups = "pwm_ao_b_6"; 171 function = "pwm_ao_b"; 172 }; 173 }; 174 175 i2s_out_ch23_ao_pins: i2s_out_ch23_ao { 176 mux { 177 groups = "i2s_out_ch23_ao"; 178 function = "i2s_out_ao"; 179 }; 180 }; 181 182 i2s_out_ch45_ao_pins: i2s_out_ch45_ao { 183 mux { 184 groups = "i2s_out_ch45_ao"; 185 function = "i2s_out_ao"; 186 }; 187 }; 188 189 spdif_out_ao_6_pins: spdif_out_ao_6 { 190 mux { 191 groups = "spdif_out_ao_6"; 192 function = "spdif_out_ao"; 193 }; 194 }; 195 196 spdif_out_ao_9_pins: spdif_out_ao_9 { 197 mux { 198 groups = "spdif_out_ao_9"; 199 function = "spdif_out_ao"; 200 }; 201 }; 202 203 ao_cec_pins: ao_cec { 204 mux { 205 groups = "ao_cec"; 206 function = "cec_ao"; 207 }; 208 }; 209 210 ee_cec_pins: ee_cec { 211 mux { 212 groups = "ee_cec"; 213 function = "cec_ao"; 214 }; 215 }; 216 }; 217}; 218 219&cec_AO { 220 clocks = <&clkc_AO CLKID_AO_CEC_32K>; 221 clock-names = "core"; 222}; 223 224&clkc_AO { 225 compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc"; 226}; 227 228&hdmi_tx { 229 compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi"; 230 resets = <&reset RESET_HDMITX_CAPB3>, 231 <&reset RESET_HDMI_SYSTEM_RESET>, 232 <&reset RESET_HDMI_TX>; 233 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 234 clocks = <&clkc CLKID_HDMI_PCLK>, 235 <&clkc CLKID_CLK81>, 236 <&clkc CLKID_GCLK_VENCI_INT0>; 237 clock-names = "isfr", "iahb", "venci"; 238}; 239 240&hiubus { 241 clkc: clock-controller@0 { 242 compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc"; 243 #clock-cells = <1>; 244 reg = <0x0 0x0 0x0 0x3db>; 245 }; 246}; 247 248&i2c_A { 249 clocks = <&clkc CLKID_I2C>; 250}; 251 252&i2c_AO { 253 clocks = <&clkc CLKID_AO_I2C>; 254}; 255 256&i2c_B { 257 clocks = <&clkc CLKID_I2C>; 258}; 259 260&i2c_C { 261 clocks = <&clkc CLKID_I2C>; 262}; 263 264&periphs { 265 pinctrl_periphs: pinctrl@4b0 { 266 compatible = "amlogic,meson-gxl-periphs-pinctrl"; 267 #address-cells = <2>; 268 #size-cells = <2>; 269 ranges; 270 271 gpio: bank@4b0 { 272 reg = <0x0 0x004b0 0x0 0x28>, 273 <0x0 0x004e8 0x0 0x14>, 274 <0x0 0x00520 0x0 0x14>, 275 <0x0 0x00430 0x0 0x40>; 276 reg-names = "mux", "pull", "pull-enable", "gpio"; 277 gpio-controller; 278 #gpio-cells = <2>; 279 gpio-ranges = <&pinctrl_periphs 0 0 100>; 280 }; 281 282 emmc_pins: emmc { 283 mux { 284 groups = "emmc_nand_d07", 285 "emmc_cmd", 286 "emmc_clk"; 287 function = "emmc"; 288 }; 289 }; 290 291 emmc_ds_pins: emmc-ds { 292 mux { 293 groups = "emmc_ds"; 294 function = "emmc"; 295 }; 296 }; 297 298 emmc_clk_gate_pins: emmc_clk_gate { 299 mux { 300 groups = "BOOT_8"; 301 function = "gpio_periphs"; 302 }; 303 cfg-pull-down { 304 pins = "BOOT_8"; 305 bias-pull-down; 306 }; 307 }; 308 309 nor_pins: nor { 310 mux { 311 groups = "nor_d", 312 "nor_q", 313 "nor_c", 314 "nor_cs"; 315 function = "nor"; 316 }; 317 }; 318 319 spi_pins: spi { 320 mux { 321 groups = "spi_miso", 322 "spi_mosi", 323 "spi_sclk"; 324 function = "spi"; 325 }; 326 }; 327 328 spi_ss0_pins: spi-ss0 { 329 mux { 330 groups = "spi_ss0"; 331 function = "spi"; 332 }; 333 }; 334 335 sdcard_pins: sdcard { 336 mux { 337 groups = "sdcard_d0", 338 "sdcard_d1", 339 "sdcard_d2", 340 "sdcard_d3", 341 "sdcard_cmd", 342 "sdcard_clk"; 343 function = "sdcard"; 344 }; 345 }; 346 347 sdcard_clk_gate_pins: sdcard_clk_gate { 348 mux { 349 groups = "CARD_2"; 350 function = "gpio_periphs"; 351 }; 352 cfg-pull-down { 353 pins = "CARD_2"; 354 bias-pull-down; 355 }; 356 }; 357 358 sdio_pins: sdio { 359 mux { 360 groups = "sdio_d0", 361 "sdio_d1", 362 "sdio_d2", 363 "sdio_d3", 364 "sdio_cmd", 365 "sdio_clk"; 366 function = "sdio"; 367 }; 368 }; 369 370 sdio_clk_gate_pins: sdio_clk_gate { 371 mux { 372 groups = "GPIOX_4"; 373 function = "gpio_periphs"; 374 }; 375 cfg-pull-down { 376 pins = "GPIOX_4"; 377 bias-pull-down; 378 }; 379 }; 380 381 sdio_irq_pins: sdio_irq { 382 mux { 383 groups = "sdio_irq"; 384 function = "sdio"; 385 }; 386 }; 387 388 uart_a_pins: uart_a { 389 mux { 390 groups = "uart_tx_a", 391 "uart_rx_a"; 392 function = "uart_a"; 393 }; 394 }; 395 396 uart_a_cts_rts_pins: uart_a_cts_rts { 397 mux { 398 groups = "uart_cts_a", 399 "uart_rts_a"; 400 function = "uart_a"; 401 }; 402 }; 403 404 uart_b_pins: uart_b { 405 mux { 406 groups = "uart_tx_b", 407 "uart_rx_b"; 408 function = "uart_b"; 409 }; 410 }; 411 412 uart_b_cts_rts_pins: uart_b_cts_rts { 413 mux { 414 groups = "uart_cts_b", 415 "uart_rts_b"; 416 function = "uart_b"; 417 }; 418 }; 419 420 uart_c_pins: uart_c { 421 mux { 422 groups = "uart_tx_c", 423 "uart_rx_c"; 424 function = "uart_c"; 425 }; 426 }; 427 428 uart_c_cts_rts_pins: uart_c_cts_rts { 429 mux { 430 groups = "uart_cts_c", 431 "uart_rts_c"; 432 function = "uart_c"; 433 }; 434 }; 435 436 i2c_a_pins: i2c_a { 437 mux { 438 groups = "i2c_sck_a", 439 "i2c_sda_a"; 440 function = "i2c_a"; 441 }; 442 }; 443 444 i2c_b_pins: i2c_b { 445 mux { 446 groups = "i2c_sck_b", 447 "i2c_sda_b"; 448 function = "i2c_b"; 449 }; 450 }; 451 452 i2c_c_pins: i2c_c { 453 mux { 454 groups = "i2c_sck_c", 455 "i2c_sda_c"; 456 function = "i2c_c"; 457 }; 458 }; 459 460 eth_pins: eth_c { 461 mux { 462 groups = "eth_mdio", 463 "eth_mdc", 464 "eth_clk_rx_clk", 465 "eth_rx_dv", 466 "eth_rxd0", 467 "eth_rxd1", 468 "eth_rxd2", 469 "eth_rxd3", 470 "eth_rgmii_tx_clk", 471 "eth_tx_en", 472 "eth_txd0", 473 "eth_txd1", 474 "eth_txd2", 475 "eth_txd3"; 476 function = "eth"; 477 }; 478 }; 479 480 eth_link_led_pins: eth_link_led { 481 mux { 482 groups = "eth_link_led"; 483 function = "eth_led"; 484 }; 485 }; 486 487 eth_act_led_pins: eth_act_led { 488 mux { 489 groups = "eth_act_led"; 490 function = "eth_led"; 491 }; 492 }; 493 494 pwm_a_pins: pwm_a { 495 mux { 496 groups = "pwm_a"; 497 function = "pwm_a"; 498 }; 499 }; 500 501 pwm_b_pins: pwm_b { 502 mux { 503 groups = "pwm_b"; 504 function = "pwm_b"; 505 }; 506 }; 507 508 pwm_c_pins: pwm_c { 509 mux { 510 groups = "pwm_c"; 511 function = "pwm_c"; 512 }; 513 }; 514 515 pwm_d_pins: pwm_d { 516 mux { 517 groups = "pwm_d"; 518 function = "pwm_d"; 519 }; 520 }; 521 522 pwm_e_pins: pwm_e { 523 mux { 524 groups = "pwm_e"; 525 function = "pwm_e"; 526 }; 527 }; 528 529 pwm_f_clk_pins: pwm_f_clk { 530 mux { 531 groups = "pwm_f_clk"; 532 function = "pwm_f"; 533 }; 534 }; 535 536 pwm_f_x_pins: pwm_f_x { 537 mux { 538 groups = "pwm_f_x"; 539 function = "pwm_f"; 540 }; 541 }; 542 543 hdmi_hpd_pins: hdmi_hpd { 544 mux { 545 groups = "hdmi_hpd"; 546 function = "hdmi_hpd"; 547 }; 548 }; 549 550 hdmi_i2c_pins: hdmi_i2c { 551 mux { 552 groups = "hdmi_sda", "hdmi_scl"; 553 function = "hdmi_i2c"; 554 }; 555 }; 556 557 i2s_am_clk_pins: i2s_am_clk { 558 mux { 559 groups = "i2s_am_clk"; 560 function = "i2s_out"; 561 }; 562 }; 563 564 i2s_out_ao_clk_pins: i2s_out_ao_clk { 565 mux { 566 groups = "i2s_out_ao_clk"; 567 function = "i2s_out"; 568 }; 569 }; 570 571 i2s_out_lr_clk_pins: i2s_out_lr_clk { 572 mux { 573 groups = "i2s_out_lr_clk"; 574 function = "i2s_out"; 575 }; 576 }; 577 578 i2s_out_ch01_pins: i2s_out_ch01 { 579 mux { 580 groups = "i2s_out_ch01"; 581 function = "i2s_out"; 582 }; 583 }; 584 i2sout_ch23_z_pins: i2sout_ch23_z { 585 mux { 586 groups = "i2sout_ch23_z"; 587 function = "i2s_out"; 588 }; 589 }; 590 591 i2sout_ch45_z_pins: i2sout_ch45_z { 592 mux { 593 groups = "i2sout_ch45_z"; 594 function = "i2s_out"; 595 }; 596 }; 597 598 i2sout_ch67_z_pins: i2sout_ch67_z { 599 mux { 600 groups = "i2sout_ch67_z"; 601 function = "i2s_out"; 602 }; 603 }; 604 605 spdif_out_h_pins: spdif_out_ao_h { 606 mux { 607 groups = "spdif_out_h"; 608 function = "spdif_out"; 609 }; 610 }; 611 }; 612 613 eth-phy-mux { 614 compatible = "mdio-mux-mmioreg", "mdio-mux"; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 reg = <0x0 0x55c 0x0 0x4>; 618 mux-mask = <0xffffffff>; 619 mdio-parent-bus = <&mdio0>; 620 621 internal_mdio: mdio@e40908ff { 622 reg = <0xe40908ff>; 623 #address-cells = <1>; 624 #size-cells = <0>; 625 626 internal_phy: ethernet-phy@8 { 627 compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22"; 628 reg = <8>; 629 max-speed = <100>; 630 }; 631 }; 632 633 external_mdio: mdio@2009087f { 634 reg = <0x2009087f>; 635 #address-cells = <1>; 636 #size-cells = <0>; 637 }; 638 }; 639}; 640 641&saradc { 642 compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc"; 643 clocks = <&xtal>, 644 <&clkc CLKID_SAR_ADC>, 645 <&clkc CLKID_SANA>, 646 <&clkc CLKID_SAR_ADC_CLK>, 647 <&clkc CLKID_SAR_ADC_SEL>; 648 clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel"; 649}; 650 651&sd_emmc_a { 652 clocks = <&clkc CLKID_SD_EMMC_A>, 653 <&clkc CLKID_SD_EMMC_A_CLK0>, 654 <&clkc CLKID_FCLK_DIV2>; 655 clock-names = "core", "clkin0", "clkin1"; 656}; 657 658&sd_emmc_b { 659 clocks = <&clkc CLKID_SD_EMMC_B>, 660 <&clkc CLKID_SD_EMMC_B_CLK0>, 661 <&clkc CLKID_FCLK_DIV2>; 662 clock-names = "core", "clkin0", "clkin1"; 663}; 664 665&sd_emmc_c { 666 clocks = <&clkc CLKID_SD_EMMC_C>, 667 <&clkc CLKID_SD_EMMC_C_CLK0>, 668 <&clkc CLKID_FCLK_DIV2>; 669 clock-names = "core", "clkin0", "clkin1"; 670}; 671 672&spicc { 673 clocks = <&clkc CLKID_SPICC>; 674 clock-names = "core"; 675 resets = <&reset RESET_PERIPHS_SPICC>; 676 num-cs = <1>; 677}; 678 679&spifc { 680 clocks = <&clkc CLKID_SPI>; 681}; 682 683&uart_A { 684 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 685 clock-names = "xtal", "core", "baud"; 686}; 687 688&uart_AO { 689 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; 690 clock-names = "xtal", "pclk", "baud"; 691}; 692 693&uart_AO_B { 694 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; 695 clock-names = "xtal", "pclk", "baud"; 696}; 697 698&uart_B { 699 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 700 clock-names = "xtal", "core", "baud"; 701}; 702 703&uart_C { 704 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 705 clock-names = "xtal", "core", "baud"; 706}; 707 708&vpu { 709 compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu"; 710}; 711