1/*
2 * Copyright (c) 2016 Endless Computers, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 *  a) This library is free software; you can redistribute it and/or
11 *     modify it under the terms of the GNU General Public License as
12 *     published by the Free Software Foundation; either version 2 of the
13 *     License, or (at your option) any later version.
14 *
15 *     This library is distributed in the hope that it will be useful,
16 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
17 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18 *     GNU General Public License for more details.
19 *
20 * Or, alternatively,
21 *
22 *  b) Permission is hereby granted, free of charge, to any person
23 *     obtaining a copy of this software and associated documentation
24 *     files (the "Software"), to deal in the Software without
25 *     restriction, including without limitation the rights to use,
26 *     copy, modify, merge, publish, distribute, sublicense, and/or
27 *     sell copies of the Software, and to permit persons to whom the
28 *     Software is furnished to do so, subject to the following
29 *     conditions:
30 *
31 *     The above copyright notice and this permission notice shall be
32 *     included in all copies or substantial portions of the Software.
33 *
34 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
36 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
37 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
38 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
39 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
40 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
41 *     OTHER DEALINGS IN THE SOFTWARE.
42 */
43
44#include "meson-gx.dtsi"
45#include <dt-bindings/clock/gxbb-clkc.h>
46#include <dt-bindings/gpio/meson-gxl-gpio.h>
47#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
48
49/ {
50	compatible = "amlogic,meson-gxl";
51};
52
53&ethmac {
54	reg = <0x0 0xc9410000 0x0 0x10000
55	       0x0 0xc8834540 0x0 0x4>;
56
57	clocks = <&clkc CLKID_ETH>,
58		 <&clkc CLKID_FCLK_DIV2>,
59		 <&clkc CLKID_MPLL2>;
60	clock-names = "stmmaceth", "clkin0", "clkin1";
61
62	mdio0: mdio {
63		#address-cells = <1>;
64		#size-cells = <0>;
65		compatible = "snps,dwmac-mdio";
66	};
67};
68
69&aobus {
70	pinctrl_aobus: pinctrl@14 {
71		compatible = "amlogic,meson-gxl-aobus-pinctrl";
72		#address-cells = <2>;
73		#size-cells = <2>;
74		ranges;
75
76		gpio_ao: bank@14 {
77			reg = <0x0 0x00014 0x0 0x8>,
78			      <0x0 0x0002c 0x0 0x4>,
79			      <0x0 0x00024 0x0 0x8>;
80			reg-names = "mux", "pull", "gpio";
81			gpio-controller;
82			#gpio-cells = <2>;
83			gpio-ranges = <&pinctrl_aobus 0 0 14>;
84		};
85
86		uart_ao_a_pins: uart_ao_a {
87			mux {
88				groups = "uart_tx_ao_a", "uart_rx_ao_a";
89				function = "uart_ao";
90			};
91		};
92
93		uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
94			mux {
95				groups = "uart_cts_ao_a",
96				       "uart_rts_ao_a";
97				function = "uart_ao";
98			};
99		};
100
101		uart_ao_b_pins: uart_ao_b {
102			mux {
103				groups = "uart_tx_ao_b", "uart_rx_ao_b";
104				function = "uart_ao_b";
105			};
106		};
107
108		uart_ao_b_0_1_pins: uart_ao_b_0_1 {
109			mux {
110				groups = "uart_tx_ao_b_0", "uart_rx_ao_b_1";
111				function = "uart_ao_b";
112			};
113		};
114
115		uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
116			mux {
117				groups = "uart_cts_ao_b",
118				       "uart_rts_ao_b";
119				function = "uart_ao_b";
120			};
121		};
122
123		remote_input_ao_pins: remote_input_ao {
124			mux {
125				groups = "remote_input_ao";
126				function = "remote_input_ao";
127			};
128		};
129
130		i2c_ao_pins: i2c_ao {
131			mux {
132				groups = "i2c_sck_ao",
133				       "i2c_sda_ao";
134				function = "i2c_ao";
135			};
136		};
137
138		pwm_ao_a_3_pins: pwm_ao_a_3 {
139			mux {
140				groups = "pwm_ao_a_3";
141				function = "pwm_ao_a";
142			};
143		};
144
145		pwm_ao_a_8_pins: pwm_ao_a_8 {
146			mux {
147				groups = "pwm_ao_a_8";
148				function = "pwm_ao_a";
149			};
150		};
151
152		pwm_ao_b_pins: pwm_ao_b {
153			mux {
154				groups = "pwm_ao_b";
155				function = "pwm_ao_b";
156			};
157		};
158
159		pwm_ao_b_6_pins: pwm_ao_b_6 {
160			mux {
161				groups = "pwm_ao_b_6";
162				function = "pwm_ao_b";
163			};
164		};
165
166		i2s_out_ch23_ao_pins: i2s_out_ch23_ao {
167			mux {
168				groups = "i2s_out_ch23_ao";
169				function = "i2s_out_ao";
170			};
171		};
172
173		i2s_out_ch45_ao_pins: i2s_out_ch45_ao {
174			mux {
175				groups = "i2s_out_ch45_ao";
176				function = "i2s_out_ao";
177			};
178		};
179
180		spdif_out_ao_6_pins: spdif_out_ao_6 {
181			mux {
182				groups = "spdif_out_ao_6";
183				function = "spdif_out_ao";
184			};
185		};
186
187		spdif_out_ao_9_pins: spdif_out_ao_9 {
188			mux {
189				groups = "spdif_out_ao_9";
190				function = "spdif_out_ao";
191			};
192		};
193
194		ao_cec_pins: ao_cec {
195			mux {
196				groups = "ao_cec";
197				function = "cec_ao";
198			};
199		};
200
201		ee_cec_pins: ee_cec {
202			mux {
203				groups = "ee_cec";
204				function = "cec_ao";
205			};
206		};
207	};
208};
209
210&hdmi_tx {
211	compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
212	resets = <&reset RESET_HDMITX_CAPB3>,
213		 <&reset RESET_HDMI_SYSTEM_RESET>,
214		 <&reset RESET_HDMI_TX>;
215	reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy";
216	clocks = <&clkc CLKID_HDMI_PCLK>,
217		 <&clkc CLKID_CLK81>,
218		 <&clkc CLKID_GCLK_VENCI_INT0>;
219	clock-names = "isfr", "iahb", "venci";
220};
221
222&hiubus {
223	clkc: clock-controller@0 {
224		compatible = "amlogic,gxl-clkc", "amlogic,gxbb-clkc";
225		#clock-cells = <1>;
226		reg = <0x0 0x0 0x0 0x3db>;
227	};
228};
229
230&i2c_A {
231	clocks = <&clkc CLKID_I2C>;
232};
233
234&i2c_AO {
235	clocks = <&clkc CLKID_AO_I2C>;
236};
237
238&i2c_B {
239	clocks = <&clkc CLKID_I2C>;
240};
241
242&i2c_C {
243	clocks = <&clkc CLKID_I2C>;
244};
245
246&periphs {
247	pinctrl_periphs: pinctrl@4b0 {
248		compatible = "amlogic,meson-gxl-periphs-pinctrl";
249		#address-cells = <2>;
250		#size-cells = <2>;
251		ranges;
252
253		gpio: bank@4b0 {
254			reg = <0x0 0x004b0 0x0 0x28>,
255			      <0x0 0x004e8 0x0 0x14>,
256			      <0x0 0x00520 0x0 0x14>,
257			      <0x0 0x00430 0x0 0x40>;
258			reg-names = "mux", "pull", "pull-enable", "gpio";
259			gpio-controller;
260			#gpio-cells = <2>;
261			gpio-ranges = <&pinctrl_periphs 0 10 101>;
262		};
263
264		emmc_pins: emmc {
265			mux {
266				groups = "emmc_nand_d07",
267				       "emmc_cmd",
268				       "emmc_clk",
269				       "emmc_ds";
270				function = "emmc";
271			};
272		};
273
274		nor_pins: nor {
275			mux {
276				groups = "nor_d",
277				       "nor_q",
278				       "nor_c",
279				       "nor_cs";
280				function = "nor";
281			};
282		};
283
284		sdcard_pins: sdcard {
285			mux {
286				groups = "sdcard_d0",
287				       "sdcard_d1",
288				       "sdcard_d2",
289				       "sdcard_d3",
290				       "sdcard_cmd",
291				       "sdcard_clk";
292				function = "sdcard";
293			};
294		};
295
296		sdio_pins: sdio {
297			mux {
298				groups = "sdio_d0",
299				       "sdio_d1",
300				       "sdio_d2",
301				       "sdio_d3",
302				       "sdio_cmd",
303				       "sdio_clk";
304				function = "sdio";
305			};
306		};
307
308		sdio_irq_pins: sdio_irq {
309			mux {
310				groups = "sdio_irq";
311				function = "sdio";
312			};
313		};
314
315		uart_a_pins: uart_a {
316			mux {
317				groups = "uart_tx_a",
318				       "uart_rx_a";
319				function = "uart_a";
320			};
321		};
322
323		uart_a_cts_rts_pins: uart_a_cts_rts {
324			mux {
325				groups = "uart_cts_a",
326				       "uart_rts_a";
327				function = "uart_a";
328			};
329		};
330
331		uart_b_pins: uart_b {
332			mux {
333				groups = "uart_tx_b",
334				       "uart_rx_b";
335				function = "uart_b";
336			};
337		};
338
339		uart_b_cts_rts_pins: uart_b_cts_rts {
340			mux {
341				groups = "uart_cts_b",
342				       "uart_rts_b";
343				function = "uart_b";
344			};
345		};
346
347		uart_c_pins: uart_c {
348			mux {
349				groups = "uart_tx_c",
350				       "uart_rx_c";
351				function = "uart_c";
352			};
353		};
354
355		uart_c_cts_rts_pins: uart_c_cts_rts {
356			mux {
357				groups = "uart_cts_c",
358				       "uart_rts_c";
359				function = "uart_c";
360			};
361		};
362
363		i2c_a_pins: i2c_a {
364			mux {
365				groups = "i2c_sck_a",
366				     "i2c_sda_a";
367				function = "i2c_a";
368			};
369		};
370
371		i2c_b_pins: i2c_b {
372			mux {
373				groups = "i2c_sck_b",
374				      "i2c_sda_b";
375				function = "i2c_b";
376			};
377		};
378
379		i2c_c_pins: i2c_c {
380			mux {
381				groups = "i2c_sck_c",
382				      "i2c_sda_c";
383				function = "i2c_c";
384			};
385		};
386
387		eth_pins: eth_c {
388			mux {
389				groups = "eth_mdio",
390				       "eth_mdc",
391				       "eth_clk_rx_clk",
392				       "eth_rx_dv",
393				       "eth_rxd0",
394				       "eth_rxd1",
395				       "eth_rxd2",
396				       "eth_rxd3",
397				       "eth_rgmii_tx_clk",
398				       "eth_tx_en",
399				       "eth_txd0",
400				       "eth_txd1",
401				       "eth_txd2",
402				       "eth_txd3";
403				function = "eth";
404			};
405		};
406
407		eth_link_led_pins: eth_link_led {
408			mux {
409				groups = "eth_link_led";
410				function = "eth_led";
411			};
412		};
413
414		eth_act_led_pins: eth_act_led {
415			mux {
416				groups = "eth_act_led";
417				function = "eth_led";
418			};
419		};
420
421		pwm_a_pins: pwm_a {
422			mux {
423				groups = "pwm_a";
424				function = "pwm_a";
425			};
426		};
427
428		pwm_b_pins: pwm_b {
429			mux {
430				groups = "pwm_b";
431				function = "pwm_b";
432			};
433		};
434
435		pwm_c_pins: pwm_c {
436			mux {
437				groups = "pwm_c";
438				function = "pwm_c";
439			};
440		};
441
442		pwm_d_pins: pwm_d {
443			mux {
444				groups = "pwm_d";
445				function = "pwm_d";
446			};
447		};
448
449		pwm_e_pins: pwm_e {
450			mux {
451				groups = "pwm_e";
452				function = "pwm_e";
453			};
454		};
455
456		pwm_f_clk_pins: pwm_f_clk {
457			mux {
458				groups = "pwm_f_clk";
459				function = "pwm_f";
460			};
461		};
462
463		pwm_f_x_pins: pwm_f_x {
464			mux {
465				groups = "pwm_f_x";
466				function = "pwm_f";
467			};
468		};
469
470		hdmi_hpd_pins: hdmi_hpd {
471			mux {
472				groups = "hdmi_hpd";
473				function = "hdmi_hpd";
474			};
475		};
476
477		hdmi_i2c_pins: hdmi_i2c {
478			mux {
479				groups = "hdmi_sda", "hdmi_scl";
480				function = "hdmi_i2c";
481			};
482		};
483
484		i2s_am_clk_pins: i2s_am_clk {
485			mux {
486				groups = "i2s_am_clk";
487				function = "i2s_out";
488			};
489		};
490
491		i2s_out_ao_clk_pins: i2s_out_ao_clk {
492			mux {
493				groups = "i2s_out_ao_clk";
494				function = "i2s_out";
495			};
496		};
497
498		i2s_out_lr_clk_pins: i2s_out_lr_clk {
499			mux {
500				groups = "i2s_out_lr_clk";
501				function = "i2s_out";
502			};
503		};
504
505		i2s_out_ch01_pins: i2s_out_ch01 {
506			mux {
507				groups = "i2s_out_ch01";
508				function = "i2s_out";
509			};
510		};
511		i2sout_ch23_z_pins: i2sout_ch23_z {
512			mux {
513				groups = "i2sout_ch23_z";
514				function = "i2s_out";
515			};
516		};
517
518		i2sout_ch45_z_pins: i2sout_ch45_z {
519			mux {
520				groups = "i2sout_ch45_z";
521				function = "i2s_out";
522			};
523		};
524
525		i2sout_ch67_z_pins: i2sout_ch67_z {
526			mux {
527				groups = "i2sout_ch67_z";
528				function = "i2s_out";
529			};
530		};
531
532		spdif_out_h_pins: spdif_out_ao_h {
533			mux {
534				groups = "spdif_out_h";
535				function = "spdif_out";
536			};
537		};
538	};
539
540	eth-phy-mux {
541		compatible = "mdio-mux-mmioreg", "mdio-mux";
542		#address-cells = <1>;
543		#size-cells = <0>;
544		reg = <0x0 0x55c 0x0 0x4>;
545		mux-mask = <0xffffffff>;
546		mdio-parent-bus = <&mdio0>;
547
548		internal_mdio: mdio@e40908ff {
549			reg = <0xe40908ff>;
550			#address-cells = <1>;
551			#size-cells = <0>;
552
553			internal_phy: ethernet-phy@8 {
554				compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
555				reg = <8>;
556				max-speed = <100>;
557			};
558		};
559
560		external_mdio: mdio@2009087f {
561			reg = <0x2009087f>;
562			#address-cells = <1>;
563			#size-cells = <0>;
564		};
565	};
566};
567
568&saradc {
569	compatible = "amlogic,meson-gxl-saradc", "amlogic,meson-saradc";
570	clocks = <&xtal>,
571		 <&clkc CLKID_SAR_ADC>,
572		 <&clkc CLKID_SANA>,
573		 <&clkc CLKID_SAR_ADC_CLK>,
574		 <&clkc CLKID_SAR_ADC_SEL>;
575	clock-names = "clkin", "core", "sana", "adc_clk", "adc_sel";
576};
577
578&sd_emmc_a {
579	clocks = <&clkc CLKID_SD_EMMC_A>,
580		 <&xtal>,
581		 <&clkc CLKID_FCLK_DIV2>;
582	clock-names = "core", "clkin0", "clkin1";
583};
584
585&sd_emmc_b {
586	clocks = <&clkc CLKID_SD_EMMC_B>,
587		 <&xtal>,
588		 <&clkc CLKID_FCLK_DIV2>;
589       clock-names = "core", "clkin0", "clkin1";
590};
591
592&sd_emmc_c {
593	clocks = <&clkc CLKID_SD_EMMC_C>,
594		 <&xtal>,
595		 <&clkc CLKID_FCLK_DIV2>;
596	clock-names = "core", "clkin0", "clkin1";
597};
598
599&spifc {
600	clocks = <&clkc CLKID_SPI>;
601};
602
603&vpu {
604	compatible = "amlogic,meson-gxl-vpu", "amlogic,meson-gx-vpu";
605};
606