1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2016 Andreas Färber
4 *
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Neil Armstrong <narmstrong@baylibre.com>
7 *
8 * Copyright (c) 2016 Endless Computers, Inc.
9 * Author: Carlo Caione <carlo@endlessm.com>
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
15
16/ {
17	interrupt-parent = <&gic>;
18	#address-cells = <2>;
19	#size-cells = <2>;
20
21	reserved-memory {
22		#address-cells = <2>;
23		#size-cells = <2>;
24		ranges;
25
26		/* 16 MiB reserved for Hardware ROM Firmware */
27		hwrom_reserved: hwrom@0 {
28			reg = <0x0 0x0 0x0 0x1000000>;
29			no-map;
30		};
31
32		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
33		secmon_reserved: secmon@10000000 {
34			reg = <0x0 0x10000000 0x0 0x200000>;
35			no-map;
36		};
37
38		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
39		secmon_reserved_alt: secmon@5000000 {
40			reg = <0x0 0x05000000 0x0 0x300000>;
41			no-map;
42		};
43
44		linux,cma {
45			compatible = "shared-dma-pool";
46			reusable;
47			size = <0x0 0xbc00000>;
48			alignment = <0x0 0x400000>;
49			linux,cma-default;
50		};
51	};
52
53	cpus {
54		#address-cells = <0x2>;
55		#size-cells = <0x0>;
56
57		cpu0: cpu@0 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a53", "arm,armv8";
60			reg = <0x0 0x0>;
61			enable-method = "psci";
62			next-level-cache = <&l2>;
63			clocks = <&scpi_dvfs 0>;
64		};
65
66		cpu1: cpu@1 {
67			device_type = "cpu";
68			compatible = "arm,cortex-a53", "arm,armv8";
69			reg = <0x0 0x1>;
70			enable-method = "psci";
71			next-level-cache = <&l2>;
72			clocks = <&scpi_dvfs 0>;
73		};
74
75		cpu2: cpu@2 {
76			device_type = "cpu";
77			compatible = "arm,cortex-a53", "arm,armv8";
78			reg = <0x0 0x2>;
79			enable-method = "psci";
80			next-level-cache = <&l2>;
81			clocks = <&scpi_dvfs 0>;
82		};
83
84		cpu3: cpu@3 {
85			device_type = "cpu";
86			compatible = "arm,cortex-a53", "arm,armv8";
87			reg = <0x0 0x3>;
88			enable-method = "psci";
89			next-level-cache = <&l2>;
90			clocks = <&scpi_dvfs 0>;
91		};
92
93		l2: l2-cache0 {
94			compatible = "cache";
95		};
96	};
97
98	arm-pmu {
99		compatible = "arm,cortex-a53-pmu";
100		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
101			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
102			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
103			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
104		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
105	};
106
107	psci {
108		compatible = "arm,psci-0.2";
109		method = "smc";
110	};
111
112	timer {
113		compatible = "arm,armv8-timer";
114		interrupts = <GIC_PPI 13
115			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
116			     <GIC_PPI 14
117			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
118			     <GIC_PPI 11
119			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
120			     <GIC_PPI 10
121			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
122	};
123
124	xtal: xtal-clk {
125		compatible = "fixed-clock";
126		clock-frequency = <24000000>;
127		clock-output-names = "xtal";
128		#clock-cells = <0>;
129	};
130
131	firmware {
132		sm: secure-monitor {
133			compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
134		};
135	};
136
137	efuse: efuse {
138		compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
139		#address-cells = <1>;
140		#size-cells = <1>;
141		read-only;
142
143		sn: sn@14 {
144			reg = <0x14 0x10>;
145		};
146
147		eth_mac: eth_mac@34 {
148			reg = <0x34 0x10>;
149		};
150
151		bid: bid@46 {
152			reg = <0x46 0x30>;
153		};
154	};
155
156	scpi {
157		compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
158		mboxes = <&mailbox 1 &mailbox 2>;
159		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
160
161		scpi_clocks: clocks {
162			compatible = "arm,scpi-clocks";
163
164			scpi_dvfs: scpi_clocks@0 {
165				compatible = "arm,scpi-dvfs-clocks";
166				#clock-cells = <1>;
167				clock-indices = <0>;
168				clock-output-names = "vcpu";
169			};
170		};
171
172		scpi_sensors: sensors {
173			compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
174			#thermal-sensor-cells = <1>;
175		};
176	};
177
178	soc {
179		compatible = "simple-bus";
180		#address-cells = <2>;
181		#size-cells = <2>;
182		ranges;
183
184		cbus: bus@c1100000 {
185			compatible = "simple-bus";
186			reg = <0x0 0xc1100000 0x0 0x100000>;
187			#address-cells = <2>;
188			#size-cells = <2>;
189			ranges = <0x0 0x0 0x0 0xc1100000 0x0 0x100000>;
190
191			gpio_intc: interrupt-controller@9880 {
192				compatible = "amlogic,meson-gpio-intc";
193				reg = <0x0 0x9880 0x0 0x10>;
194				interrupt-controller;
195				#interrupt-cells = <2>;
196				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
197				status = "disabled";
198			};
199
200			reset: reset-controller@4404 {
201				compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
202				reg = <0x0 0x04404 0x0 0x9c>;
203				#reset-cells = <1>;
204			};
205
206			uart_A: serial@84c0 {
207				compatible = "amlogic,meson-gx-uart";
208				reg = <0x0 0x84c0 0x0 0x18>;
209				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
210				status = "disabled";
211			};
212
213			uart_B: serial@84dc {
214				compatible = "amlogic,meson-gx-uart";
215				reg = <0x0 0x84dc 0x0 0x18>;
216				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
217				status = "disabled";
218			};
219
220			i2c_A: i2c@8500 {
221				compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
222				reg = <0x0 0x08500 0x0 0x20>;
223				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
224				#address-cells = <1>;
225				#size-cells = <0>;
226				status = "disabled";
227			};
228
229			pwm_ab: pwm@8550 {
230				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
231				reg = <0x0 0x08550 0x0 0x10>;
232				#pwm-cells = <3>;
233				status = "disabled";
234			};
235
236			pwm_cd: pwm@8650 {
237				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
238				reg = <0x0 0x08650 0x0 0x10>;
239				#pwm-cells = <3>;
240				status = "disabled";
241			};
242
243			saradc: adc@8680 {
244				compatible = "amlogic,meson-saradc";
245				reg = <0x0 0x8680 0x0 0x34>;
246				#io-channel-cells = <1>;
247				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
248				status = "disabled";
249			};
250
251			pwm_ef: pwm@86c0 {
252				compatible = "amlogic,meson-gx-pwm", "amlogic,meson-gxbb-pwm";
253				reg = <0x0 0x086c0 0x0 0x10>;
254				#pwm-cells = <3>;
255				status = "disabled";
256			};
257
258			uart_C: serial@8700 {
259				compatible = "amlogic,meson-gx-uart";
260				reg = <0x0 0x8700 0x0 0x18>;
261				interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
262				status = "disabled";
263			};
264
265			i2c_B: i2c@87c0 {
266				compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
267				reg = <0x0 0x087c0 0x0 0x20>;
268				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
269				#address-cells = <1>;
270				#size-cells = <0>;
271				status = "disabled";
272			};
273
274			i2c_C: i2c@87e0 {
275				compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
276				reg = <0x0 0x087e0 0x0 0x20>;
277				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
278				#address-cells = <1>;
279				#size-cells = <0>;
280				status = "disabled";
281			};
282
283			spicc: spi@8d80 {
284				compatible = "amlogic,meson-gx-spicc";
285				reg = <0x0 0x08d80 0x0 0x80>;
286				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
287				#address-cells = <1>;
288				#size-cells = <0>;
289				status = "disabled";
290			};
291
292			spifc: spi@8c80 {
293				compatible = "amlogic,meson-gx-spifc", "amlogic,meson-gxbb-spifc";
294				reg = <0x0 0x08c80 0x0 0x80>;
295				#address-cells = <1>;
296				#size-cells = <0>;
297				status = "disabled";
298			};
299
300			watchdog@98d0 {
301				compatible = "amlogic,meson-gx-wdt", "amlogic,meson-gxbb-wdt";
302				reg = <0x0 0x098d0 0x0 0x10>;
303				clocks = <&xtal>;
304			};
305		};
306
307		gic: interrupt-controller@c4301000 {
308			compatible = "arm,gic-400";
309			reg = <0x0 0xc4301000 0 0x1000>,
310			      <0x0 0xc4302000 0 0x2000>,
311			      <0x0 0xc4304000 0 0x2000>,
312			      <0x0 0xc4306000 0 0x2000>;
313			interrupt-controller;
314			interrupts = <GIC_PPI 9
315				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
316			#interrupt-cells = <3>;
317			#address-cells = <0>;
318		};
319
320		sram: sram@c8000000 {
321			compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
322			reg = <0x0 0xc8000000 0x0 0x14000>;
323
324			#address-cells = <1>;
325			#size-cells = <1>;
326			ranges = <0 0x0 0xc8000000 0x14000>;
327
328			cpu_scp_lpri: scp-shmem@0 {
329				compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
330				reg = <0x13000 0x400>;
331			};
332
333			cpu_scp_hpri: scp-shmem@200 {
334				compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
335				reg = <0x13400 0x400>;
336			};
337		};
338
339		aobus: bus@c8100000 {
340			compatible = "simple-bus";
341			reg = <0x0 0xc8100000 0x0 0x100000>;
342			#address-cells = <2>;
343			#size-cells = <2>;
344			ranges = <0x0 0x0 0x0 0xc8100000 0x0 0x100000>;
345
346			sysctrl_AO: sys-ctrl@0 {
347				compatible = "amlogic,meson-gx-ao-sysctrl", "syscon", "simple-mfd";
348				reg =  <0x0 0x0 0x0 0x100>;
349
350				pwrc_vpu: power-controller-vpu {
351					compatible = "amlogic,meson-gx-pwrc-vpu";
352					#power-domain-cells = <0>;
353					amlogic,hhi-sysctrl = <&sysctrl>;
354				};
355
356				clkc_AO: clock-controller {
357					compatible = "amlogic,meson-gx-aoclkc";
358					#clock-cells = <1>;
359					#reset-cells = <1>;
360				};
361			};
362
363			cec_AO: cec@100 {
364				compatible = "amlogic,meson-gx-ao-cec";
365				reg = <0x0 0x00100 0x0 0x14>;
366				interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>;
367			};
368
369			sec_AO: ao-secure@140 {
370				compatible = "amlogic,meson-gx-ao-secure", "syscon";
371				reg = <0x0 0x140 0x0 0x140>;
372				amlogic,has-chip-id;
373			};
374
375			uart_AO: serial@4c0 {
376				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
377				reg = <0x0 0x004c0 0x0 0x18>;
378				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
379				status = "disabled";
380			};
381
382			uart_AO_B: serial@4e0 {
383				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
384				reg = <0x0 0x004e0 0x0 0x18>;
385				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
386				status = "disabled";
387			};
388
389			i2c_AO: i2c@500 {
390				compatible = "amlogic,meson-gx-i2c", "amlogic,meson-gxbb-i2c";
391				reg = <0x0 0x500 0x0 0x20>;
392				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
393				#address-cells = <1>;
394				#size-cells = <0>;
395				status = "disabled";
396			};
397
398			pwm_AO_ab: pwm@550 {
399				compatible = "amlogic,meson-gx-ao-pwm", "amlogic,meson-gxbb-ao-pwm";
400				reg = <0x0 0x00550 0x0 0x10>;
401				#pwm-cells = <3>;
402				status = "disabled";
403			};
404
405			ir: ir@580 {
406				compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
407				reg = <0x0 0x00580 0x0 0x40>;
408				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
409				status = "disabled";
410			};
411		};
412
413		periphs: periphs@c8834000 {
414			compatible = "simple-bus";
415			reg = <0x0 0xc8834000 0x0 0x2000>;
416			#address-cells = <2>;
417			#size-cells = <2>;
418			ranges = <0x0 0x0 0x0 0xc8834000 0x0 0x2000>;
419
420			hwrng: rng {
421				compatible = "amlogic,meson-rng";
422				reg = <0x0 0x0 0x0 0x4>;
423			};
424		};
425
426		hiubus: bus@c883c000 {
427			compatible = "simple-bus";
428			reg = <0x0 0xc883c000 0x0 0x2000>;
429			#address-cells = <2>;
430			#size-cells = <2>;
431			ranges = <0x0 0x0 0x0 0xc883c000 0x0 0x2000>;
432
433			sysctrl: system-controller@0 {
434				compatible = "amlogic,meson-gx-hhi-sysctrl", "syscon", "simple-mfd";
435				reg = <0 0 0 0x400>;
436			};
437
438			mailbox: mailbox@404 {
439				compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
440				reg = <0 0x404 0 0x4c>;
441				interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
442					     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
443					     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
444				#mbox-cells = <1>;
445			};
446		};
447
448		ethmac: ethernet@c9410000 {
449			compatible = "amlogic,meson-gx-dwmac", "amlogic,meson-gxbb-dwmac", "snps,dwmac";
450			reg = <0x0 0xc9410000 0x0 0x10000
451			       0x0 0xc8834540 0x0 0x4>;
452			interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
453			interrupt-names = "macirq";
454			status = "disabled";
455		};
456
457		apb: apb@d0000000 {
458			compatible = "simple-bus";
459			reg = <0x0 0xd0000000 0x0 0x200000>;
460			#address-cells = <2>;
461			#size-cells = <2>;
462			ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
463
464			sd_emmc_a: mmc@70000 {
465				compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
466				reg = <0x0 0x70000 0x0 0x800>;
467				interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
468				status = "disabled";
469			};
470
471			sd_emmc_b: mmc@72000 {
472				compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
473				reg = <0x0 0x72000 0x0 0x800>;
474				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
475				status = "disabled";
476			};
477
478			sd_emmc_c: mmc@74000 {
479				compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
480				reg = <0x0 0x74000 0x0 0x800>;
481				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
482				status = "disabled";
483			};
484		};
485
486		vpu: vpu@d0100000 {
487			compatible = "amlogic,meson-gx-vpu";
488			reg = <0x0 0xd0100000 0x0 0x100000>,
489			      <0x0 0xc883c000 0x0 0x1000>,
490			      <0x0 0xc8838000 0x0 0x1000>;
491			reg-names = "vpu", "hhi", "dmc";
492			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
493			#address-cells = <1>;
494			#size-cells = <0>;
495
496			/* CVBS VDAC output port */
497			cvbs_vdac_port: port@0 {
498				reg = <0>;
499			};
500
501			/* HDMI-TX output port */
502			hdmi_tx_port: port@1 {
503				reg = <1>;
504
505				hdmi_tx_out: endpoint {
506					remote-endpoint = <&hdmi_tx_in>;
507				};
508			};
509		};
510
511		hdmi_tx: hdmi-tx@c883a000 {
512			compatible = "amlogic,meson-gx-dw-hdmi";
513			reg = <0x0 0xc883a000 0x0 0x1c>;
514			interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
515			#address-cells = <1>;
516			#size-cells = <0>;
517			status = "disabled";
518
519			/* VPU VENC Input */
520			hdmi_tx_venc_port: port@0 {
521				reg = <0>;
522
523				hdmi_tx_in: endpoint {
524					remote-endpoint = <&hdmi_tx_out>;
525				};
526			};
527
528			/* TMDS Output */
529			hdmi_tx_tmds_port: port@1 {
530				reg = <1>;
531			};
532		};
533	};
534};
535