1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { 21 #address-cells = <2>; 22 #size-cells = <2>; 23 ranges; 24 25 simplefb_cvbs: framebuffer-cvbs { 26 compatible = "amlogic,simple-framebuffer", 27 "simple-framebuffer"; 28 amlogic,pipeline = "vpu-cvbs"; 29 clocks = <&clkc CLKID_HDMI>, 30 <&clkc CLKID_HTX_PCLK>, 31 <&clkc CLKID_VPU_INTR>; 32 status = "disabled"; 33 }; 34 35 simplefb_hdmi: framebuffer-hdmi { 36 compatible = "amlogic,simple-framebuffer", 37 "simple-framebuffer"; 38 amlogic,pipeline = "vpu-hdmi"; 39 clocks = <&clkc CLKID_HDMI>, 40 <&clkc CLKID_HTX_PCLK>, 41 <&clkc CLKID_VPU_INTR>; 42 status = "disabled"; 43 }; 44 }; 45 46 efuse: efuse { 47 compatible = "amlogic,meson-gxbb-efuse"; 48 clocks = <&clkc CLKID_EFUSE>; 49 #address-cells = <1>; 50 #size-cells = <1>; 51 read-only; 52 secure-monitor = <&sm>; 53 }; 54 55 gpu_opp_table: gpu-opp-table { 56 compatible = "operating-points-v2"; 57 58 opp-124999998 { 59 opp-hz = /bits/ 64 <124999998>; 60 opp-microvolt = <800000>; 61 }; 62 opp-249999996 { 63 opp-hz = /bits/ 64 <249999996>; 64 opp-microvolt = <800000>; 65 }; 66 opp-285714281 { 67 opp-hz = /bits/ 64 <285714281>; 68 opp-microvolt = <800000>; 69 }; 70 opp-399999994 { 71 opp-hz = /bits/ 64 <399999994>; 72 opp-microvolt = <800000>; 73 }; 74 opp-499999992 { 75 opp-hz = /bits/ 64 <499999992>; 76 opp-microvolt = <800000>; 77 }; 78 opp-666666656 { 79 opp-hz = /bits/ 64 <666666656>; 80 opp-microvolt = <800000>; 81 }; 82 opp-799999987 { 83 opp-hz = /bits/ 64 <799999987>; 84 opp-microvolt = <800000>; 85 }; 86 }; 87 88 psci { 89 compatible = "arm,psci-1.0"; 90 method = "smc"; 91 }; 92 93 reserved-memory { 94 #address-cells = <2>; 95 #size-cells = <2>; 96 ranges; 97 98 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 99 secmon_reserved: secmon@5000000 { 100 reg = <0x0 0x05000000 0x0 0x300000>; 101 no-map; 102 }; 103 104 linux,cma { 105 compatible = "shared-dma-pool"; 106 reusable; 107 size = <0x0 0x10000000>; 108 alignment = <0x0 0x400000>; 109 linux,cma-default; 110 }; 111 }; 112 113 sm: secure-monitor { 114 compatible = "amlogic,meson-gxbb-sm"; 115 }; 116 117 soc { 118 compatible = "simple-bus"; 119 #address-cells = <2>; 120 #size-cells = <2>; 121 ranges; 122 123 pcie: pcie@fc000000 { 124 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 125 reg = <0x0 0xfc000000 0x0 0x400000 126 0x0 0xff648000 0x0 0x2000 127 0x0 0xfc400000 0x0 0x200000>; 128 reg-names = "elbi", "cfg", "config"; 129 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 130 #interrupt-cells = <1>; 131 interrupt-map-mask = <0 0 0 0>; 132 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 133 bus-range = <0x0 0xff>; 134 #address-cells = <3>; 135 #size-cells = <2>; 136 device_type = "pci"; 137 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000 138 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 139 140 clocks = <&clkc CLKID_PCIE_PHY 141 &clkc CLKID_PCIE_COMB 142 &clkc CLKID_PCIE_PLL>; 143 clock-names = "general", 144 "pclk", 145 "port"; 146 resets = <&reset RESET_PCIE_CTRL_A>, 147 <&reset RESET_PCIE_APB>; 148 reset-names = "port", 149 "apb"; 150 num-lanes = <1>; 151 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 152 phy-names = "pcie"; 153 status = "disabled"; 154 }; 155 156 thermal-zones { 157 cpu_thermal: cpu-thermal { 158 polling-delay = <1000>; 159 polling-delay-passive = <100>; 160 thermal-sensors = <&cpu_temp>; 161 162 trips { 163 cpu_passive: cpu-passive { 164 temperature = <85000>; /* millicelsius */ 165 hysteresis = <2000>; /* millicelsius */ 166 type = "passive"; 167 }; 168 169 cpu_hot: cpu-hot { 170 temperature = <95000>; /* millicelsius */ 171 hysteresis = <2000>; /* millicelsius */ 172 type = "hot"; 173 }; 174 175 cpu_critical: cpu-critical { 176 temperature = <110000>; /* millicelsius */ 177 hysteresis = <2000>; /* millicelsius */ 178 type = "critical"; 179 }; 180 }; 181 }; 182 183 ddr_thermal: ddr-thermal { 184 polling-delay = <1000>; 185 polling-delay-passive = <100>; 186 thermal-sensors = <&ddr_temp>; 187 188 trips { 189 ddr_passive: ddr-passive { 190 temperature = <85000>; /* millicelsius */ 191 hysteresis = <2000>; /* millicelsius */ 192 type = "passive"; 193 }; 194 195 ddr_critical: ddr-critical { 196 temperature = <110000>; /* millicelsius */ 197 hysteresis = <2000>; /* millicelsius */ 198 type = "critical"; 199 }; 200 }; 201 202 cooling-maps { 203 map { 204 trip = <&ddr_passive>; 205 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 206 }; 207 }; 208 }; 209 }; 210 211 ethmac: ethernet@ff3f0000 { 212 compatible = "amlogic,meson-g12a-dwmac", 213 "snps,dwmac-3.70a", 214 "snps,dwmac"; 215 reg = <0x0 0xff3f0000 0x0 0x10000>, 216 <0x0 0xff634540 0x0 0x8>; 217 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 218 interrupt-names = "macirq"; 219 clocks = <&clkc CLKID_ETH>, 220 <&clkc CLKID_FCLK_DIV2>, 221 <&clkc CLKID_MPLL2>, 222 <&clkc CLKID_FCLK_DIV2>; 223 clock-names = "stmmaceth", "clkin0", "clkin1", 224 "timing-adjustment"; 225 rx-fifo-depth = <4096>; 226 tx-fifo-depth = <2048>; 227 status = "disabled"; 228 229 mdio0: mdio { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 compatible = "snps,dwmac-mdio"; 233 }; 234 }; 235 236 apb: bus@ff600000 { 237 compatible = "simple-bus"; 238 reg = <0x0 0xff600000 0x0 0x200000>; 239 #address-cells = <2>; 240 #size-cells = <2>; 241 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 242 243 hdmi_tx: hdmi-tx@0 { 244 compatible = "amlogic,meson-g12a-dw-hdmi"; 245 reg = <0x0 0x0 0x0 0x10000>; 246 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 247 resets = <&reset RESET_HDMITX_CAPB3>, 248 <&reset RESET_HDMITX_PHY>, 249 <&reset RESET_HDMITX>; 250 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 251 clocks = <&clkc CLKID_HDMI>, 252 <&clkc CLKID_HTX_PCLK>, 253 <&clkc CLKID_VPU_INTR>; 254 clock-names = "isfr", "iahb", "venci"; 255 #address-cells = <1>; 256 #size-cells = <0>; 257 #sound-dai-cells = <0>; 258 status = "disabled"; 259 260 /* VPU VENC Input */ 261 hdmi_tx_venc_port: port@0 { 262 reg = <0>; 263 264 hdmi_tx_in: endpoint { 265 remote-endpoint = <&hdmi_tx_out>; 266 }; 267 }; 268 269 /* TMDS Output */ 270 hdmi_tx_tmds_port: port@1 { 271 reg = <1>; 272 }; 273 }; 274 275 apb_efuse: bus@30000 { 276 compatible = "simple-bus"; 277 reg = <0x0 0x30000 0x0 0x2000>; 278 #address-cells = <2>; 279 #size-cells = <2>; 280 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 281 282 hwrng: rng@218 { 283 compatible = "amlogic,meson-rng"; 284 reg = <0x0 0x218 0x0 0x4>; 285 clocks = <&clkc CLKID_RNG0>; 286 clock-names = "core"; 287 }; 288 }; 289 290 acodec: audio-controller@32000 { 291 compatible = "amlogic,t9015"; 292 reg = <0x0 0x32000 0x0 0x14>; 293 #sound-dai-cells = <0>; 294 sound-name-prefix = "ACODEC"; 295 clocks = <&clkc CLKID_AUDIO_CODEC>; 296 clock-names = "pclk"; 297 resets = <&reset RESET_AUDIO_CODEC>; 298 status = "disabled"; 299 }; 300 301 periphs: bus@34400 { 302 compatible = "simple-bus"; 303 reg = <0x0 0x34400 0x0 0x400>; 304 #address-cells = <2>; 305 #size-cells = <2>; 306 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 307 308 periphs_pinctrl: pinctrl@40 { 309 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 310 #address-cells = <2>; 311 #size-cells = <2>; 312 ranges; 313 314 gpio: bank@40 { 315 reg = <0x0 0x40 0x0 0x4c>, 316 <0x0 0xe8 0x0 0x18>, 317 <0x0 0x120 0x0 0x18>, 318 <0x0 0x2c0 0x0 0x40>, 319 <0x0 0x340 0x0 0x1c>; 320 reg-names = "gpio", 321 "pull", 322 "pull-enable", 323 "mux", 324 "ds"; 325 gpio-controller; 326 #gpio-cells = <2>; 327 gpio-ranges = <&periphs_pinctrl 0 0 86>; 328 }; 329 330 cec_ao_a_h_pins: cec_ao_a_h { 331 mux { 332 groups = "cec_ao_a_h"; 333 function = "cec_ao_a_h"; 334 bias-disable; 335 }; 336 }; 337 338 cec_ao_b_h_pins: cec_ao_b_h { 339 mux { 340 groups = "cec_ao_b_h"; 341 function = "cec_ao_b_h"; 342 bias-disable; 343 }; 344 }; 345 346 emmc_ctrl_pins: emmc-ctrl { 347 mux-0 { 348 groups = "emmc_cmd"; 349 function = "emmc"; 350 bias-pull-up; 351 drive-strength-microamp = <4000>; 352 }; 353 354 mux-1 { 355 groups = "emmc_clk"; 356 function = "emmc"; 357 bias-disable; 358 drive-strength-microamp = <4000>; 359 }; 360 }; 361 362 emmc_data_4b_pins: emmc-data-4b { 363 mux-0 { 364 groups = "emmc_nand_d0", 365 "emmc_nand_d1", 366 "emmc_nand_d2", 367 "emmc_nand_d3"; 368 function = "emmc"; 369 bias-pull-up; 370 drive-strength-microamp = <4000>; 371 }; 372 }; 373 374 emmc_data_8b_pins: emmc-data-8b { 375 mux-0 { 376 groups = "emmc_nand_d0", 377 "emmc_nand_d1", 378 "emmc_nand_d2", 379 "emmc_nand_d3", 380 "emmc_nand_d4", 381 "emmc_nand_d5", 382 "emmc_nand_d6", 383 "emmc_nand_d7"; 384 function = "emmc"; 385 bias-pull-up; 386 drive-strength-microamp = <4000>; 387 }; 388 }; 389 390 emmc_ds_pins: emmc-ds { 391 mux { 392 groups = "emmc_nand_ds"; 393 function = "emmc"; 394 bias-pull-down; 395 drive-strength-microamp = <4000>; 396 }; 397 }; 398 399 emmc_clk_gate_pins: emmc_clk_gate { 400 mux { 401 groups = "BOOT_8"; 402 function = "gpio_periphs"; 403 bias-pull-down; 404 drive-strength-microamp = <4000>; 405 }; 406 }; 407 408 hdmitx_ddc_pins: hdmitx_ddc { 409 mux { 410 groups = "hdmitx_sda", 411 "hdmitx_sck"; 412 function = "hdmitx"; 413 bias-disable; 414 drive-strength-microamp = <4000>; 415 }; 416 }; 417 418 hdmitx_hpd_pins: hdmitx_hpd { 419 mux { 420 groups = "hdmitx_hpd_in"; 421 function = "hdmitx"; 422 bias-disable; 423 }; 424 }; 425 426 427 i2c0_sda_c_pins: i2c0-sda-c { 428 mux { 429 groups = "i2c0_sda_c"; 430 function = "i2c0"; 431 bias-disable; 432 drive-strength-microamp = <3000>; 433 434 }; 435 }; 436 437 i2c0_sck_c_pins: i2c0-sck-c { 438 mux { 439 groups = "i2c0_sck_c"; 440 function = "i2c0"; 441 bias-disable; 442 drive-strength-microamp = <3000>; 443 }; 444 }; 445 446 i2c0_sda_z0_pins: i2c0-sda-z0 { 447 mux { 448 groups = "i2c0_sda_z0"; 449 function = "i2c0"; 450 bias-disable; 451 drive-strength-microamp = <3000>; 452 }; 453 }; 454 455 i2c0_sck_z1_pins: i2c0-sck-z1 { 456 mux { 457 groups = "i2c0_sck_z1"; 458 function = "i2c0"; 459 bias-disable; 460 drive-strength-microamp = <3000>; 461 }; 462 }; 463 464 i2c0_sda_z7_pins: i2c0-sda-z7 { 465 mux { 466 groups = "i2c0_sda_z7"; 467 function = "i2c0"; 468 bias-disable; 469 drive-strength-microamp = <3000>; 470 }; 471 }; 472 473 i2c0_sda_z8_pins: i2c0-sda-z8 { 474 mux { 475 groups = "i2c0_sda_z8"; 476 function = "i2c0"; 477 bias-disable; 478 drive-strength-microamp = <3000>; 479 }; 480 }; 481 482 i2c1_sda_x_pins: i2c1-sda-x { 483 mux { 484 groups = "i2c1_sda_x"; 485 function = "i2c1"; 486 bias-disable; 487 drive-strength-microamp = <3000>; 488 }; 489 }; 490 491 i2c1_sck_x_pins: i2c1-sck-x { 492 mux { 493 groups = "i2c1_sck_x"; 494 function = "i2c1"; 495 bias-disable; 496 drive-strength-microamp = <3000>; 497 }; 498 }; 499 500 i2c1_sda_h2_pins: i2c1-sda-h2 { 501 mux { 502 groups = "i2c1_sda_h2"; 503 function = "i2c1"; 504 bias-disable; 505 drive-strength-microamp = <3000>; 506 }; 507 }; 508 509 i2c1_sck_h3_pins: i2c1-sck-h3 { 510 mux { 511 groups = "i2c1_sck_h3"; 512 function = "i2c1"; 513 bias-disable; 514 drive-strength-microamp = <3000>; 515 }; 516 }; 517 518 i2c1_sda_h6_pins: i2c1-sda-h6 { 519 mux { 520 groups = "i2c1_sda_h6"; 521 function = "i2c1"; 522 bias-disable; 523 drive-strength-microamp = <3000>; 524 }; 525 }; 526 527 i2c1_sck_h7_pins: i2c1-sck-h7 { 528 mux { 529 groups = "i2c1_sck_h7"; 530 function = "i2c1"; 531 bias-disable; 532 drive-strength-microamp = <3000>; 533 }; 534 }; 535 536 i2c2_sda_x_pins: i2c2-sda-x { 537 mux { 538 groups = "i2c2_sda_x"; 539 function = "i2c2"; 540 bias-disable; 541 drive-strength-microamp = <3000>; 542 }; 543 }; 544 545 i2c2_sck_x_pins: i2c2-sck-x { 546 mux { 547 groups = "i2c2_sck_x"; 548 function = "i2c2"; 549 bias-disable; 550 drive-strength-microamp = <3000>; 551 }; 552 }; 553 554 i2c2_sda_z_pins: i2c2-sda-z { 555 mux { 556 groups = "i2c2_sda_z"; 557 function = "i2c2"; 558 bias-disable; 559 drive-strength-microamp = <3000>; 560 }; 561 }; 562 563 i2c2_sck_z_pins: i2c2-sck-z { 564 mux { 565 groups = "i2c2_sck_z"; 566 function = "i2c2"; 567 bias-disable; 568 drive-strength-microamp = <3000>; 569 }; 570 }; 571 572 i2c3_sda_h_pins: i2c3-sda-h { 573 mux { 574 groups = "i2c3_sda_h"; 575 function = "i2c3"; 576 bias-disable; 577 drive-strength-microamp = <3000>; 578 }; 579 }; 580 581 i2c3_sck_h_pins: i2c3-sck-h { 582 mux { 583 groups = "i2c3_sck_h"; 584 function = "i2c3"; 585 bias-disable; 586 drive-strength-microamp = <3000>; 587 }; 588 }; 589 590 i2c3_sda_a_pins: i2c3-sda-a { 591 mux { 592 groups = "i2c3_sda_a"; 593 function = "i2c3"; 594 bias-disable; 595 drive-strength-microamp = <3000>; 596 }; 597 }; 598 599 i2c3_sck_a_pins: i2c3-sck-a { 600 mux { 601 groups = "i2c3_sck_a"; 602 function = "i2c3"; 603 bias-disable; 604 drive-strength-microamp = <3000>; 605 }; 606 }; 607 608 mclk0_a_pins: mclk0-a { 609 mux { 610 groups = "mclk0_a"; 611 function = "mclk0"; 612 bias-disable; 613 drive-strength-microamp = <3000>; 614 }; 615 }; 616 617 mclk1_a_pins: mclk1-a { 618 mux { 619 groups = "mclk1_a"; 620 function = "mclk1"; 621 bias-disable; 622 drive-strength-microamp = <3000>; 623 }; 624 }; 625 626 mclk1_x_pins: mclk1-x { 627 mux { 628 groups = "mclk1_x"; 629 function = "mclk1"; 630 bias-disable; 631 drive-strength-microamp = <3000>; 632 }; 633 }; 634 635 mclk1_z_pins: mclk1-z { 636 mux { 637 groups = "mclk1_z"; 638 function = "mclk1"; 639 bias-disable; 640 drive-strength-microamp = <3000>; 641 }; 642 }; 643 644 nor_pins: nor { 645 mux { 646 groups = "nor_d", 647 "nor_q", 648 "nor_c", 649 "nor_cs"; 650 function = "nor"; 651 bias-disable; 652 }; 653 }; 654 655 pdm_din0_a_pins: pdm-din0-a { 656 mux { 657 groups = "pdm_din0_a"; 658 function = "pdm"; 659 bias-disable; 660 }; 661 }; 662 663 pdm_din0_c_pins: pdm-din0-c { 664 mux { 665 groups = "pdm_din0_c"; 666 function = "pdm"; 667 bias-disable; 668 }; 669 }; 670 671 pdm_din0_x_pins: pdm-din0-x { 672 mux { 673 groups = "pdm_din0_x"; 674 function = "pdm"; 675 bias-disable; 676 }; 677 }; 678 679 pdm_din0_z_pins: pdm-din0-z { 680 mux { 681 groups = "pdm_din0_z"; 682 function = "pdm"; 683 bias-disable; 684 }; 685 }; 686 687 pdm_din1_a_pins: pdm-din1-a { 688 mux { 689 groups = "pdm_din1_a"; 690 function = "pdm"; 691 bias-disable; 692 }; 693 }; 694 695 pdm_din1_c_pins: pdm-din1-c { 696 mux { 697 groups = "pdm_din1_c"; 698 function = "pdm"; 699 bias-disable; 700 }; 701 }; 702 703 pdm_din1_x_pins: pdm-din1-x { 704 mux { 705 groups = "pdm_din1_x"; 706 function = "pdm"; 707 bias-disable; 708 }; 709 }; 710 711 pdm_din1_z_pins: pdm-din1-z { 712 mux { 713 groups = "pdm_din1_z"; 714 function = "pdm"; 715 bias-disable; 716 }; 717 }; 718 719 pdm_din2_a_pins: pdm-din2-a { 720 mux { 721 groups = "pdm_din2_a"; 722 function = "pdm"; 723 bias-disable; 724 }; 725 }; 726 727 pdm_din2_c_pins: pdm-din2-c { 728 mux { 729 groups = "pdm_din2_c"; 730 function = "pdm"; 731 bias-disable; 732 }; 733 }; 734 735 pdm_din2_x_pins: pdm-din2-x { 736 mux { 737 groups = "pdm_din2_x"; 738 function = "pdm"; 739 bias-disable; 740 }; 741 }; 742 743 pdm_din2_z_pins: pdm-din2-z { 744 mux { 745 groups = "pdm_din2_z"; 746 function = "pdm"; 747 bias-disable; 748 }; 749 }; 750 751 pdm_din3_a_pins: pdm-din3-a { 752 mux { 753 groups = "pdm_din3_a"; 754 function = "pdm"; 755 bias-disable; 756 }; 757 }; 758 759 pdm_din3_c_pins: pdm-din3-c { 760 mux { 761 groups = "pdm_din3_c"; 762 function = "pdm"; 763 bias-disable; 764 }; 765 }; 766 767 pdm_din3_x_pins: pdm-din3-x { 768 mux { 769 groups = "pdm_din3_x"; 770 function = "pdm"; 771 bias-disable; 772 }; 773 }; 774 775 pdm_din3_z_pins: pdm-din3-z { 776 mux { 777 groups = "pdm_din3_z"; 778 function = "pdm"; 779 bias-disable; 780 }; 781 }; 782 783 pdm_dclk_a_pins: pdm-dclk-a { 784 mux { 785 groups = "pdm_dclk_a"; 786 function = "pdm"; 787 bias-disable; 788 drive-strength-microamp = <500>; 789 }; 790 }; 791 792 pdm_dclk_c_pins: pdm-dclk-c { 793 mux { 794 groups = "pdm_dclk_c"; 795 function = "pdm"; 796 bias-disable; 797 drive-strength-microamp = <500>; 798 }; 799 }; 800 801 pdm_dclk_x_pins: pdm-dclk-x { 802 mux { 803 groups = "pdm_dclk_x"; 804 function = "pdm"; 805 bias-disable; 806 drive-strength-microamp = <500>; 807 }; 808 }; 809 810 pdm_dclk_z_pins: pdm-dclk-z { 811 mux { 812 groups = "pdm_dclk_z"; 813 function = "pdm"; 814 bias-disable; 815 drive-strength-microamp = <500>; 816 }; 817 }; 818 819 pwm_a_pins: pwm-a { 820 mux { 821 groups = "pwm_a"; 822 function = "pwm_a"; 823 bias-disable; 824 }; 825 }; 826 827 pwm_b_x7_pins: pwm-b-x7 { 828 mux { 829 groups = "pwm_b_x7"; 830 function = "pwm_b"; 831 bias-disable; 832 }; 833 }; 834 835 pwm_b_x19_pins: pwm-b-x19 { 836 mux { 837 groups = "pwm_b_x19"; 838 function = "pwm_b"; 839 bias-disable; 840 }; 841 }; 842 843 pwm_c_c_pins: pwm-c-c { 844 mux { 845 groups = "pwm_c_c"; 846 function = "pwm_c"; 847 bias-disable; 848 }; 849 }; 850 851 pwm_c_x5_pins: pwm-c-x5 { 852 mux { 853 groups = "pwm_c_x5"; 854 function = "pwm_c"; 855 bias-disable; 856 }; 857 }; 858 859 pwm_c_x8_pins: pwm-c-x8 { 860 mux { 861 groups = "pwm_c_x8"; 862 function = "pwm_c"; 863 bias-disable; 864 }; 865 }; 866 867 pwm_d_x3_pins: pwm-d-x3 { 868 mux { 869 groups = "pwm_d_x3"; 870 function = "pwm_d"; 871 bias-disable; 872 }; 873 }; 874 875 pwm_d_x6_pins: pwm-d-x6 { 876 mux { 877 groups = "pwm_d_x6"; 878 function = "pwm_d"; 879 bias-disable; 880 }; 881 }; 882 883 pwm_e_pins: pwm-e { 884 mux { 885 groups = "pwm_e"; 886 function = "pwm_e"; 887 bias-disable; 888 }; 889 }; 890 891 pwm_f_x_pins: pwm-f-x { 892 mux { 893 groups = "pwm_f_x"; 894 function = "pwm_f"; 895 bias-disable; 896 }; 897 }; 898 899 pwm_f_h_pins: pwm-f-h { 900 mux { 901 groups = "pwm_f_h"; 902 function = "pwm_f"; 903 bias-disable; 904 }; 905 }; 906 907 sdcard_c_pins: sdcard_c { 908 mux-0 { 909 groups = "sdcard_d0_c", 910 "sdcard_d1_c", 911 "sdcard_d2_c", 912 "sdcard_d3_c", 913 "sdcard_cmd_c"; 914 function = "sdcard"; 915 bias-pull-up; 916 drive-strength-microamp = <4000>; 917 }; 918 919 mux-1 { 920 groups = "sdcard_clk_c"; 921 function = "sdcard"; 922 bias-disable; 923 drive-strength-microamp = <4000>; 924 }; 925 }; 926 927 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 928 mux { 929 groups = "GPIOC_4"; 930 function = "gpio_periphs"; 931 bias-pull-down; 932 drive-strength-microamp = <4000>; 933 }; 934 }; 935 936 sdcard_z_pins: sdcard_z { 937 mux-0 { 938 groups = "sdcard_d0_z", 939 "sdcard_d1_z", 940 "sdcard_d2_z", 941 "sdcard_d3_z", 942 "sdcard_cmd_z"; 943 function = "sdcard"; 944 bias-pull-up; 945 drive-strength-microamp = <4000>; 946 }; 947 948 mux-1 { 949 groups = "sdcard_clk_z"; 950 function = "sdcard"; 951 bias-disable; 952 drive-strength-microamp = <4000>; 953 }; 954 }; 955 956 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 957 mux { 958 groups = "GPIOZ_6"; 959 function = "gpio_periphs"; 960 bias-pull-down; 961 drive-strength-microamp = <4000>; 962 }; 963 }; 964 965 sdio_pins: sdio { 966 mux { 967 groups = "sdio_d0", 968 "sdio_d1", 969 "sdio_d2", 970 "sdio_d3", 971 "sdio_clk", 972 "sdio_cmd"; 973 function = "sdio"; 974 bias-disable; 975 drive-strength-microamp = <4000>; 976 }; 977 }; 978 979 sdio_clk_gate_pins: sdio_clk_gate { 980 mux { 981 groups = "GPIOX_4"; 982 function = "gpio_periphs"; 983 bias-pull-down; 984 drive-strength-microamp = <4000>; 985 }; 986 }; 987 988 spdif_in_a10_pins: spdif-in-a10 { 989 mux { 990 groups = "spdif_in_a10"; 991 function = "spdif_in"; 992 bias-disable; 993 }; 994 }; 995 996 spdif_in_a12_pins: spdif-in-a12 { 997 mux { 998 groups = "spdif_in_a12"; 999 function = "spdif_in"; 1000 bias-disable; 1001 }; 1002 }; 1003 1004 spdif_in_h_pins: spdif-in-h { 1005 mux { 1006 groups = "spdif_in_h"; 1007 function = "spdif_in"; 1008 bias-disable; 1009 }; 1010 }; 1011 1012 spdif_out_h_pins: spdif-out-h { 1013 mux { 1014 groups = "spdif_out_h"; 1015 function = "spdif_out"; 1016 drive-strength-microamp = <500>; 1017 bias-disable; 1018 }; 1019 }; 1020 1021 spdif_out_a11_pins: spdif-out-a11 { 1022 mux { 1023 groups = "spdif_out_a11"; 1024 function = "spdif_out"; 1025 drive-strength-microamp = <500>; 1026 bias-disable; 1027 }; 1028 }; 1029 1030 spdif_out_a13_pins: spdif-out-a13 { 1031 mux { 1032 groups = "spdif_out_a13"; 1033 function = "spdif_out"; 1034 drive-strength-microamp = <500>; 1035 bias-disable; 1036 }; 1037 }; 1038 1039 spicc0_x_pins: spicc0-x { 1040 mux { 1041 groups = "spi0_mosi_x", 1042 "spi0_miso_x", 1043 "spi0_clk_x"; 1044 function = "spi0"; 1045 drive-strength-microamp = <4000>; 1046 bias-disable; 1047 }; 1048 }; 1049 1050 spicc0_ss0_x_pins: spicc0-ss0-x { 1051 mux { 1052 groups = "spi0_ss0_x"; 1053 function = "spi0"; 1054 drive-strength-microamp = <4000>; 1055 bias-disable; 1056 }; 1057 }; 1058 1059 spicc0_c_pins: spicc0-c { 1060 mux { 1061 groups = "spi0_mosi_c", 1062 "spi0_miso_c", 1063 "spi0_ss0_c", 1064 "spi0_clk_c"; 1065 function = "spi0"; 1066 drive-strength-microamp = <4000>; 1067 bias-disable; 1068 }; 1069 }; 1070 1071 spicc1_pins: spicc1 { 1072 mux { 1073 groups = "spi1_mosi", 1074 "spi1_miso", 1075 "spi1_clk"; 1076 function = "spi1"; 1077 drive-strength-microamp = <4000>; 1078 }; 1079 }; 1080 1081 spicc1_ss0_pins: spicc1-ss0 { 1082 mux { 1083 groups = "spi1_ss0"; 1084 function = "spi1"; 1085 drive-strength-microamp = <4000>; 1086 bias-disable; 1087 }; 1088 }; 1089 1090 tdm_a_din0_pins: tdm-a-din0 { 1091 mux { 1092 groups = "tdm_a_din0"; 1093 function = "tdm_a"; 1094 bias-disable; 1095 }; 1096 }; 1097 1098 1099 tdm_a_din1_pins: tdm-a-din1 { 1100 mux { 1101 groups = "tdm_a_din1"; 1102 function = "tdm_a"; 1103 bias-disable; 1104 }; 1105 }; 1106 1107 tdm_a_dout0_pins: tdm-a-dout0 { 1108 mux { 1109 groups = "tdm_a_dout0"; 1110 function = "tdm_a"; 1111 bias-disable; 1112 drive-strength-microamp = <3000>; 1113 }; 1114 }; 1115 1116 tdm_a_dout1_pins: tdm-a-dout1 { 1117 mux { 1118 groups = "tdm_a_dout1"; 1119 function = "tdm_a"; 1120 bias-disable; 1121 drive-strength-microamp = <3000>; 1122 }; 1123 }; 1124 1125 tdm_a_fs_pins: tdm-a-fs { 1126 mux { 1127 groups = "tdm_a_fs"; 1128 function = "tdm_a"; 1129 bias-disable; 1130 drive-strength-microamp = <3000>; 1131 }; 1132 }; 1133 1134 tdm_a_sclk_pins: tdm-a-sclk { 1135 mux { 1136 groups = "tdm_a_sclk"; 1137 function = "tdm_a"; 1138 bias-disable; 1139 drive-strength-microamp = <3000>; 1140 }; 1141 }; 1142 1143 tdm_a_slv_fs_pins: tdm-a-slv-fs { 1144 mux { 1145 groups = "tdm_a_slv_fs"; 1146 function = "tdm_a"; 1147 bias-disable; 1148 }; 1149 }; 1150 1151 1152 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 1153 mux { 1154 groups = "tdm_a_slv_sclk"; 1155 function = "tdm_a"; 1156 bias-disable; 1157 }; 1158 }; 1159 1160 tdm_b_din0_pins: tdm-b-din0 { 1161 mux { 1162 groups = "tdm_b_din0"; 1163 function = "tdm_b"; 1164 bias-disable; 1165 }; 1166 }; 1167 1168 tdm_b_din1_pins: tdm-b-din1 { 1169 mux { 1170 groups = "tdm_b_din1"; 1171 function = "tdm_b"; 1172 bias-disable; 1173 }; 1174 }; 1175 1176 tdm_b_din2_pins: tdm-b-din2 { 1177 mux { 1178 groups = "tdm_b_din2"; 1179 function = "tdm_b"; 1180 bias-disable; 1181 }; 1182 }; 1183 1184 tdm_b_din3_a_pins: tdm-b-din3-a { 1185 mux { 1186 groups = "tdm_b_din3_a"; 1187 function = "tdm_b"; 1188 bias-disable; 1189 }; 1190 }; 1191 1192 tdm_b_din3_h_pins: tdm-b-din3-h { 1193 mux { 1194 groups = "tdm_b_din3_h"; 1195 function = "tdm_b"; 1196 bias-disable; 1197 }; 1198 }; 1199 1200 tdm_b_dout0_pins: tdm-b-dout0 { 1201 mux { 1202 groups = "tdm_b_dout0"; 1203 function = "tdm_b"; 1204 bias-disable; 1205 drive-strength-microamp = <3000>; 1206 }; 1207 }; 1208 1209 tdm_b_dout1_pins: tdm-b-dout1 { 1210 mux { 1211 groups = "tdm_b_dout1"; 1212 function = "tdm_b"; 1213 bias-disable; 1214 drive-strength-microamp = <3000>; 1215 }; 1216 }; 1217 1218 tdm_b_dout2_pins: tdm-b-dout2 { 1219 mux { 1220 groups = "tdm_b_dout2"; 1221 function = "tdm_b"; 1222 bias-disable; 1223 drive-strength-microamp = <3000>; 1224 }; 1225 }; 1226 1227 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1228 mux { 1229 groups = "tdm_b_dout3_a"; 1230 function = "tdm_b"; 1231 bias-disable; 1232 drive-strength-microamp = <3000>; 1233 }; 1234 }; 1235 1236 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1237 mux { 1238 groups = "tdm_b_dout3_h"; 1239 function = "tdm_b"; 1240 bias-disable; 1241 drive-strength-microamp = <3000>; 1242 }; 1243 }; 1244 1245 tdm_b_fs_pins: tdm-b-fs { 1246 mux { 1247 groups = "tdm_b_fs"; 1248 function = "tdm_b"; 1249 bias-disable; 1250 drive-strength-microamp = <3000>; 1251 }; 1252 }; 1253 1254 tdm_b_sclk_pins: tdm-b-sclk { 1255 mux { 1256 groups = "tdm_b_sclk"; 1257 function = "tdm_b"; 1258 bias-disable; 1259 drive-strength-microamp = <3000>; 1260 }; 1261 }; 1262 1263 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1264 mux { 1265 groups = "tdm_b_slv_fs"; 1266 function = "tdm_b"; 1267 bias-disable; 1268 }; 1269 }; 1270 1271 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1272 mux { 1273 groups = "tdm_b_slv_sclk"; 1274 function = "tdm_b"; 1275 bias-disable; 1276 }; 1277 }; 1278 1279 tdm_c_din0_a_pins: tdm-c-din0-a { 1280 mux { 1281 groups = "tdm_c_din0_a"; 1282 function = "tdm_c"; 1283 bias-disable; 1284 }; 1285 }; 1286 1287 tdm_c_din0_z_pins: tdm-c-din0-z { 1288 mux { 1289 groups = "tdm_c_din0_z"; 1290 function = "tdm_c"; 1291 bias-disable; 1292 }; 1293 }; 1294 1295 tdm_c_din1_a_pins: tdm-c-din1-a { 1296 mux { 1297 groups = "tdm_c_din1_a"; 1298 function = "tdm_c"; 1299 bias-disable; 1300 }; 1301 }; 1302 1303 tdm_c_din1_z_pins: tdm-c-din1-z { 1304 mux { 1305 groups = "tdm_c_din1_z"; 1306 function = "tdm_c"; 1307 bias-disable; 1308 }; 1309 }; 1310 1311 tdm_c_din2_a_pins: tdm-c-din2-a { 1312 mux { 1313 groups = "tdm_c_din2_a"; 1314 function = "tdm_c"; 1315 bias-disable; 1316 }; 1317 }; 1318 1319 eth_leds_pins: eth-leds { 1320 mux { 1321 groups = "eth_link_led", 1322 "eth_act_led"; 1323 function = "eth"; 1324 bias-disable; 1325 }; 1326 }; 1327 1328 eth_pins: eth { 1329 mux { 1330 groups = "eth_mdio", 1331 "eth_mdc", 1332 "eth_rgmii_rx_clk", 1333 "eth_rx_dv", 1334 "eth_rxd0", 1335 "eth_rxd1", 1336 "eth_txen", 1337 "eth_txd0", 1338 "eth_txd1"; 1339 function = "eth"; 1340 drive-strength-microamp = <4000>; 1341 bias-disable; 1342 }; 1343 }; 1344 1345 eth_rgmii_pins: eth-rgmii { 1346 mux { 1347 groups = "eth_rxd2_rgmii", 1348 "eth_rxd3_rgmii", 1349 "eth_rgmii_tx_clk", 1350 "eth_txd2_rgmii", 1351 "eth_txd3_rgmii"; 1352 function = "eth"; 1353 drive-strength-microamp = <4000>; 1354 bias-disable; 1355 }; 1356 }; 1357 1358 tdm_c_din2_z_pins: tdm-c-din2-z { 1359 mux { 1360 groups = "tdm_c_din2_z"; 1361 function = "tdm_c"; 1362 bias-disable; 1363 }; 1364 }; 1365 1366 tdm_c_din3_a_pins: tdm-c-din3-a { 1367 mux { 1368 groups = "tdm_c_din3_a"; 1369 function = "tdm_c"; 1370 bias-disable; 1371 }; 1372 }; 1373 1374 tdm_c_din3_z_pins: tdm-c-din3-z { 1375 mux { 1376 groups = "tdm_c_din3_z"; 1377 function = "tdm_c"; 1378 bias-disable; 1379 }; 1380 }; 1381 1382 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1383 mux { 1384 groups = "tdm_c_dout0_a"; 1385 function = "tdm_c"; 1386 bias-disable; 1387 drive-strength-microamp = <3000>; 1388 }; 1389 }; 1390 1391 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1392 mux { 1393 groups = "tdm_c_dout0_z"; 1394 function = "tdm_c"; 1395 bias-disable; 1396 drive-strength-microamp = <3000>; 1397 }; 1398 }; 1399 1400 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1401 mux { 1402 groups = "tdm_c_dout1_a"; 1403 function = "tdm_c"; 1404 bias-disable; 1405 drive-strength-microamp = <3000>; 1406 }; 1407 }; 1408 1409 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1410 mux { 1411 groups = "tdm_c_dout1_z"; 1412 function = "tdm_c"; 1413 bias-disable; 1414 drive-strength-microamp = <3000>; 1415 }; 1416 }; 1417 1418 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1419 mux { 1420 groups = "tdm_c_dout2_a"; 1421 function = "tdm_c"; 1422 bias-disable; 1423 drive-strength-microamp = <3000>; 1424 }; 1425 }; 1426 1427 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1428 mux { 1429 groups = "tdm_c_dout2_z"; 1430 function = "tdm_c"; 1431 bias-disable; 1432 drive-strength-microamp = <3000>; 1433 }; 1434 }; 1435 1436 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1437 mux { 1438 groups = "tdm_c_dout3_a"; 1439 function = "tdm_c"; 1440 bias-disable; 1441 drive-strength-microamp = <3000>; 1442 }; 1443 }; 1444 1445 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1446 mux { 1447 groups = "tdm_c_dout3_z"; 1448 function = "tdm_c"; 1449 bias-disable; 1450 drive-strength-microamp = <3000>; 1451 }; 1452 }; 1453 1454 tdm_c_fs_a_pins: tdm-c-fs-a { 1455 mux { 1456 groups = "tdm_c_fs_a"; 1457 function = "tdm_c"; 1458 bias-disable; 1459 drive-strength-microamp = <3000>; 1460 }; 1461 }; 1462 1463 tdm_c_fs_z_pins: tdm-c-fs-z { 1464 mux { 1465 groups = "tdm_c_fs_z"; 1466 function = "tdm_c"; 1467 bias-disable; 1468 drive-strength-microamp = <3000>; 1469 }; 1470 }; 1471 1472 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1473 mux { 1474 groups = "tdm_c_sclk_a"; 1475 function = "tdm_c"; 1476 bias-disable; 1477 drive-strength-microamp = <3000>; 1478 }; 1479 }; 1480 1481 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1482 mux { 1483 groups = "tdm_c_sclk_z"; 1484 function = "tdm_c"; 1485 bias-disable; 1486 drive-strength-microamp = <3000>; 1487 }; 1488 }; 1489 1490 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1491 mux { 1492 groups = "tdm_c_slv_fs_a"; 1493 function = "tdm_c"; 1494 bias-disable; 1495 }; 1496 }; 1497 1498 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1499 mux { 1500 groups = "tdm_c_slv_fs_z"; 1501 function = "tdm_c"; 1502 bias-disable; 1503 }; 1504 }; 1505 1506 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1507 mux { 1508 groups = "tdm_c_slv_sclk_a"; 1509 function = "tdm_c"; 1510 bias-disable; 1511 }; 1512 }; 1513 1514 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1515 mux { 1516 groups = "tdm_c_slv_sclk_z"; 1517 function = "tdm_c"; 1518 bias-disable; 1519 }; 1520 }; 1521 1522 uart_a_pins: uart-a { 1523 mux { 1524 groups = "uart_a_tx", 1525 "uart_a_rx"; 1526 function = "uart_a"; 1527 bias-disable; 1528 }; 1529 }; 1530 1531 uart_a_cts_rts_pins: uart-a-cts-rts { 1532 mux { 1533 groups = "uart_a_cts", 1534 "uart_a_rts"; 1535 function = "uart_a"; 1536 bias-disable; 1537 }; 1538 }; 1539 1540 uart_b_pins: uart-b { 1541 mux { 1542 groups = "uart_b_tx", 1543 "uart_b_rx"; 1544 function = "uart_b"; 1545 bias-disable; 1546 }; 1547 }; 1548 1549 uart_c_pins: uart-c { 1550 mux { 1551 groups = "uart_c_tx", 1552 "uart_c_rx"; 1553 function = "uart_c"; 1554 bias-disable; 1555 }; 1556 }; 1557 1558 uart_c_cts_rts_pins: uart-c-cts-rts { 1559 mux { 1560 groups = "uart_c_cts", 1561 "uart_c_rts"; 1562 function = "uart_c"; 1563 bias-disable; 1564 }; 1565 }; 1566 }; 1567 }; 1568 1569 cpu_temp: temperature-sensor@34800 { 1570 compatible = "amlogic,g12a-cpu-thermal", 1571 "amlogic,g12a-thermal"; 1572 reg = <0x0 0x34800 0x0 0x50>; 1573 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 1574 clocks = <&clkc CLKID_TS>; 1575 #thermal-sensor-cells = <0>; 1576 amlogic,ao-secure = <&sec_AO>; 1577 }; 1578 1579 ddr_temp: temperature-sensor@34c00 { 1580 compatible = "amlogic,g12a-ddr-thermal", 1581 "amlogic,g12a-thermal"; 1582 reg = <0x0 0x34c00 0x0 0x50>; 1583 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; 1584 clocks = <&clkc CLKID_TS>; 1585 #thermal-sensor-cells = <0>; 1586 amlogic,ao-secure = <&sec_AO>; 1587 }; 1588 1589 usb2_phy0: phy@36000 { 1590 compatible = "amlogic,g12a-usb2-phy"; 1591 reg = <0x0 0x36000 0x0 0x2000>; 1592 clocks = <&xtal>; 1593 clock-names = "xtal"; 1594 resets = <&reset RESET_USB_PHY20>; 1595 reset-names = "phy"; 1596 #phy-cells = <0>; 1597 }; 1598 1599 dmc: bus@38000 { 1600 compatible = "simple-bus"; 1601 reg = <0x0 0x38000 0x0 0x400>; 1602 #address-cells = <2>; 1603 #size-cells = <2>; 1604 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1605 1606 canvas: video-lut@48 { 1607 compatible = "amlogic,canvas"; 1608 reg = <0x0 0x48 0x0 0x14>; 1609 }; 1610 }; 1611 1612 usb2_phy1: phy@3a000 { 1613 compatible = "amlogic,g12a-usb2-phy"; 1614 reg = <0x0 0x3a000 0x0 0x2000>; 1615 clocks = <&xtal>; 1616 clock-names = "xtal"; 1617 resets = <&reset RESET_USB_PHY21>; 1618 reset-names = "phy"; 1619 #phy-cells = <0>; 1620 }; 1621 1622 hiu: bus@3c000 { 1623 compatible = "simple-bus"; 1624 reg = <0x0 0x3c000 0x0 0x1400>; 1625 #address-cells = <2>; 1626 #size-cells = <2>; 1627 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1628 1629 hhi: system-controller@0 { 1630 compatible = "amlogic,meson-gx-hhi-sysctrl", 1631 "simple-mfd", "syscon"; 1632 reg = <0 0 0 0x400>; 1633 1634 clkc: clock-controller { 1635 compatible = "amlogic,g12a-clkc"; 1636 #clock-cells = <1>; 1637 clocks = <&xtal>; 1638 clock-names = "xtal"; 1639 }; 1640 1641 pwrc: power-controller { 1642 compatible = "amlogic,meson-g12a-pwrc"; 1643 #power-domain-cells = <1>; 1644 amlogic,ao-sysctrl = <&rti>; 1645 resets = <&reset RESET_VIU>, 1646 <&reset RESET_VENC>, 1647 <&reset RESET_VCBUS>, 1648 <&reset RESET_BT656>, 1649 <&reset RESET_RDMA>, 1650 <&reset RESET_VENCI>, 1651 <&reset RESET_VENCP>, 1652 <&reset RESET_VDAC>, 1653 <&reset RESET_VDI6>, 1654 <&reset RESET_VENCL>, 1655 <&reset RESET_VID_LOCK>; 1656 reset-names = "viu", "venc", "vcbus", "bt656", 1657 "rdma", "venci", "vencp", "vdac", 1658 "vdi6", "vencl", "vid_lock"; 1659 clocks = <&clkc CLKID_VPU>, 1660 <&clkc CLKID_VAPB>; 1661 clock-names = "vpu", "vapb"; 1662 /* 1663 * VPU clocking is provided by two identical clock paths 1664 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1665 * free mux to safely change frequency while running. 1666 * Same for VAPB but with a final gate after the glitch free mux. 1667 */ 1668 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1669 <&clkc CLKID_VPU_0>, 1670 <&clkc CLKID_VPU>, /* Glitch free mux */ 1671 <&clkc CLKID_VAPB_0_SEL>, 1672 <&clkc CLKID_VAPB_0>, 1673 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1674 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1675 <0>, /* Do Nothing */ 1676 <&clkc CLKID_VPU_0>, 1677 <&clkc CLKID_FCLK_DIV4>, 1678 <0>, /* Do Nothing */ 1679 <&clkc CLKID_VAPB_0>; 1680 assigned-clock-rates = <0>, /* Do Nothing */ 1681 <666666666>, 1682 <0>, /* Do Nothing */ 1683 <0>, /* Do Nothing */ 1684 <250000000>, 1685 <0>; /* Do Nothing */ 1686 }; 1687 }; 1688 }; 1689 1690 usb3_pcie_phy: phy@46000 { 1691 compatible = "amlogic,g12a-usb3-pcie-phy"; 1692 reg = <0x0 0x46000 0x0 0x2000>; 1693 clocks = <&clkc CLKID_PCIE_PLL>; 1694 clock-names = "ref_clk"; 1695 resets = <&reset RESET_PCIE_PHY>; 1696 reset-names = "phy"; 1697 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1698 assigned-clock-rates = <100000000>; 1699 #phy-cells = <1>; 1700 }; 1701 1702 eth_phy: mdio-multiplexer@4c000 { 1703 compatible = "amlogic,g12a-mdio-mux"; 1704 reg = <0x0 0x4c000 0x0 0xa4>; 1705 clocks = <&clkc CLKID_ETH_PHY>, 1706 <&xtal>, 1707 <&clkc CLKID_MPLL_50M>; 1708 clock-names = "pclk", "clkin0", "clkin1"; 1709 mdio-parent-bus = <&mdio0>; 1710 #address-cells = <1>; 1711 #size-cells = <0>; 1712 1713 ext_mdio: mdio@0 { 1714 reg = <0>; 1715 #address-cells = <1>; 1716 #size-cells = <0>; 1717 }; 1718 1719 int_mdio: mdio@1 { 1720 reg = <1>; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 1724 internal_ephy: ethernet_phy@8 { 1725 compatible = "ethernet-phy-id0180.3301", 1726 "ethernet-phy-ieee802.3-c22"; 1727 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1728 reg = <8>; 1729 max-speed = <100>; 1730 }; 1731 }; 1732 }; 1733 }; 1734 1735 aobus: bus@ff800000 { 1736 compatible = "simple-bus"; 1737 reg = <0x0 0xff800000 0x0 0x100000>; 1738 #address-cells = <2>; 1739 #size-cells = <2>; 1740 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1741 1742 rti: sys-ctrl@0 { 1743 compatible = "amlogic,meson-gx-ao-sysctrl", 1744 "simple-mfd", "syscon"; 1745 reg = <0x0 0x0 0x0 0x100>; 1746 #address-cells = <2>; 1747 #size-cells = <2>; 1748 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1749 1750 clkc_AO: clock-controller { 1751 compatible = "amlogic,meson-g12a-aoclkc"; 1752 #clock-cells = <1>; 1753 #reset-cells = <1>; 1754 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1755 clock-names = "xtal", "mpeg-clk"; 1756 }; 1757 1758 ao_pinctrl: pinctrl@14 { 1759 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1760 #address-cells = <2>; 1761 #size-cells = <2>; 1762 ranges; 1763 1764 gpio_ao: bank@14 { 1765 reg = <0x0 0x14 0x0 0x8>, 1766 <0x0 0x1c 0x0 0x8>, 1767 <0x0 0x24 0x0 0x14>; 1768 reg-names = "mux", 1769 "ds", 1770 "gpio"; 1771 gpio-controller; 1772 #gpio-cells = <2>; 1773 gpio-ranges = <&ao_pinctrl 0 0 15>; 1774 }; 1775 1776 i2c_ao_sck_pins: i2c_ao_sck_pins { 1777 mux { 1778 groups = "i2c_ao_sck"; 1779 function = "i2c_ao"; 1780 bias-disable; 1781 drive-strength-microamp = <3000>; 1782 }; 1783 }; 1784 1785 i2c_ao_sda_pins: i2c_ao_sda { 1786 mux { 1787 groups = "i2c_ao_sda"; 1788 function = "i2c_ao"; 1789 bias-disable; 1790 drive-strength-microamp = <3000>; 1791 }; 1792 }; 1793 1794 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1795 mux { 1796 groups = "i2c_ao_sck_e"; 1797 function = "i2c_ao"; 1798 bias-disable; 1799 drive-strength-microamp = <3000>; 1800 }; 1801 }; 1802 1803 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1804 mux { 1805 groups = "i2c_ao_sda_e"; 1806 function = "i2c_ao"; 1807 bias-disable; 1808 drive-strength-microamp = <3000>; 1809 }; 1810 }; 1811 1812 mclk0_ao_pins: mclk0-ao { 1813 mux { 1814 groups = "mclk0_ao"; 1815 function = "mclk0_ao"; 1816 bias-disable; 1817 drive-strength-microamp = <3000>; 1818 }; 1819 }; 1820 1821 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1822 mux { 1823 groups = "tdm_ao_b_din0"; 1824 function = "tdm_ao_b"; 1825 bias-disable; 1826 }; 1827 }; 1828 1829 spdif_ao_out_pins: spdif-ao-out { 1830 mux { 1831 groups = "spdif_ao_out"; 1832 function = "spdif_ao_out"; 1833 drive-strength-microamp = <500>; 1834 bias-disable; 1835 }; 1836 }; 1837 1838 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1839 mux { 1840 groups = "tdm_ao_b_din1"; 1841 function = "tdm_ao_b"; 1842 bias-disable; 1843 }; 1844 }; 1845 1846 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1847 mux { 1848 groups = "tdm_ao_b_din2"; 1849 function = "tdm_ao_b"; 1850 bias-disable; 1851 }; 1852 }; 1853 1854 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1855 mux { 1856 groups = "tdm_ao_b_dout0"; 1857 function = "tdm_ao_b"; 1858 bias-disable; 1859 drive-strength-microamp = <3000>; 1860 }; 1861 }; 1862 1863 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1864 mux { 1865 groups = "tdm_ao_b_dout1"; 1866 function = "tdm_ao_b"; 1867 bias-disable; 1868 drive-strength-microamp = <3000>; 1869 }; 1870 }; 1871 1872 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1873 mux { 1874 groups = "tdm_ao_b_dout2"; 1875 function = "tdm_ao_b"; 1876 bias-disable; 1877 drive-strength-microamp = <3000>; 1878 }; 1879 }; 1880 1881 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1882 mux { 1883 groups = "tdm_ao_b_fs"; 1884 function = "tdm_ao_b"; 1885 bias-disable; 1886 drive-strength-microamp = <3000>; 1887 }; 1888 }; 1889 1890 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1891 mux { 1892 groups = "tdm_ao_b_sclk"; 1893 function = "tdm_ao_b"; 1894 bias-disable; 1895 drive-strength-microamp = <3000>; 1896 }; 1897 }; 1898 1899 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1900 mux { 1901 groups = "tdm_ao_b_slv_fs"; 1902 function = "tdm_ao_b"; 1903 bias-disable; 1904 }; 1905 }; 1906 1907 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1908 mux { 1909 groups = "tdm_ao_b_slv_sclk"; 1910 function = "tdm_ao_b"; 1911 bias-disable; 1912 }; 1913 }; 1914 1915 uart_ao_a_pins: uart-a-ao { 1916 mux { 1917 groups = "uart_ao_a_tx", 1918 "uart_ao_a_rx"; 1919 function = "uart_ao_a"; 1920 bias-disable; 1921 }; 1922 }; 1923 1924 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1925 mux { 1926 groups = "uart_ao_a_cts", 1927 "uart_ao_a_rts"; 1928 function = "uart_ao_a"; 1929 bias-disable; 1930 }; 1931 }; 1932 1933 pwm_a_e_pins: pwm-a-e { 1934 mux { 1935 groups = "pwm_a_e"; 1936 function = "pwm_a_e"; 1937 bias-disable; 1938 }; 1939 }; 1940 1941 pwm_ao_a_pins: pwm-ao-a { 1942 mux { 1943 groups = "pwm_ao_a"; 1944 function = "pwm_ao_a"; 1945 bias-disable; 1946 }; 1947 }; 1948 1949 pwm_ao_b_pins: pwm-ao-b { 1950 mux { 1951 groups = "pwm_ao_b"; 1952 function = "pwm_ao_b"; 1953 bias-disable; 1954 }; 1955 }; 1956 1957 pwm_ao_c_4_pins: pwm-ao-c-4 { 1958 mux { 1959 groups = "pwm_ao_c_4"; 1960 function = "pwm_ao_c"; 1961 bias-disable; 1962 }; 1963 }; 1964 1965 pwm_ao_c_6_pins: pwm-ao-c-6 { 1966 mux { 1967 groups = "pwm_ao_c_6"; 1968 function = "pwm_ao_c"; 1969 bias-disable; 1970 }; 1971 }; 1972 1973 pwm_ao_d_5_pins: pwm-ao-d-5 { 1974 mux { 1975 groups = "pwm_ao_d_5"; 1976 function = "pwm_ao_d"; 1977 bias-disable; 1978 }; 1979 }; 1980 1981 pwm_ao_d_10_pins: pwm-ao-d-10 { 1982 mux { 1983 groups = "pwm_ao_d_10"; 1984 function = "pwm_ao_d"; 1985 bias-disable; 1986 }; 1987 }; 1988 1989 pwm_ao_d_e_pins: pwm-ao-d-e { 1990 mux { 1991 groups = "pwm_ao_d_e"; 1992 function = "pwm_ao_d"; 1993 }; 1994 }; 1995 1996 remote_input_ao_pins: remote-input-ao { 1997 mux { 1998 groups = "remote_ao_input"; 1999 function = "remote_ao_input"; 2000 bias-disable; 2001 }; 2002 }; 2003 }; 2004 }; 2005 2006 vrtc: rtc@0a8 { 2007 compatible = "amlogic,meson-vrtc"; 2008 reg = <0x0 0x000a8 0x0 0x4>; 2009 }; 2010 2011 cec_AO: cec@100 { 2012 compatible = "amlogic,meson-gx-ao-cec"; 2013 reg = <0x0 0x00100 0x0 0x14>; 2014 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2015 clocks = <&clkc_AO CLKID_AO_CEC>; 2016 clock-names = "core"; 2017 status = "disabled"; 2018 }; 2019 2020 sec_AO: ao-secure@140 { 2021 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2022 reg = <0x0 0x140 0x0 0x140>; 2023 amlogic,has-chip-id; 2024 }; 2025 2026 cecb_AO: cec@280 { 2027 compatible = "amlogic,meson-g12a-ao-cec"; 2028 reg = <0x0 0x00280 0x0 0x1c>; 2029 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2030 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2031 clock-names = "oscin"; 2032 status = "disabled"; 2033 }; 2034 2035 pwm_AO_cd: pwm@2000 { 2036 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2037 reg = <0x0 0x2000 0x0 0x20>; 2038 #pwm-cells = <3>; 2039 status = "disabled"; 2040 }; 2041 2042 uart_AO: serial@3000 { 2043 compatible = "amlogic,meson-gx-uart", 2044 "amlogic,meson-ao-uart"; 2045 reg = <0x0 0x3000 0x0 0x18>; 2046 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2047 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2048 clock-names = "xtal", "pclk", "baud"; 2049 status = "disabled"; 2050 }; 2051 2052 uart_AO_B: serial@4000 { 2053 compatible = "amlogic,meson-gx-uart", 2054 "amlogic,meson-ao-uart"; 2055 reg = <0x0 0x4000 0x0 0x18>; 2056 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2057 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2058 clock-names = "xtal", "pclk", "baud"; 2059 status = "disabled"; 2060 }; 2061 2062 i2c_AO: i2c@5000 { 2063 compatible = "amlogic,meson-axg-i2c"; 2064 status = "disabled"; 2065 reg = <0x0 0x05000 0x0 0x20>; 2066 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2067 #address-cells = <1>; 2068 #size-cells = <0>; 2069 clocks = <&clkc CLKID_I2C>; 2070 }; 2071 2072 pwm_AO_ab: pwm@7000 { 2073 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2074 reg = <0x0 0x7000 0x0 0x20>; 2075 #pwm-cells = <3>; 2076 status = "disabled"; 2077 }; 2078 2079 ir: ir@8000 { 2080 compatible = "amlogic,meson-gxbb-ir"; 2081 reg = <0x0 0x8000 0x0 0x20>; 2082 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2083 status = "disabled"; 2084 }; 2085 2086 saradc: adc@9000 { 2087 compatible = "amlogic,meson-g12a-saradc", 2088 "amlogic,meson-saradc"; 2089 reg = <0x0 0x9000 0x0 0x48>; 2090 #io-channel-cells = <1>; 2091 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2092 clocks = <&xtal>, 2093 <&clkc_AO CLKID_AO_SAR_ADC>, 2094 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2095 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2096 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2097 status = "disabled"; 2098 }; 2099 }; 2100 2101 vdec: video-decoder@ff620000 { 2102 compatible = "amlogic,g12a-vdec"; 2103 reg = <0x0 0xff620000 0x0 0x10000>, 2104 <0x0 0xffd0e180 0x0 0xe4>; 2105 reg-names = "dos", "esparser"; 2106 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 2107 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 2108 interrupt-names = "vdec", "esparser"; 2109 2110 amlogic,ao-sysctrl = <&rti>; 2111 amlogic,canvas = <&canvas>; 2112 2113 clocks = <&clkc CLKID_PARSER>, 2114 <&clkc CLKID_DOS>, 2115 <&clkc CLKID_VDEC_1>, 2116 <&clkc CLKID_VDEC_HEVC>, 2117 <&clkc CLKID_VDEC_HEVCF>; 2118 clock-names = "dos_parser", "dos", "vdec_1", 2119 "vdec_hevc", "vdec_hevcf"; 2120 resets = <&reset RESET_PARSER>; 2121 reset-names = "esparser"; 2122 }; 2123 2124 vpu: vpu@ff900000 { 2125 compatible = "amlogic,meson-g12a-vpu"; 2126 reg = <0x0 0xff900000 0x0 0x100000>, 2127 <0x0 0xff63c000 0x0 0x1000>; 2128 reg-names = "vpu", "hhi"; 2129 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2130 #address-cells = <1>; 2131 #size-cells = <0>; 2132 amlogic,canvas = <&canvas>; 2133 2134 /* CVBS VDAC output port */ 2135 cvbs_vdac_port: port@0 { 2136 reg = <0>; 2137 }; 2138 2139 /* HDMI-TX output port */ 2140 hdmi_tx_port: port@1 { 2141 reg = <1>; 2142 2143 hdmi_tx_out: endpoint { 2144 remote-endpoint = <&hdmi_tx_in>; 2145 }; 2146 }; 2147 }; 2148 2149 gic: interrupt-controller@ffc01000 { 2150 compatible = "arm,gic-400"; 2151 reg = <0x0 0xffc01000 0 0x1000>, 2152 <0x0 0xffc02000 0 0x2000>, 2153 <0x0 0xffc04000 0 0x2000>, 2154 <0x0 0xffc06000 0 0x2000>; 2155 interrupt-controller; 2156 interrupts = <GIC_PPI 9 2157 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2158 #interrupt-cells = <3>; 2159 #address-cells = <0>; 2160 }; 2161 2162 cbus: bus@ffd00000 { 2163 compatible = "simple-bus"; 2164 reg = <0x0 0xffd00000 0x0 0x100000>; 2165 #address-cells = <2>; 2166 #size-cells = <2>; 2167 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2168 2169 reset: reset-controller@1004 { 2170 compatible = "amlogic,meson-axg-reset"; 2171 reg = <0x0 0x1004 0x0 0x9c>; 2172 #reset-cells = <1>; 2173 }; 2174 2175 gpio_intc: interrupt-controller@f080 { 2176 compatible = "amlogic,meson-g12a-gpio-intc", 2177 "amlogic,meson-gpio-intc"; 2178 reg = <0x0 0xf080 0x0 0x10>; 2179 interrupt-controller; 2180 #interrupt-cells = <2>; 2181 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2182 }; 2183 2184 watchdog: wdt@f0d0 { 2185 compatible = "amlogic,meson-gxbb-wdt"; 2186 reg = <0x0 0xf0d0 0x0 0x10>; 2187 clocks = <&xtal>; 2188 }; 2189 2190 spicc0: spi@13000 { 2191 compatible = "amlogic,meson-g12a-spicc"; 2192 reg = <0x0 0x13000 0x0 0x44>; 2193 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2194 clocks = <&clkc CLKID_SPICC0>, 2195 <&clkc CLKID_SPICC0_SCLK>; 2196 clock-names = "core", "pclk"; 2197 #address-cells = <1>; 2198 #size-cells = <0>; 2199 status = "disabled"; 2200 }; 2201 2202 spicc1: spi@15000 { 2203 compatible = "amlogic,meson-g12a-spicc"; 2204 reg = <0x0 0x15000 0x0 0x44>; 2205 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2206 clocks = <&clkc CLKID_SPICC1>, 2207 <&clkc CLKID_SPICC1_SCLK>; 2208 clock-names = "core", "pclk"; 2209 #address-cells = <1>; 2210 #size-cells = <0>; 2211 status = "disabled"; 2212 }; 2213 2214 spifc: spi@14000 { 2215 compatible = "amlogic,meson-gxbb-spifc"; 2216 status = "disabled"; 2217 reg = <0x0 0x14000 0x0 0x80>; 2218 #address-cells = <1>; 2219 #size-cells = <0>; 2220 clocks = <&clkc CLKID_CLK81>; 2221 }; 2222 2223 pwm_ef: pwm@19000 { 2224 compatible = "amlogic,meson-g12a-ee-pwm"; 2225 reg = <0x0 0x19000 0x0 0x20>; 2226 #pwm-cells = <3>; 2227 status = "disabled"; 2228 }; 2229 2230 pwm_cd: pwm@1a000 { 2231 compatible = "amlogic,meson-g12a-ee-pwm"; 2232 reg = <0x0 0x1a000 0x0 0x20>; 2233 #pwm-cells = <3>; 2234 status = "disabled"; 2235 }; 2236 2237 pwm_ab: pwm@1b000 { 2238 compatible = "amlogic,meson-g12a-ee-pwm"; 2239 reg = <0x0 0x1b000 0x0 0x20>; 2240 #pwm-cells = <3>; 2241 status = "disabled"; 2242 }; 2243 2244 i2c3: i2c@1c000 { 2245 compatible = "amlogic,meson-axg-i2c"; 2246 status = "disabled"; 2247 reg = <0x0 0x1c000 0x0 0x20>; 2248 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2249 #address-cells = <1>; 2250 #size-cells = <0>; 2251 clocks = <&clkc CLKID_I2C>; 2252 }; 2253 2254 i2c2: i2c@1d000 { 2255 compatible = "amlogic,meson-axg-i2c"; 2256 status = "disabled"; 2257 reg = <0x0 0x1d000 0x0 0x20>; 2258 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2259 #address-cells = <1>; 2260 #size-cells = <0>; 2261 clocks = <&clkc CLKID_I2C>; 2262 }; 2263 2264 i2c1: i2c@1e000 { 2265 compatible = "amlogic,meson-axg-i2c"; 2266 status = "disabled"; 2267 reg = <0x0 0x1e000 0x0 0x20>; 2268 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2269 #address-cells = <1>; 2270 #size-cells = <0>; 2271 clocks = <&clkc CLKID_I2C>; 2272 }; 2273 2274 i2c0: i2c@1f000 { 2275 compatible = "amlogic,meson-axg-i2c"; 2276 status = "disabled"; 2277 reg = <0x0 0x1f000 0x0 0x20>; 2278 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2279 #address-cells = <1>; 2280 #size-cells = <0>; 2281 clocks = <&clkc CLKID_I2C>; 2282 }; 2283 2284 clk_msr: clock-measure@18000 { 2285 compatible = "amlogic,meson-g12a-clk-measure"; 2286 reg = <0x0 0x18000 0x0 0x10>; 2287 }; 2288 2289 uart_C: serial@22000 { 2290 compatible = "amlogic,meson-gx-uart"; 2291 reg = <0x0 0x22000 0x0 0x18>; 2292 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2293 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2294 clock-names = "xtal", "pclk", "baud"; 2295 status = "disabled"; 2296 }; 2297 2298 uart_B: serial@23000 { 2299 compatible = "amlogic,meson-gx-uart"; 2300 reg = <0x0 0x23000 0x0 0x18>; 2301 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2302 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2303 clock-names = "xtal", "pclk", "baud"; 2304 status = "disabled"; 2305 }; 2306 2307 uart_A: serial@24000 { 2308 compatible = "amlogic,meson-gx-uart"; 2309 reg = <0x0 0x24000 0x0 0x18>; 2310 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2311 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2312 clock-names = "xtal", "pclk", "baud"; 2313 status = "disabled"; 2314 }; 2315 }; 2316 2317 sd_emmc_a: sd@ffe03000 { 2318 compatible = "amlogic,meson-axg-mmc"; 2319 reg = <0x0 0xffe03000 0x0 0x800>; 2320 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; 2321 status = "disabled"; 2322 clocks = <&clkc CLKID_SD_EMMC_A>, 2323 <&clkc CLKID_SD_EMMC_A_CLK0>, 2324 <&clkc CLKID_FCLK_DIV2>; 2325 clock-names = "core", "clkin0", "clkin1"; 2326 resets = <&reset RESET_SD_EMMC_A>; 2327 }; 2328 2329 sd_emmc_b: sd@ffe05000 { 2330 compatible = "amlogic,meson-axg-mmc"; 2331 reg = <0x0 0xffe05000 0x0 0x800>; 2332 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2333 status = "disabled"; 2334 clocks = <&clkc CLKID_SD_EMMC_B>, 2335 <&clkc CLKID_SD_EMMC_B_CLK0>, 2336 <&clkc CLKID_FCLK_DIV2>; 2337 clock-names = "core", "clkin0", "clkin1"; 2338 resets = <&reset RESET_SD_EMMC_B>; 2339 }; 2340 2341 sd_emmc_c: mmc@ffe07000 { 2342 compatible = "amlogic,meson-axg-mmc"; 2343 reg = <0x0 0xffe07000 0x0 0x800>; 2344 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2345 status = "disabled"; 2346 clocks = <&clkc CLKID_SD_EMMC_C>, 2347 <&clkc CLKID_SD_EMMC_C_CLK0>, 2348 <&clkc CLKID_FCLK_DIV2>; 2349 clock-names = "core", "clkin0", "clkin1"; 2350 resets = <&reset RESET_SD_EMMC_C>; 2351 }; 2352 2353 usb: usb@ffe09000 { 2354 status = "disabled"; 2355 compatible = "amlogic,meson-g12a-usb-ctrl"; 2356 reg = <0x0 0xffe09000 0x0 0xa0>; 2357 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2358 #address-cells = <2>; 2359 #size-cells = <2>; 2360 ranges; 2361 2362 clocks = <&clkc CLKID_USB>; 2363 resets = <&reset RESET_USB>; 2364 2365 dr_mode = "otg"; 2366 2367 phys = <&usb2_phy0>, <&usb2_phy1>, 2368 <&usb3_pcie_phy PHY_TYPE_USB3>; 2369 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2370 2371 dwc2: usb@ff400000 { 2372 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2373 reg = <0x0 0xff400000 0x0 0x40000>; 2374 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2375 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2376 clock-names = "otg"; 2377 phys = <&usb2_phy1>; 2378 phy-names = "usb2-phy"; 2379 dr_mode = "peripheral"; 2380 g-rx-fifo-size = <192>; 2381 g-np-tx-fifo-size = <128>; 2382 g-tx-fifo-size = <128 128 16 16 16>; 2383 }; 2384 2385 dwc3: usb@ff500000 { 2386 compatible = "snps,dwc3"; 2387 reg = <0x0 0xff500000 0x0 0x100000>; 2388 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2389 dr_mode = "host"; 2390 snps,dis_u2_susphy_quirk; 2391 snps,quirk-frame-length-adjustment = <0x20>; 2392 snps,parkmode-disable-ss-quirk; 2393 }; 2394 }; 2395 2396 mali: gpu@ffe40000 { 2397 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2398 reg = <0x0 0xffe40000 0x0 0x40000>; 2399 interrupt-parent = <&gic>; 2400 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2401 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2402 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2403 interrupt-names = "job", "mmu", "gpu"; 2404 clocks = <&clkc CLKID_MALI>; 2405 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2406 operating-points-v2 = <&gpu_opp_table>; 2407 #cooling-cells = <2>; 2408 }; 2409 }; 2410 2411 timer { 2412 compatible = "arm,armv8-timer"; 2413 interrupts = <GIC_PPI 13 2414 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2415 <GIC_PPI 14 2416 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2417 <GIC_PPI 11 2418 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2419 <GIC_PPI 10 2420 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2421 arm,no-tick-in-suspend; 2422 }; 2423 2424 xtal: xtal-clk { 2425 compatible = "fixed-clock"; 2426 clock-frequency = <24000000>; 2427 clock-output-names = "xtal"; 2428 #clock-cells = <0>; 2429 }; 2430 2431}; 2432