1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 mmc0 = &sd_emmc_b; /* SD card */ 22 mmc1 = &sd_emmc_c; /* eMMC */ 23 mmc2 = &sd_emmc_a; /* SDIO */ 24 }; 25 26 chosen { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 simplefb_cvbs: framebuffer-cvbs { 32 compatible = "amlogic,simple-framebuffer", 33 "simple-framebuffer"; 34 amlogic,pipeline = "vpu-cvbs"; 35 clocks = <&clkc CLKID_HDMI>, 36 <&clkc CLKID_HTX_PCLK>, 37 <&clkc CLKID_VPU_INTR>; 38 status = "disabled"; 39 }; 40 41 simplefb_hdmi: framebuffer-hdmi { 42 compatible = "amlogic,simple-framebuffer", 43 "simple-framebuffer"; 44 amlogic,pipeline = "vpu-hdmi"; 45 clocks = <&clkc CLKID_HDMI>, 46 <&clkc CLKID_HTX_PCLK>, 47 <&clkc CLKID_VPU_INTR>; 48 status = "disabled"; 49 }; 50 }; 51 52 efuse: efuse { 53 compatible = "amlogic,meson-gxbb-efuse"; 54 clocks = <&clkc CLKID_EFUSE>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 read-only; 58 secure-monitor = <&sm>; 59 }; 60 61 gpu_opp_table: opp-table-gpu { 62 compatible = "operating-points-v2"; 63 64 opp-124999998 { 65 opp-hz = /bits/ 64 <124999998>; 66 opp-microvolt = <800000>; 67 }; 68 opp-249999996 { 69 opp-hz = /bits/ 64 <249999996>; 70 opp-microvolt = <800000>; 71 }; 72 opp-285714281 { 73 opp-hz = /bits/ 64 <285714281>; 74 opp-microvolt = <800000>; 75 }; 76 opp-399999994 { 77 opp-hz = /bits/ 64 <399999994>; 78 opp-microvolt = <800000>; 79 }; 80 opp-499999992 { 81 opp-hz = /bits/ 64 <499999992>; 82 opp-microvolt = <800000>; 83 }; 84 opp-666666656 { 85 opp-hz = /bits/ 64 <666666656>; 86 opp-microvolt = <800000>; 87 }; 88 opp-799999987 { 89 opp-hz = /bits/ 64 <799999987>; 90 opp-microvolt = <800000>; 91 }; 92 }; 93 94 psci { 95 compatible = "arm,psci-1.0"; 96 method = "smc"; 97 }; 98 99 reserved-memory { 100 #address-cells = <2>; 101 #size-cells = <2>; 102 ranges; 103 104 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 105 secmon_reserved: secmon@5000000 { 106 reg = <0x0 0x05000000 0x0 0x300000>; 107 no-map; 108 }; 109 110 linux,cma { 111 compatible = "shared-dma-pool"; 112 reusable; 113 size = <0x0 0x10000000>; 114 alignment = <0x0 0x400000>; 115 linux,cma-default; 116 }; 117 }; 118 119 sm: secure-monitor { 120 compatible = "amlogic,meson-gxbb-sm"; 121 }; 122 123 soc { 124 compatible = "simple-bus"; 125 #address-cells = <2>; 126 #size-cells = <2>; 127 ranges; 128 129 pcie: pcie@fc000000 { 130 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 131 reg = <0x0 0xfc000000 0x0 0x400000>, 132 <0x0 0xff648000 0x0 0x2000>, 133 <0x0 0xfc400000 0x0 0x200000>; 134 reg-names = "elbi", "cfg", "config"; 135 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 136 #interrupt-cells = <1>; 137 interrupt-map-mask = <0 0 0 0>; 138 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 139 bus-range = <0x0 0xff>; 140 #address-cells = <3>; 141 #size-cells = <2>; 142 device_type = "pci"; 143 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, 144 <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 145 146 clocks = <&clkc CLKID_PCIE_PHY 147 &clkc CLKID_PCIE_COMB 148 &clkc CLKID_PCIE_PLL>; 149 clock-names = "general", 150 "pclk", 151 "port"; 152 resets = <&reset RESET_PCIE_CTRL_A>, 153 <&reset RESET_PCIE_APB>; 154 reset-names = "port", 155 "apb"; 156 num-lanes = <1>; 157 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 158 phy-names = "pcie"; 159 status = "disabled"; 160 }; 161 162 ethmac: ethernet@ff3f0000 { 163 compatible = "amlogic,meson-g12a-dwmac", 164 "snps,dwmac-3.70a", 165 "snps,dwmac"; 166 reg = <0x0 0xff3f0000 0x0 0x10000>, 167 <0x0 0xff634540 0x0 0x8>; 168 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 169 interrupt-names = "macirq"; 170 clocks = <&clkc CLKID_ETH>, 171 <&clkc CLKID_FCLK_DIV2>, 172 <&clkc CLKID_MPLL2>, 173 <&clkc CLKID_FCLK_DIV2>; 174 clock-names = "stmmaceth", "clkin0", "clkin1", 175 "timing-adjustment"; 176 rx-fifo-depth = <4096>; 177 tx-fifo-depth = <2048>; 178 status = "disabled"; 179 180 mdio0: mdio { 181 #address-cells = <1>; 182 #size-cells = <0>; 183 compatible = "snps,dwmac-mdio"; 184 }; 185 }; 186 187 apb: bus@ff600000 { 188 compatible = "simple-bus"; 189 reg = <0x0 0xff600000 0x0 0x200000>; 190 #address-cells = <2>; 191 #size-cells = <2>; 192 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 193 194 hdmi_tx: hdmi-tx@0 { 195 compatible = "amlogic,meson-g12a-dw-hdmi"; 196 reg = <0x0 0x0 0x0 0x10000>; 197 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 198 resets = <&reset RESET_HDMITX_CAPB3>, 199 <&reset RESET_HDMITX_PHY>, 200 <&reset RESET_HDMITX>; 201 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 202 clocks = <&clkc CLKID_HDMI>, 203 <&clkc CLKID_HTX_PCLK>, 204 <&clkc CLKID_VPU_INTR>; 205 clock-names = "isfr", "iahb", "venci"; 206 #address-cells = <1>; 207 #size-cells = <0>; 208 #sound-dai-cells = <0>; 209 status = "disabled"; 210 211 /* VPU VENC Input */ 212 hdmi_tx_venc_port: port@0 { 213 reg = <0>; 214 215 hdmi_tx_in: endpoint { 216 remote-endpoint = <&hdmi_tx_out>; 217 }; 218 }; 219 220 /* TMDS Output */ 221 hdmi_tx_tmds_port: port@1 { 222 reg = <1>; 223 }; 224 }; 225 226 apb_efuse: bus@30000 { 227 compatible = "simple-bus"; 228 reg = <0x0 0x30000 0x0 0x2000>; 229 #address-cells = <2>; 230 #size-cells = <2>; 231 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 232 233 hwrng: rng@218 { 234 compatible = "amlogic,meson-rng"; 235 reg = <0x0 0x218 0x0 0x4>; 236 clocks = <&clkc CLKID_RNG0>; 237 clock-names = "core"; 238 }; 239 }; 240 241 acodec: audio-controller@32000 { 242 compatible = "amlogic,t9015"; 243 reg = <0x0 0x32000 0x0 0x14>; 244 #sound-dai-cells = <0>; 245 sound-name-prefix = "ACODEC"; 246 clocks = <&clkc CLKID_AUDIO_CODEC>; 247 clock-names = "pclk"; 248 resets = <&reset RESET_AUDIO_CODEC>; 249 status = "disabled"; 250 }; 251 252 periphs: bus@34400 { 253 compatible = "simple-bus"; 254 reg = <0x0 0x34400 0x0 0x400>; 255 #address-cells = <2>; 256 #size-cells = <2>; 257 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 258 259 periphs_pinctrl: pinctrl@40 { 260 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 261 #address-cells = <2>; 262 #size-cells = <2>; 263 ranges; 264 265 gpio: bank@40 { 266 reg = <0x0 0x40 0x0 0x4c>, 267 <0x0 0xe8 0x0 0x18>, 268 <0x0 0x120 0x0 0x18>, 269 <0x0 0x2c0 0x0 0x40>, 270 <0x0 0x340 0x0 0x1c>; 271 reg-names = "gpio", 272 "pull", 273 "pull-enable", 274 "mux", 275 "ds"; 276 gpio-controller; 277 #gpio-cells = <2>; 278 gpio-ranges = <&periphs_pinctrl 0 0 86>; 279 }; 280 281 cec_ao_a_h_pins: cec_ao_a_h { 282 mux { 283 groups = "cec_ao_a_h"; 284 function = "cec_ao_a_h"; 285 bias-disable; 286 }; 287 }; 288 289 cec_ao_b_h_pins: cec_ao_b_h { 290 mux { 291 groups = "cec_ao_b_h"; 292 function = "cec_ao_b_h"; 293 bias-disable; 294 }; 295 }; 296 297 emmc_ctrl_pins: emmc-ctrl { 298 mux-0 { 299 groups = "emmc_cmd"; 300 function = "emmc"; 301 bias-pull-up; 302 drive-strength-microamp = <4000>; 303 }; 304 305 mux-1 { 306 groups = "emmc_clk"; 307 function = "emmc"; 308 bias-disable; 309 drive-strength-microamp = <4000>; 310 }; 311 }; 312 313 emmc_data_4b_pins: emmc-data-4b { 314 mux-0 { 315 groups = "emmc_nand_d0", 316 "emmc_nand_d1", 317 "emmc_nand_d2", 318 "emmc_nand_d3"; 319 function = "emmc"; 320 bias-pull-up; 321 drive-strength-microamp = <4000>; 322 }; 323 }; 324 325 emmc_data_8b_pins: emmc-data-8b { 326 mux-0 { 327 groups = "emmc_nand_d0", 328 "emmc_nand_d1", 329 "emmc_nand_d2", 330 "emmc_nand_d3", 331 "emmc_nand_d4", 332 "emmc_nand_d5", 333 "emmc_nand_d6", 334 "emmc_nand_d7"; 335 function = "emmc"; 336 bias-pull-up; 337 drive-strength-microamp = <4000>; 338 }; 339 }; 340 341 emmc_ds_pins: emmc-ds { 342 mux { 343 groups = "emmc_nand_ds"; 344 function = "emmc"; 345 bias-pull-down; 346 drive-strength-microamp = <4000>; 347 }; 348 }; 349 350 emmc_clk_gate_pins: emmc_clk_gate { 351 mux { 352 groups = "BOOT_8"; 353 function = "gpio_periphs"; 354 bias-pull-down; 355 drive-strength-microamp = <4000>; 356 }; 357 }; 358 359 hdmitx_ddc_pins: hdmitx_ddc { 360 mux { 361 groups = "hdmitx_sda", 362 "hdmitx_sck"; 363 function = "hdmitx"; 364 bias-disable; 365 drive-strength-microamp = <4000>; 366 }; 367 }; 368 369 hdmitx_hpd_pins: hdmitx_hpd { 370 mux { 371 groups = "hdmitx_hpd_in"; 372 function = "hdmitx"; 373 bias-disable; 374 }; 375 }; 376 377 378 i2c0_sda_c_pins: i2c0-sda-c { 379 mux { 380 groups = "i2c0_sda_c"; 381 function = "i2c0"; 382 bias-disable; 383 drive-strength-microamp = <3000>; 384 385 }; 386 }; 387 388 i2c0_sck_c_pins: i2c0-sck-c { 389 mux { 390 groups = "i2c0_sck_c"; 391 function = "i2c0"; 392 bias-disable; 393 drive-strength-microamp = <3000>; 394 }; 395 }; 396 397 i2c0_sda_z0_pins: i2c0-sda-z0 { 398 mux { 399 groups = "i2c0_sda_z0"; 400 function = "i2c0"; 401 bias-disable; 402 drive-strength-microamp = <3000>; 403 }; 404 }; 405 406 i2c0_sck_z1_pins: i2c0-sck-z1 { 407 mux { 408 groups = "i2c0_sck_z1"; 409 function = "i2c0"; 410 bias-disable; 411 drive-strength-microamp = <3000>; 412 }; 413 }; 414 415 i2c0_sda_z7_pins: i2c0-sda-z7 { 416 mux { 417 groups = "i2c0_sda_z7"; 418 function = "i2c0"; 419 bias-disable; 420 drive-strength-microamp = <3000>; 421 }; 422 }; 423 424 i2c0_sda_z8_pins: i2c0-sda-z8 { 425 mux { 426 groups = "i2c0_sda_z8"; 427 function = "i2c0"; 428 bias-disable; 429 drive-strength-microamp = <3000>; 430 }; 431 }; 432 433 i2c1_sda_x_pins: i2c1-sda-x { 434 mux { 435 groups = "i2c1_sda_x"; 436 function = "i2c1"; 437 bias-disable; 438 drive-strength-microamp = <3000>; 439 }; 440 }; 441 442 i2c1_sck_x_pins: i2c1-sck-x { 443 mux { 444 groups = "i2c1_sck_x"; 445 function = "i2c1"; 446 bias-disable; 447 drive-strength-microamp = <3000>; 448 }; 449 }; 450 451 i2c1_sda_h2_pins: i2c1-sda-h2 { 452 mux { 453 groups = "i2c1_sda_h2"; 454 function = "i2c1"; 455 bias-disable; 456 drive-strength-microamp = <3000>; 457 }; 458 }; 459 460 i2c1_sck_h3_pins: i2c1-sck-h3 { 461 mux { 462 groups = "i2c1_sck_h3"; 463 function = "i2c1"; 464 bias-disable; 465 drive-strength-microamp = <3000>; 466 }; 467 }; 468 469 i2c1_sda_h6_pins: i2c1-sda-h6 { 470 mux { 471 groups = "i2c1_sda_h6"; 472 function = "i2c1"; 473 bias-disable; 474 drive-strength-microamp = <3000>; 475 }; 476 }; 477 478 i2c1_sck_h7_pins: i2c1-sck-h7 { 479 mux { 480 groups = "i2c1_sck_h7"; 481 function = "i2c1"; 482 bias-disable; 483 drive-strength-microamp = <3000>; 484 }; 485 }; 486 487 i2c2_sda_x_pins: i2c2-sda-x { 488 mux { 489 groups = "i2c2_sda_x"; 490 function = "i2c2"; 491 bias-disable; 492 drive-strength-microamp = <3000>; 493 }; 494 }; 495 496 i2c2_sck_x_pins: i2c2-sck-x { 497 mux { 498 groups = "i2c2_sck_x"; 499 function = "i2c2"; 500 bias-disable; 501 drive-strength-microamp = <3000>; 502 }; 503 }; 504 505 i2c2_sda_z_pins: i2c2-sda-z { 506 mux { 507 groups = "i2c2_sda_z"; 508 function = "i2c2"; 509 bias-disable; 510 drive-strength-microamp = <3000>; 511 }; 512 }; 513 514 i2c2_sck_z_pins: i2c2-sck-z { 515 mux { 516 groups = "i2c2_sck_z"; 517 function = "i2c2"; 518 bias-disable; 519 drive-strength-microamp = <3000>; 520 }; 521 }; 522 523 i2c3_sda_h_pins: i2c3-sda-h { 524 mux { 525 groups = "i2c3_sda_h"; 526 function = "i2c3"; 527 bias-disable; 528 drive-strength-microamp = <3000>; 529 }; 530 }; 531 532 i2c3_sck_h_pins: i2c3-sck-h { 533 mux { 534 groups = "i2c3_sck_h"; 535 function = "i2c3"; 536 bias-disable; 537 drive-strength-microamp = <3000>; 538 }; 539 }; 540 541 i2c3_sda_a_pins: i2c3-sda-a { 542 mux { 543 groups = "i2c3_sda_a"; 544 function = "i2c3"; 545 bias-disable; 546 drive-strength-microamp = <3000>; 547 }; 548 }; 549 550 i2c3_sck_a_pins: i2c3-sck-a { 551 mux { 552 groups = "i2c3_sck_a"; 553 function = "i2c3"; 554 bias-disable; 555 drive-strength-microamp = <3000>; 556 }; 557 }; 558 559 mclk0_a_pins: mclk0-a { 560 mux { 561 groups = "mclk0_a"; 562 function = "mclk0"; 563 bias-disable; 564 drive-strength-microamp = <3000>; 565 }; 566 }; 567 568 mclk1_a_pins: mclk1-a { 569 mux { 570 groups = "mclk1_a"; 571 function = "mclk1"; 572 bias-disable; 573 drive-strength-microamp = <3000>; 574 }; 575 }; 576 577 mclk1_x_pins: mclk1-x { 578 mux { 579 groups = "mclk1_x"; 580 function = "mclk1"; 581 bias-disable; 582 drive-strength-microamp = <3000>; 583 }; 584 }; 585 586 mclk1_z_pins: mclk1-z { 587 mux { 588 groups = "mclk1_z"; 589 function = "mclk1"; 590 bias-disable; 591 drive-strength-microamp = <3000>; 592 }; 593 }; 594 595 nor_pins: nor { 596 mux { 597 groups = "nor_d", 598 "nor_q", 599 "nor_c", 600 "nor_cs"; 601 function = "nor"; 602 bias-disable; 603 }; 604 }; 605 606 pdm_din0_a_pins: pdm-din0-a { 607 mux { 608 groups = "pdm_din0_a"; 609 function = "pdm"; 610 bias-disable; 611 }; 612 }; 613 614 pdm_din0_c_pins: pdm-din0-c { 615 mux { 616 groups = "pdm_din0_c"; 617 function = "pdm"; 618 bias-disable; 619 }; 620 }; 621 622 pdm_din0_x_pins: pdm-din0-x { 623 mux { 624 groups = "pdm_din0_x"; 625 function = "pdm"; 626 bias-disable; 627 }; 628 }; 629 630 pdm_din0_z_pins: pdm-din0-z { 631 mux { 632 groups = "pdm_din0_z"; 633 function = "pdm"; 634 bias-disable; 635 }; 636 }; 637 638 pdm_din1_a_pins: pdm-din1-a { 639 mux { 640 groups = "pdm_din1_a"; 641 function = "pdm"; 642 bias-disable; 643 }; 644 }; 645 646 pdm_din1_c_pins: pdm-din1-c { 647 mux { 648 groups = "pdm_din1_c"; 649 function = "pdm"; 650 bias-disable; 651 }; 652 }; 653 654 pdm_din1_x_pins: pdm-din1-x { 655 mux { 656 groups = "pdm_din1_x"; 657 function = "pdm"; 658 bias-disable; 659 }; 660 }; 661 662 pdm_din1_z_pins: pdm-din1-z { 663 mux { 664 groups = "pdm_din1_z"; 665 function = "pdm"; 666 bias-disable; 667 }; 668 }; 669 670 pdm_din2_a_pins: pdm-din2-a { 671 mux { 672 groups = "pdm_din2_a"; 673 function = "pdm"; 674 bias-disable; 675 }; 676 }; 677 678 pdm_din2_c_pins: pdm-din2-c { 679 mux { 680 groups = "pdm_din2_c"; 681 function = "pdm"; 682 bias-disable; 683 }; 684 }; 685 686 pdm_din2_x_pins: pdm-din2-x { 687 mux { 688 groups = "pdm_din2_x"; 689 function = "pdm"; 690 bias-disable; 691 }; 692 }; 693 694 pdm_din2_z_pins: pdm-din2-z { 695 mux { 696 groups = "pdm_din2_z"; 697 function = "pdm"; 698 bias-disable; 699 }; 700 }; 701 702 pdm_din3_a_pins: pdm-din3-a { 703 mux { 704 groups = "pdm_din3_a"; 705 function = "pdm"; 706 bias-disable; 707 }; 708 }; 709 710 pdm_din3_c_pins: pdm-din3-c { 711 mux { 712 groups = "pdm_din3_c"; 713 function = "pdm"; 714 bias-disable; 715 }; 716 }; 717 718 pdm_din3_x_pins: pdm-din3-x { 719 mux { 720 groups = "pdm_din3_x"; 721 function = "pdm"; 722 bias-disable; 723 }; 724 }; 725 726 pdm_din3_z_pins: pdm-din3-z { 727 mux { 728 groups = "pdm_din3_z"; 729 function = "pdm"; 730 bias-disable; 731 }; 732 }; 733 734 pdm_dclk_a_pins: pdm-dclk-a { 735 mux { 736 groups = "pdm_dclk_a"; 737 function = "pdm"; 738 bias-disable; 739 drive-strength-microamp = <500>; 740 }; 741 }; 742 743 pdm_dclk_c_pins: pdm-dclk-c { 744 mux { 745 groups = "pdm_dclk_c"; 746 function = "pdm"; 747 bias-disable; 748 drive-strength-microamp = <500>; 749 }; 750 }; 751 752 pdm_dclk_x_pins: pdm-dclk-x { 753 mux { 754 groups = "pdm_dclk_x"; 755 function = "pdm"; 756 bias-disable; 757 drive-strength-microamp = <500>; 758 }; 759 }; 760 761 pdm_dclk_z_pins: pdm-dclk-z { 762 mux { 763 groups = "pdm_dclk_z"; 764 function = "pdm"; 765 bias-disable; 766 drive-strength-microamp = <500>; 767 }; 768 }; 769 770 pwm_a_pins: pwm-a { 771 mux { 772 groups = "pwm_a"; 773 function = "pwm_a"; 774 bias-disable; 775 }; 776 }; 777 778 pwm_b_x7_pins: pwm-b-x7 { 779 mux { 780 groups = "pwm_b_x7"; 781 function = "pwm_b"; 782 bias-disable; 783 }; 784 }; 785 786 pwm_b_x19_pins: pwm-b-x19 { 787 mux { 788 groups = "pwm_b_x19"; 789 function = "pwm_b"; 790 bias-disable; 791 }; 792 }; 793 794 pwm_c_c_pins: pwm-c-c { 795 mux { 796 groups = "pwm_c_c"; 797 function = "pwm_c"; 798 bias-disable; 799 }; 800 }; 801 802 pwm_c_x5_pins: pwm-c-x5 { 803 mux { 804 groups = "pwm_c_x5"; 805 function = "pwm_c"; 806 bias-disable; 807 }; 808 }; 809 810 pwm_c_x8_pins: pwm-c-x8 { 811 mux { 812 groups = "pwm_c_x8"; 813 function = "pwm_c"; 814 bias-disable; 815 }; 816 }; 817 818 pwm_d_x3_pins: pwm-d-x3 { 819 mux { 820 groups = "pwm_d_x3"; 821 function = "pwm_d"; 822 bias-disable; 823 }; 824 }; 825 826 pwm_d_x6_pins: pwm-d-x6 { 827 mux { 828 groups = "pwm_d_x6"; 829 function = "pwm_d"; 830 bias-disable; 831 }; 832 }; 833 834 pwm_e_pins: pwm-e { 835 mux { 836 groups = "pwm_e"; 837 function = "pwm_e"; 838 bias-disable; 839 }; 840 }; 841 842 pwm_f_x_pins: pwm-f-x { 843 mux { 844 groups = "pwm_f_x"; 845 function = "pwm_f"; 846 bias-disable; 847 }; 848 }; 849 850 pwm_f_h_pins: pwm-f-h { 851 mux { 852 groups = "pwm_f_h"; 853 function = "pwm_f"; 854 bias-disable; 855 }; 856 }; 857 858 sdcard_c_pins: sdcard_c { 859 mux-0 { 860 groups = "sdcard_d0_c", 861 "sdcard_d1_c", 862 "sdcard_d2_c", 863 "sdcard_d3_c", 864 "sdcard_cmd_c"; 865 function = "sdcard"; 866 bias-pull-up; 867 drive-strength-microamp = <4000>; 868 }; 869 870 mux-1 { 871 groups = "sdcard_clk_c"; 872 function = "sdcard"; 873 bias-disable; 874 drive-strength-microamp = <4000>; 875 }; 876 }; 877 878 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 879 mux { 880 groups = "GPIOC_4"; 881 function = "gpio_periphs"; 882 bias-pull-down; 883 drive-strength-microamp = <4000>; 884 }; 885 }; 886 887 sdcard_z_pins: sdcard_z { 888 mux-0 { 889 groups = "sdcard_d0_z", 890 "sdcard_d1_z", 891 "sdcard_d2_z", 892 "sdcard_d3_z", 893 "sdcard_cmd_z"; 894 function = "sdcard"; 895 bias-pull-up; 896 drive-strength-microamp = <4000>; 897 }; 898 899 mux-1 { 900 groups = "sdcard_clk_z"; 901 function = "sdcard"; 902 bias-disable; 903 drive-strength-microamp = <4000>; 904 }; 905 }; 906 907 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 908 mux { 909 groups = "GPIOZ_6"; 910 function = "gpio_periphs"; 911 bias-pull-down; 912 drive-strength-microamp = <4000>; 913 }; 914 }; 915 916 sdio_pins: sdio { 917 mux { 918 groups = "sdio_d0", 919 "sdio_d1", 920 "sdio_d2", 921 "sdio_d3", 922 "sdio_clk", 923 "sdio_cmd"; 924 function = "sdio"; 925 bias-disable; 926 drive-strength-microamp = <4000>; 927 }; 928 }; 929 930 sdio_clk_gate_pins: sdio_clk_gate { 931 mux { 932 groups = "GPIOX_4"; 933 function = "gpio_periphs"; 934 bias-pull-down; 935 drive-strength-microamp = <4000>; 936 }; 937 }; 938 939 spdif_in_a10_pins: spdif-in-a10 { 940 mux { 941 groups = "spdif_in_a10"; 942 function = "spdif_in"; 943 bias-disable; 944 }; 945 }; 946 947 spdif_in_a12_pins: spdif-in-a12 { 948 mux { 949 groups = "spdif_in_a12"; 950 function = "spdif_in"; 951 bias-disable; 952 }; 953 }; 954 955 spdif_in_h_pins: spdif-in-h { 956 mux { 957 groups = "spdif_in_h"; 958 function = "spdif_in"; 959 bias-disable; 960 }; 961 }; 962 963 spdif_out_h_pins: spdif-out-h { 964 mux { 965 groups = "spdif_out_h"; 966 function = "spdif_out"; 967 drive-strength-microamp = <500>; 968 bias-disable; 969 }; 970 }; 971 972 spdif_out_a11_pins: spdif-out-a11 { 973 mux { 974 groups = "spdif_out_a11"; 975 function = "spdif_out"; 976 drive-strength-microamp = <500>; 977 bias-disable; 978 }; 979 }; 980 981 spdif_out_a13_pins: spdif-out-a13 { 982 mux { 983 groups = "spdif_out_a13"; 984 function = "spdif_out"; 985 drive-strength-microamp = <500>; 986 bias-disable; 987 }; 988 }; 989 990 spicc0_x_pins: spicc0-x { 991 mux { 992 groups = "spi0_mosi_x", 993 "spi0_miso_x", 994 "spi0_clk_x"; 995 function = "spi0"; 996 drive-strength-microamp = <4000>; 997 bias-disable; 998 }; 999 }; 1000 1001 spicc0_ss0_x_pins: spicc0-ss0-x { 1002 mux { 1003 groups = "spi0_ss0_x"; 1004 function = "spi0"; 1005 drive-strength-microamp = <4000>; 1006 bias-disable; 1007 }; 1008 }; 1009 1010 spicc0_c_pins: spicc0-c { 1011 mux { 1012 groups = "spi0_mosi_c", 1013 "spi0_miso_c", 1014 "spi0_ss0_c", 1015 "spi0_clk_c"; 1016 function = "spi0"; 1017 drive-strength-microamp = <4000>; 1018 bias-disable; 1019 }; 1020 }; 1021 1022 spicc1_pins: spicc1 { 1023 mux { 1024 groups = "spi1_mosi", 1025 "spi1_miso", 1026 "spi1_clk"; 1027 function = "spi1"; 1028 drive-strength-microamp = <4000>; 1029 }; 1030 }; 1031 1032 spicc1_ss0_pins: spicc1-ss0 { 1033 mux { 1034 groups = "spi1_ss0"; 1035 function = "spi1"; 1036 drive-strength-microamp = <4000>; 1037 bias-disable; 1038 }; 1039 }; 1040 1041 tdm_a_din0_pins: tdm-a-din0 { 1042 mux { 1043 groups = "tdm_a_din0"; 1044 function = "tdm_a"; 1045 bias-disable; 1046 }; 1047 }; 1048 1049 1050 tdm_a_din1_pins: tdm-a-din1 { 1051 mux { 1052 groups = "tdm_a_din1"; 1053 function = "tdm_a"; 1054 bias-disable; 1055 }; 1056 }; 1057 1058 tdm_a_dout0_pins: tdm-a-dout0 { 1059 mux { 1060 groups = "tdm_a_dout0"; 1061 function = "tdm_a"; 1062 bias-disable; 1063 drive-strength-microamp = <3000>; 1064 }; 1065 }; 1066 1067 tdm_a_dout1_pins: tdm-a-dout1 { 1068 mux { 1069 groups = "tdm_a_dout1"; 1070 function = "tdm_a"; 1071 bias-disable; 1072 drive-strength-microamp = <3000>; 1073 }; 1074 }; 1075 1076 tdm_a_fs_pins: tdm-a-fs { 1077 mux { 1078 groups = "tdm_a_fs"; 1079 function = "tdm_a"; 1080 bias-disable; 1081 drive-strength-microamp = <3000>; 1082 }; 1083 }; 1084 1085 tdm_a_sclk_pins: tdm-a-sclk { 1086 mux { 1087 groups = "tdm_a_sclk"; 1088 function = "tdm_a"; 1089 bias-disable; 1090 drive-strength-microamp = <3000>; 1091 }; 1092 }; 1093 1094 tdm_a_slv_fs_pins: tdm-a-slv-fs { 1095 mux { 1096 groups = "tdm_a_slv_fs"; 1097 function = "tdm_a"; 1098 bias-disable; 1099 }; 1100 }; 1101 1102 1103 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 1104 mux { 1105 groups = "tdm_a_slv_sclk"; 1106 function = "tdm_a"; 1107 bias-disable; 1108 }; 1109 }; 1110 1111 tdm_b_din0_pins: tdm-b-din0 { 1112 mux { 1113 groups = "tdm_b_din0"; 1114 function = "tdm_b"; 1115 bias-disable; 1116 }; 1117 }; 1118 1119 tdm_b_din1_pins: tdm-b-din1 { 1120 mux { 1121 groups = "tdm_b_din1"; 1122 function = "tdm_b"; 1123 bias-disable; 1124 }; 1125 }; 1126 1127 tdm_b_din2_pins: tdm-b-din2 { 1128 mux { 1129 groups = "tdm_b_din2"; 1130 function = "tdm_b"; 1131 bias-disable; 1132 }; 1133 }; 1134 1135 tdm_b_din3_a_pins: tdm-b-din3-a { 1136 mux { 1137 groups = "tdm_b_din3_a"; 1138 function = "tdm_b"; 1139 bias-disable; 1140 }; 1141 }; 1142 1143 tdm_b_din3_h_pins: tdm-b-din3-h { 1144 mux { 1145 groups = "tdm_b_din3_h"; 1146 function = "tdm_b"; 1147 bias-disable; 1148 }; 1149 }; 1150 1151 tdm_b_dout0_pins: tdm-b-dout0 { 1152 mux { 1153 groups = "tdm_b_dout0"; 1154 function = "tdm_b"; 1155 bias-disable; 1156 drive-strength-microamp = <3000>; 1157 }; 1158 }; 1159 1160 tdm_b_dout1_pins: tdm-b-dout1 { 1161 mux { 1162 groups = "tdm_b_dout1"; 1163 function = "tdm_b"; 1164 bias-disable; 1165 drive-strength-microamp = <3000>; 1166 }; 1167 }; 1168 1169 tdm_b_dout2_pins: tdm-b-dout2 { 1170 mux { 1171 groups = "tdm_b_dout2"; 1172 function = "tdm_b"; 1173 bias-disable; 1174 drive-strength-microamp = <3000>; 1175 }; 1176 }; 1177 1178 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1179 mux { 1180 groups = "tdm_b_dout3_a"; 1181 function = "tdm_b"; 1182 bias-disable; 1183 drive-strength-microamp = <3000>; 1184 }; 1185 }; 1186 1187 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1188 mux { 1189 groups = "tdm_b_dout3_h"; 1190 function = "tdm_b"; 1191 bias-disable; 1192 drive-strength-microamp = <3000>; 1193 }; 1194 }; 1195 1196 tdm_b_fs_pins: tdm-b-fs { 1197 mux { 1198 groups = "tdm_b_fs"; 1199 function = "tdm_b"; 1200 bias-disable; 1201 drive-strength-microamp = <3000>; 1202 }; 1203 }; 1204 1205 tdm_b_sclk_pins: tdm-b-sclk { 1206 mux { 1207 groups = "tdm_b_sclk"; 1208 function = "tdm_b"; 1209 bias-disable; 1210 drive-strength-microamp = <3000>; 1211 }; 1212 }; 1213 1214 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1215 mux { 1216 groups = "tdm_b_slv_fs"; 1217 function = "tdm_b"; 1218 bias-disable; 1219 }; 1220 }; 1221 1222 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1223 mux { 1224 groups = "tdm_b_slv_sclk"; 1225 function = "tdm_b"; 1226 bias-disable; 1227 }; 1228 }; 1229 1230 tdm_c_din0_a_pins: tdm-c-din0-a { 1231 mux { 1232 groups = "tdm_c_din0_a"; 1233 function = "tdm_c"; 1234 bias-disable; 1235 }; 1236 }; 1237 1238 tdm_c_din0_z_pins: tdm-c-din0-z { 1239 mux { 1240 groups = "tdm_c_din0_z"; 1241 function = "tdm_c"; 1242 bias-disable; 1243 }; 1244 }; 1245 1246 tdm_c_din1_a_pins: tdm-c-din1-a { 1247 mux { 1248 groups = "tdm_c_din1_a"; 1249 function = "tdm_c"; 1250 bias-disable; 1251 }; 1252 }; 1253 1254 tdm_c_din1_z_pins: tdm-c-din1-z { 1255 mux { 1256 groups = "tdm_c_din1_z"; 1257 function = "tdm_c"; 1258 bias-disable; 1259 }; 1260 }; 1261 1262 tdm_c_din2_a_pins: tdm-c-din2-a { 1263 mux { 1264 groups = "tdm_c_din2_a"; 1265 function = "tdm_c"; 1266 bias-disable; 1267 }; 1268 }; 1269 1270 eth_leds_pins: eth-leds { 1271 mux { 1272 groups = "eth_link_led", 1273 "eth_act_led"; 1274 function = "eth"; 1275 bias-disable; 1276 }; 1277 }; 1278 1279 eth_pins: eth { 1280 mux { 1281 groups = "eth_mdio", 1282 "eth_mdc", 1283 "eth_rgmii_rx_clk", 1284 "eth_rx_dv", 1285 "eth_rxd0", 1286 "eth_rxd1", 1287 "eth_txen", 1288 "eth_txd0", 1289 "eth_txd1"; 1290 function = "eth"; 1291 drive-strength-microamp = <4000>; 1292 bias-disable; 1293 }; 1294 }; 1295 1296 eth_rgmii_pins: eth-rgmii { 1297 mux { 1298 groups = "eth_rxd2_rgmii", 1299 "eth_rxd3_rgmii", 1300 "eth_rgmii_tx_clk", 1301 "eth_txd2_rgmii", 1302 "eth_txd3_rgmii"; 1303 function = "eth"; 1304 drive-strength-microamp = <4000>; 1305 bias-disable; 1306 }; 1307 }; 1308 1309 tdm_c_din2_z_pins: tdm-c-din2-z { 1310 mux { 1311 groups = "tdm_c_din2_z"; 1312 function = "tdm_c"; 1313 bias-disable; 1314 }; 1315 }; 1316 1317 tdm_c_din3_a_pins: tdm-c-din3-a { 1318 mux { 1319 groups = "tdm_c_din3_a"; 1320 function = "tdm_c"; 1321 bias-disable; 1322 }; 1323 }; 1324 1325 tdm_c_din3_z_pins: tdm-c-din3-z { 1326 mux { 1327 groups = "tdm_c_din3_z"; 1328 function = "tdm_c"; 1329 bias-disable; 1330 }; 1331 }; 1332 1333 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1334 mux { 1335 groups = "tdm_c_dout0_a"; 1336 function = "tdm_c"; 1337 bias-disable; 1338 drive-strength-microamp = <3000>; 1339 }; 1340 }; 1341 1342 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1343 mux { 1344 groups = "tdm_c_dout0_z"; 1345 function = "tdm_c"; 1346 bias-disable; 1347 drive-strength-microamp = <3000>; 1348 }; 1349 }; 1350 1351 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1352 mux { 1353 groups = "tdm_c_dout1_a"; 1354 function = "tdm_c"; 1355 bias-disable; 1356 drive-strength-microamp = <3000>; 1357 }; 1358 }; 1359 1360 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1361 mux { 1362 groups = "tdm_c_dout1_z"; 1363 function = "tdm_c"; 1364 bias-disable; 1365 drive-strength-microamp = <3000>; 1366 }; 1367 }; 1368 1369 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1370 mux { 1371 groups = "tdm_c_dout2_a"; 1372 function = "tdm_c"; 1373 bias-disable; 1374 drive-strength-microamp = <3000>; 1375 }; 1376 }; 1377 1378 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1379 mux { 1380 groups = "tdm_c_dout2_z"; 1381 function = "tdm_c"; 1382 bias-disable; 1383 drive-strength-microamp = <3000>; 1384 }; 1385 }; 1386 1387 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1388 mux { 1389 groups = "tdm_c_dout3_a"; 1390 function = "tdm_c"; 1391 bias-disable; 1392 drive-strength-microamp = <3000>; 1393 }; 1394 }; 1395 1396 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1397 mux { 1398 groups = "tdm_c_dout3_z"; 1399 function = "tdm_c"; 1400 bias-disable; 1401 drive-strength-microamp = <3000>; 1402 }; 1403 }; 1404 1405 tdm_c_fs_a_pins: tdm-c-fs-a { 1406 mux { 1407 groups = "tdm_c_fs_a"; 1408 function = "tdm_c"; 1409 bias-disable; 1410 drive-strength-microamp = <3000>; 1411 }; 1412 }; 1413 1414 tdm_c_fs_z_pins: tdm-c-fs-z { 1415 mux { 1416 groups = "tdm_c_fs_z"; 1417 function = "tdm_c"; 1418 bias-disable; 1419 drive-strength-microamp = <3000>; 1420 }; 1421 }; 1422 1423 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1424 mux { 1425 groups = "tdm_c_sclk_a"; 1426 function = "tdm_c"; 1427 bias-disable; 1428 drive-strength-microamp = <3000>; 1429 }; 1430 }; 1431 1432 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1433 mux { 1434 groups = "tdm_c_sclk_z"; 1435 function = "tdm_c"; 1436 bias-disable; 1437 drive-strength-microamp = <3000>; 1438 }; 1439 }; 1440 1441 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1442 mux { 1443 groups = "tdm_c_slv_fs_a"; 1444 function = "tdm_c"; 1445 bias-disable; 1446 }; 1447 }; 1448 1449 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1450 mux { 1451 groups = "tdm_c_slv_fs_z"; 1452 function = "tdm_c"; 1453 bias-disable; 1454 }; 1455 }; 1456 1457 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1458 mux { 1459 groups = "tdm_c_slv_sclk_a"; 1460 function = "tdm_c"; 1461 bias-disable; 1462 }; 1463 }; 1464 1465 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1466 mux { 1467 groups = "tdm_c_slv_sclk_z"; 1468 function = "tdm_c"; 1469 bias-disable; 1470 }; 1471 }; 1472 1473 uart_a_pins: uart-a { 1474 mux { 1475 groups = "uart_a_tx", 1476 "uart_a_rx"; 1477 function = "uart_a"; 1478 bias-disable; 1479 }; 1480 }; 1481 1482 uart_a_cts_rts_pins: uart-a-cts-rts { 1483 mux { 1484 groups = "uart_a_cts", 1485 "uart_a_rts"; 1486 function = "uart_a"; 1487 bias-disable; 1488 }; 1489 }; 1490 1491 uart_b_pins: uart-b { 1492 mux { 1493 groups = "uart_b_tx", 1494 "uart_b_rx"; 1495 function = "uart_b"; 1496 bias-disable; 1497 }; 1498 }; 1499 1500 uart_c_pins: uart-c { 1501 mux { 1502 groups = "uart_c_tx", 1503 "uart_c_rx"; 1504 function = "uart_c"; 1505 bias-disable; 1506 }; 1507 }; 1508 1509 uart_c_cts_rts_pins: uart-c-cts-rts { 1510 mux { 1511 groups = "uart_c_cts", 1512 "uart_c_rts"; 1513 function = "uart_c"; 1514 bias-disable; 1515 }; 1516 }; 1517 }; 1518 }; 1519 1520 cpu_temp: temperature-sensor@34800 { 1521 compatible = "amlogic,g12a-cpu-thermal", 1522 "amlogic,g12a-thermal"; 1523 reg = <0x0 0x34800 0x0 0x50>; 1524 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 1525 clocks = <&clkc CLKID_TS>; 1526 #thermal-sensor-cells = <0>; 1527 amlogic,ao-secure = <&sec_AO>; 1528 }; 1529 1530 ddr_temp: temperature-sensor@34c00 { 1531 compatible = "amlogic,g12a-ddr-thermal", 1532 "amlogic,g12a-thermal"; 1533 reg = <0x0 0x34c00 0x0 0x50>; 1534 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; 1535 clocks = <&clkc CLKID_TS>; 1536 #thermal-sensor-cells = <0>; 1537 amlogic,ao-secure = <&sec_AO>; 1538 }; 1539 1540 usb2_phy0: phy@36000 { 1541 compatible = "amlogic,g12a-usb2-phy"; 1542 reg = <0x0 0x36000 0x0 0x2000>; 1543 clocks = <&xtal>; 1544 clock-names = "xtal"; 1545 resets = <&reset RESET_USB_PHY20>; 1546 reset-names = "phy"; 1547 #phy-cells = <0>; 1548 }; 1549 1550 dmc: bus@38000 { 1551 compatible = "simple-bus"; 1552 reg = <0x0 0x38000 0x0 0x400>; 1553 #address-cells = <2>; 1554 #size-cells = <2>; 1555 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1556 1557 canvas: video-lut@48 { 1558 compatible = "amlogic,canvas"; 1559 reg = <0x0 0x48 0x0 0x14>; 1560 }; 1561 }; 1562 1563 usb2_phy1: phy@3a000 { 1564 compatible = "amlogic,g12a-usb2-phy"; 1565 reg = <0x0 0x3a000 0x0 0x2000>; 1566 clocks = <&xtal>; 1567 clock-names = "xtal"; 1568 resets = <&reset RESET_USB_PHY21>; 1569 reset-names = "phy"; 1570 #phy-cells = <0>; 1571 }; 1572 1573 hiu: bus@3c000 { 1574 compatible = "simple-bus"; 1575 reg = <0x0 0x3c000 0x0 0x1400>; 1576 #address-cells = <2>; 1577 #size-cells = <2>; 1578 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1579 1580 hhi: system-controller@0 { 1581 compatible = "amlogic,meson-gx-hhi-sysctrl", 1582 "simple-mfd", "syscon"; 1583 reg = <0 0 0 0x400>; 1584 1585 clkc: clock-controller { 1586 compatible = "amlogic,g12a-clkc"; 1587 #clock-cells = <1>; 1588 clocks = <&xtal>; 1589 clock-names = "xtal"; 1590 }; 1591 1592 pwrc: power-controller { 1593 compatible = "amlogic,meson-g12a-pwrc"; 1594 #power-domain-cells = <1>; 1595 amlogic,ao-sysctrl = <&rti>; 1596 resets = <&reset RESET_VIU>, 1597 <&reset RESET_VENC>, 1598 <&reset RESET_VCBUS>, 1599 <&reset RESET_BT656>, 1600 <&reset RESET_RDMA>, 1601 <&reset RESET_VENCI>, 1602 <&reset RESET_VENCP>, 1603 <&reset RESET_VDAC>, 1604 <&reset RESET_VDI6>, 1605 <&reset RESET_VENCL>, 1606 <&reset RESET_VID_LOCK>; 1607 reset-names = "viu", "venc", "vcbus", "bt656", 1608 "rdma", "venci", "vencp", "vdac", 1609 "vdi6", "vencl", "vid_lock"; 1610 clocks = <&clkc CLKID_VPU>, 1611 <&clkc CLKID_VAPB>; 1612 clock-names = "vpu", "vapb"; 1613 /* 1614 * VPU clocking is provided by two identical clock paths 1615 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1616 * free mux to safely change frequency while running. 1617 * Same for VAPB but with a final gate after the glitch free mux. 1618 */ 1619 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1620 <&clkc CLKID_VPU_0>, 1621 <&clkc CLKID_VPU>, /* Glitch free mux */ 1622 <&clkc CLKID_VAPB_0_SEL>, 1623 <&clkc CLKID_VAPB_0>, 1624 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1625 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1626 <0>, /* Do Nothing */ 1627 <&clkc CLKID_VPU_0>, 1628 <&clkc CLKID_FCLK_DIV4>, 1629 <0>, /* Do Nothing */ 1630 <&clkc CLKID_VAPB_0>; 1631 assigned-clock-rates = <0>, /* Do Nothing */ 1632 <666666666>, 1633 <0>, /* Do Nothing */ 1634 <0>, /* Do Nothing */ 1635 <250000000>, 1636 <0>; /* Do Nothing */ 1637 }; 1638 }; 1639 }; 1640 1641 usb3_pcie_phy: phy@46000 { 1642 compatible = "amlogic,g12a-usb3-pcie-phy"; 1643 reg = <0x0 0x46000 0x0 0x2000>; 1644 clocks = <&clkc CLKID_PCIE_PLL>; 1645 clock-names = "ref_clk"; 1646 resets = <&reset RESET_PCIE_PHY>; 1647 reset-names = "phy"; 1648 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1649 assigned-clock-rates = <100000000>; 1650 #phy-cells = <1>; 1651 }; 1652 1653 eth_phy: mdio-multiplexer@4c000 { 1654 compatible = "amlogic,g12a-mdio-mux"; 1655 reg = <0x0 0x4c000 0x0 0xa4>; 1656 clocks = <&clkc CLKID_ETH_PHY>, 1657 <&xtal>, 1658 <&clkc CLKID_MPLL_50M>; 1659 clock-names = "pclk", "clkin0", "clkin1"; 1660 mdio-parent-bus = <&mdio0>; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 1664 ext_mdio: mdio@0 { 1665 reg = <0>; 1666 #address-cells = <1>; 1667 #size-cells = <0>; 1668 }; 1669 1670 int_mdio: mdio@1 { 1671 reg = <1>; 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 1675 internal_ephy: ethernet_phy@8 { 1676 compatible = "ethernet-phy-id0180.3301", 1677 "ethernet-phy-ieee802.3-c22"; 1678 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1679 reg = <8>; 1680 max-speed = <100>; 1681 }; 1682 }; 1683 }; 1684 }; 1685 1686 aobus: bus@ff800000 { 1687 compatible = "simple-bus"; 1688 reg = <0x0 0xff800000 0x0 0x100000>; 1689 #address-cells = <2>; 1690 #size-cells = <2>; 1691 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1692 1693 rti: sys-ctrl@0 { 1694 compatible = "amlogic,meson-gx-ao-sysctrl", 1695 "simple-mfd", "syscon"; 1696 reg = <0x0 0x0 0x0 0x100>; 1697 #address-cells = <2>; 1698 #size-cells = <2>; 1699 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1700 1701 clkc_AO: clock-controller { 1702 compatible = "amlogic,meson-g12a-aoclkc"; 1703 #clock-cells = <1>; 1704 #reset-cells = <1>; 1705 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1706 clock-names = "xtal", "mpeg-clk"; 1707 }; 1708 1709 ao_pinctrl: pinctrl@14 { 1710 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1711 #address-cells = <2>; 1712 #size-cells = <2>; 1713 ranges; 1714 1715 gpio_ao: bank@14 { 1716 reg = <0x0 0x14 0x0 0x8>, 1717 <0x0 0x1c 0x0 0x8>, 1718 <0x0 0x24 0x0 0x14>; 1719 reg-names = "mux", 1720 "ds", 1721 "gpio"; 1722 gpio-controller; 1723 #gpio-cells = <2>; 1724 gpio-ranges = <&ao_pinctrl 0 0 15>; 1725 }; 1726 1727 i2c_ao_sck_pins: i2c_ao_sck_pins { 1728 mux { 1729 groups = "i2c_ao_sck"; 1730 function = "i2c_ao"; 1731 bias-disable; 1732 drive-strength-microamp = <3000>; 1733 }; 1734 }; 1735 1736 i2c_ao_sda_pins: i2c_ao_sda { 1737 mux { 1738 groups = "i2c_ao_sda"; 1739 function = "i2c_ao"; 1740 bias-disable; 1741 drive-strength-microamp = <3000>; 1742 }; 1743 }; 1744 1745 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1746 mux { 1747 groups = "i2c_ao_sck_e"; 1748 function = "i2c_ao"; 1749 bias-disable; 1750 drive-strength-microamp = <3000>; 1751 }; 1752 }; 1753 1754 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1755 mux { 1756 groups = "i2c_ao_sda_e"; 1757 function = "i2c_ao"; 1758 bias-disable; 1759 drive-strength-microamp = <3000>; 1760 }; 1761 }; 1762 1763 mclk0_ao_pins: mclk0-ao { 1764 mux { 1765 groups = "mclk0_ao"; 1766 function = "mclk0_ao"; 1767 bias-disable; 1768 drive-strength-microamp = <3000>; 1769 }; 1770 }; 1771 1772 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1773 mux { 1774 groups = "tdm_ao_b_din0"; 1775 function = "tdm_ao_b"; 1776 bias-disable; 1777 }; 1778 }; 1779 1780 spdif_ao_out_pins: spdif-ao-out { 1781 mux { 1782 groups = "spdif_ao_out"; 1783 function = "spdif_ao_out"; 1784 drive-strength-microamp = <500>; 1785 bias-disable; 1786 }; 1787 }; 1788 1789 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1790 mux { 1791 groups = "tdm_ao_b_din1"; 1792 function = "tdm_ao_b"; 1793 bias-disable; 1794 }; 1795 }; 1796 1797 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1798 mux { 1799 groups = "tdm_ao_b_din2"; 1800 function = "tdm_ao_b"; 1801 bias-disable; 1802 }; 1803 }; 1804 1805 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1806 mux { 1807 groups = "tdm_ao_b_dout0"; 1808 function = "tdm_ao_b"; 1809 bias-disable; 1810 drive-strength-microamp = <3000>; 1811 }; 1812 }; 1813 1814 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1815 mux { 1816 groups = "tdm_ao_b_dout1"; 1817 function = "tdm_ao_b"; 1818 bias-disable; 1819 drive-strength-microamp = <3000>; 1820 }; 1821 }; 1822 1823 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1824 mux { 1825 groups = "tdm_ao_b_dout2"; 1826 function = "tdm_ao_b"; 1827 bias-disable; 1828 drive-strength-microamp = <3000>; 1829 }; 1830 }; 1831 1832 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1833 mux { 1834 groups = "tdm_ao_b_fs"; 1835 function = "tdm_ao_b"; 1836 bias-disable; 1837 drive-strength-microamp = <3000>; 1838 }; 1839 }; 1840 1841 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1842 mux { 1843 groups = "tdm_ao_b_sclk"; 1844 function = "tdm_ao_b"; 1845 bias-disable; 1846 drive-strength-microamp = <3000>; 1847 }; 1848 }; 1849 1850 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1851 mux { 1852 groups = "tdm_ao_b_slv_fs"; 1853 function = "tdm_ao_b"; 1854 bias-disable; 1855 }; 1856 }; 1857 1858 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1859 mux { 1860 groups = "tdm_ao_b_slv_sclk"; 1861 function = "tdm_ao_b"; 1862 bias-disable; 1863 }; 1864 }; 1865 1866 uart_ao_a_pins: uart-a-ao { 1867 mux { 1868 groups = "uart_ao_a_tx", 1869 "uart_ao_a_rx"; 1870 function = "uart_ao_a"; 1871 bias-disable; 1872 }; 1873 }; 1874 1875 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1876 mux { 1877 groups = "uart_ao_a_cts", 1878 "uart_ao_a_rts"; 1879 function = "uart_ao_a"; 1880 bias-disable; 1881 }; 1882 }; 1883 1884 pwm_a_e_pins: pwm-a-e { 1885 mux { 1886 groups = "pwm_a_e"; 1887 function = "pwm_a_e"; 1888 bias-disable; 1889 }; 1890 }; 1891 1892 pwm_ao_a_pins: pwm-ao-a { 1893 mux { 1894 groups = "pwm_ao_a"; 1895 function = "pwm_ao_a"; 1896 bias-disable; 1897 }; 1898 }; 1899 1900 pwm_ao_b_pins: pwm-ao-b { 1901 mux { 1902 groups = "pwm_ao_b"; 1903 function = "pwm_ao_b"; 1904 bias-disable; 1905 }; 1906 }; 1907 1908 pwm_ao_c_4_pins: pwm-ao-c-4 { 1909 mux { 1910 groups = "pwm_ao_c_4"; 1911 function = "pwm_ao_c"; 1912 bias-disable; 1913 }; 1914 }; 1915 1916 pwm_ao_c_6_pins: pwm-ao-c-6 { 1917 mux { 1918 groups = "pwm_ao_c_6"; 1919 function = "pwm_ao_c"; 1920 bias-disable; 1921 }; 1922 }; 1923 1924 pwm_ao_d_5_pins: pwm-ao-d-5 { 1925 mux { 1926 groups = "pwm_ao_d_5"; 1927 function = "pwm_ao_d"; 1928 bias-disable; 1929 }; 1930 }; 1931 1932 pwm_ao_d_10_pins: pwm-ao-d-10 { 1933 mux { 1934 groups = "pwm_ao_d_10"; 1935 function = "pwm_ao_d"; 1936 bias-disable; 1937 }; 1938 }; 1939 1940 pwm_ao_d_e_pins: pwm-ao-d-e { 1941 mux { 1942 groups = "pwm_ao_d_e"; 1943 function = "pwm_ao_d"; 1944 }; 1945 }; 1946 1947 remote_input_ao_pins: remote-input-ao { 1948 mux { 1949 groups = "remote_ao_input"; 1950 function = "remote_ao_input"; 1951 bias-disable; 1952 }; 1953 }; 1954 }; 1955 }; 1956 1957 vrtc: rtc@a8 { 1958 compatible = "amlogic,meson-vrtc"; 1959 reg = <0x0 0x000a8 0x0 0x4>; 1960 }; 1961 1962 cec_AO: cec@100 { 1963 compatible = "amlogic,meson-gx-ao-cec"; 1964 reg = <0x0 0x00100 0x0 0x14>; 1965 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 1966 clocks = <&clkc_AO CLKID_AO_CEC>; 1967 clock-names = "core"; 1968 status = "disabled"; 1969 }; 1970 1971 sec_AO: ao-secure@140 { 1972 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1973 reg = <0x0 0x140 0x0 0x140>; 1974 amlogic,has-chip-id; 1975 }; 1976 1977 cecb_AO: cec@280 { 1978 compatible = "amlogic,meson-g12a-ao-cec"; 1979 reg = <0x0 0x00280 0x0 0x1c>; 1980 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 1981 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 1982 clock-names = "oscin"; 1983 status = "disabled"; 1984 }; 1985 1986 pwm_AO_cd: pwm@2000 { 1987 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 1988 reg = <0x0 0x2000 0x0 0x20>; 1989 #pwm-cells = <3>; 1990 status = "disabled"; 1991 }; 1992 1993 uart_AO: serial@3000 { 1994 compatible = "amlogic,meson-gx-uart", 1995 "amlogic,meson-ao-uart"; 1996 reg = <0x0 0x3000 0x0 0x18>; 1997 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1998 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 1999 clock-names = "xtal", "pclk", "baud"; 2000 status = "disabled"; 2001 }; 2002 2003 uart_AO_B: serial@4000 { 2004 compatible = "amlogic,meson-gx-uart", 2005 "amlogic,meson-ao-uart"; 2006 reg = <0x0 0x4000 0x0 0x18>; 2007 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2008 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2009 clock-names = "xtal", "pclk", "baud"; 2010 status = "disabled"; 2011 }; 2012 2013 i2c_AO: i2c@5000 { 2014 compatible = "amlogic,meson-axg-i2c"; 2015 status = "disabled"; 2016 reg = <0x0 0x05000 0x0 0x20>; 2017 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2018 #address-cells = <1>; 2019 #size-cells = <0>; 2020 clocks = <&clkc CLKID_I2C>; 2021 }; 2022 2023 pwm_AO_ab: pwm@7000 { 2024 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2025 reg = <0x0 0x7000 0x0 0x20>; 2026 #pwm-cells = <3>; 2027 status = "disabled"; 2028 }; 2029 2030 ir: ir@8000 { 2031 compatible = "amlogic,meson-gxbb-ir"; 2032 reg = <0x0 0x8000 0x0 0x20>; 2033 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2034 status = "disabled"; 2035 }; 2036 2037 saradc: adc@9000 { 2038 compatible = "amlogic,meson-g12a-saradc", 2039 "amlogic,meson-saradc"; 2040 reg = <0x0 0x9000 0x0 0x48>; 2041 #io-channel-cells = <1>; 2042 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2043 clocks = <&xtal>, 2044 <&clkc_AO CLKID_AO_SAR_ADC>, 2045 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2046 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2047 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2048 status = "disabled"; 2049 }; 2050 }; 2051 2052 vdec: video-decoder@ff620000 { 2053 compatible = "amlogic,g12a-vdec"; 2054 reg = <0x0 0xff620000 0x0 0x10000>, 2055 <0x0 0xffd0e180 0x0 0xe4>; 2056 reg-names = "dos", "esparser"; 2057 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 2058 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 2059 interrupt-names = "vdec", "esparser"; 2060 2061 amlogic,ao-sysctrl = <&rti>; 2062 amlogic,canvas = <&canvas>; 2063 2064 clocks = <&clkc CLKID_PARSER>, 2065 <&clkc CLKID_DOS>, 2066 <&clkc CLKID_VDEC_1>, 2067 <&clkc CLKID_VDEC_HEVC>, 2068 <&clkc CLKID_VDEC_HEVCF>; 2069 clock-names = "dos_parser", "dos", "vdec_1", 2070 "vdec_hevc", "vdec_hevcf"; 2071 resets = <&reset RESET_PARSER>; 2072 reset-names = "esparser"; 2073 }; 2074 2075 vpu: vpu@ff900000 { 2076 compatible = "amlogic,meson-g12a-vpu"; 2077 reg = <0x0 0xff900000 0x0 0x100000>, 2078 <0x0 0xff63c000 0x0 0x1000>; 2079 reg-names = "vpu", "hhi"; 2080 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2081 #address-cells = <1>; 2082 #size-cells = <0>; 2083 amlogic,canvas = <&canvas>; 2084 2085 /* CVBS VDAC output port */ 2086 cvbs_vdac_port: port@0 { 2087 reg = <0>; 2088 }; 2089 2090 /* HDMI-TX output port */ 2091 hdmi_tx_port: port@1 { 2092 reg = <1>; 2093 2094 hdmi_tx_out: endpoint { 2095 remote-endpoint = <&hdmi_tx_in>; 2096 }; 2097 }; 2098 }; 2099 2100 gic: interrupt-controller@ffc01000 { 2101 compatible = "arm,gic-400"; 2102 reg = <0x0 0xffc01000 0 0x1000>, 2103 <0x0 0xffc02000 0 0x2000>, 2104 <0x0 0xffc04000 0 0x2000>, 2105 <0x0 0xffc06000 0 0x2000>; 2106 interrupt-controller; 2107 interrupts = <GIC_PPI 9 2108 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2109 #interrupt-cells = <3>; 2110 #address-cells = <0>; 2111 }; 2112 2113 cbus: bus@ffd00000 { 2114 compatible = "simple-bus"; 2115 reg = <0x0 0xffd00000 0x0 0x100000>; 2116 #address-cells = <2>; 2117 #size-cells = <2>; 2118 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2119 2120 reset: reset-controller@1004 { 2121 compatible = "amlogic,meson-axg-reset"; 2122 reg = <0x0 0x1004 0x0 0x9c>; 2123 #reset-cells = <1>; 2124 }; 2125 2126 gpio_intc: interrupt-controller@f080 { 2127 compatible = "amlogic,meson-g12a-gpio-intc", 2128 "amlogic,meson-gpio-intc"; 2129 reg = <0x0 0xf080 0x0 0x10>; 2130 interrupt-controller; 2131 #interrupt-cells = <2>; 2132 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2133 }; 2134 2135 watchdog: watchdog@f0d0 { 2136 compatible = "amlogic,meson-gxbb-wdt"; 2137 reg = <0x0 0xf0d0 0x0 0x10>; 2138 clocks = <&xtal>; 2139 }; 2140 2141 spicc0: spi@13000 { 2142 compatible = "amlogic,meson-g12a-spicc"; 2143 reg = <0x0 0x13000 0x0 0x44>; 2144 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2145 clocks = <&clkc CLKID_SPICC0>, 2146 <&clkc CLKID_SPICC0_SCLK>; 2147 clock-names = "core", "pclk"; 2148 #address-cells = <1>; 2149 #size-cells = <0>; 2150 status = "disabled"; 2151 }; 2152 2153 spicc1: spi@15000 { 2154 compatible = "amlogic,meson-g12a-spicc"; 2155 reg = <0x0 0x15000 0x0 0x44>; 2156 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2157 clocks = <&clkc CLKID_SPICC1>, 2158 <&clkc CLKID_SPICC1_SCLK>; 2159 clock-names = "core", "pclk"; 2160 #address-cells = <1>; 2161 #size-cells = <0>; 2162 status = "disabled"; 2163 }; 2164 2165 spifc: spi@14000 { 2166 compatible = "amlogic,meson-gxbb-spifc"; 2167 status = "disabled"; 2168 reg = <0x0 0x14000 0x0 0x80>; 2169 #address-cells = <1>; 2170 #size-cells = <0>; 2171 clocks = <&clkc CLKID_CLK81>; 2172 }; 2173 2174 pwm_ef: pwm@19000 { 2175 compatible = "amlogic,meson-g12a-ee-pwm"; 2176 reg = <0x0 0x19000 0x0 0x20>; 2177 #pwm-cells = <3>; 2178 status = "disabled"; 2179 }; 2180 2181 pwm_cd: pwm@1a000 { 2182 compatible = "amlogic,meson-g12a-ee-pwm"; 2183 reg = <0x0 0x1a000 0x0 0x20>; 2184 #pwm-cells = <3>; 2185 status = "disabled"; 2186 }; 2187 2188 pwm_ab: pwm@1b000 { 2189 compatible = "amlogic,meson-g12a-ee-pwm"; 2190 reg = <0x0 0x1b000 0x0 0x20>; 2191 #pwm-cells = <3>; 2192 status = "disabled"; 2193 }; 2194 2195 i2c3: i2c@1c000 { 2196 compatible = "amlogic,meson-axg-i2c"; 2197 status = "disabled"; 2198 reg = <0x0 0x1c000 0x0 0x20>; 2199 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2200 #address-cells = <1>; 2201 #size-cells = <0>; 2202 clocks = <&clkc CLKID_I2C>; 2203 }; 2204 2205 i2c2: i2c@1d000 { 2206 compatible = "amlogic,meson-axg-i2c"; 2207 status = "disabled"; 2208 reg = <0x0 0x1d000 0x0 0x20>; 2209 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2210 #address-cells = <1>; 2211 #size-cells = <0>; 2212 clocks = <&clkc CLKID_I2C>; 2213 }; 2214 2215 i2c1: i2c@1e000 { 2216 compatible = "amlogic,meson-axg-i2c"; 2217 status = "disabled"; 2218 reg = <0x0 0x1e000 0x0 0x20>; 2219 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2220 #address-cells = <1>; 2221 #size-cells = <0>; 2222 clocks = <&clkc CLKID_I2C>; 2223 }; 2224 2225 i2c0: i2c@1f000 { 2226 compatible = "amlogic,meson-axg-i2c"; 2227 status = "disabled"; 2228 reg = <0x0 0x1f000 0x0 0x20>; 2229 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2230 #address-cells = <1>; 2231 #size-cells = <0>; 2232 clocks = <&clkc CLKID_I2C>; 2233 }; 2234 2235 clk_msr: clock-measure@18000 { 2236 compatible = "amlogic,meson-g12a-clk-measure"; 2237 reg = <0x0 0x18000 0x0 0x10>; 2238 }; 2239 2240 uart_C: serial@22000 { 2241 compatible = "amlogic,meson-gx-uart"; 2242 reg = <0x0 0x22000 0x0 0x18>; 2243 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2244 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2245 clock-names = "xtal", "pclk", "baud"; 2246 status = "disabled"; 2247 }; 2248 2249 uart_B: serial@23000 { 2250 compatible = "amlogic,meson-gx-uart"; 2251 reg = <0x0 0x23000 0x0 0x18>; 2252 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2253 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2254 clock-names = "xtal", "pclk", "baud"; 2255 status = "disabled"; 2256 }; 2257 2258 uart_A: serial@24000 { 2259 compatible = "amlogic,meson-gx-uart"; 2260 reg = <0x0 0x24000 0x0 0x18>; 2261 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2262 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2263 clock-names = "xtal", "pclk", "baud"; 2264 status = "disabled"; 2265 fifo-size = <128>; 2266 }; 2267 }; 2268 2269 sd_emmc_a: sd@ffe03000 { 2270 compatible = "amlogic,meson-axg-mmc"; 2271 reg = <0x0 0xffe03000 0x0 0x800>; 2272 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; 2273 status = "disabled"; 2274 clocks = <&clkc CLKID_SD_EMMC_A>, 2275 <&clkc CLKID_SD_EMMC_A_CLK0>, 2276 <&clkc CLKID_FCLK_DIV2>; 2277 clock-names = "core", "clkin0", "clkin1"; 2278 resets = <&reset RESET_SD_EMMC_A>; 2279 }; 2280 2281 sd_emmc_b: sd@ffe05000 { 2282 compatible = "amlogic,meson-axg-mmc"; 2283 reg = <0x0 0xffe05000 0x0 0x800>; 2284 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2285 status = "disabled"; 2286 clocks = <&clkc CLKID_SD_EMMC_B>, 2287 <&clkc CLKID_SD_EMMC_B_CLK0>, 2288 <&clkc CLKID_FCLK_DIV2>; 2289 clock-names = "core", "clkin0", "clkin1"; 2290 resets = <&reset RESET_SD_EMMC_B>; 2291 }; 2292 2293 sd_emmc_c: mmc@ffe07000 { 2294 compatible = "amlogic,meson-axg-mmc"; 2295 reg = <0x0 0xffe07000 0x0 0x800>; 2296 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2297 status = "disabled"; 2298 clocks = <&clkc CLKID_SD_EMMC_C>, 2299 <&clkc CLKID_SD_EMMC_C_CLK0>, 2300 <&clkc CLKID_FCLK_DIV2>; 2301 clock-names = "core", "clkin0", "clkin1"; 2302 resets = <&reset RESET_SD_EMMC_C>; 2303 }; 2304 2305 usb: usb@ffe09000 { 2306 status = "disabled"; 2307 compatible = "amlogic,meson-g12a-usb-ctrl"; 2308 reg = <0x0 0xffe09000 0x0 0xa0>; 2309 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2310 #address-cells = <2>; 2311 #size-cells = <2>; 2312 ranges; 2313 2314 clocks = <&clkc CLKID_USB>; 2315 resets = <&reset RESET_USB>; 2316 2317 dr_mode = "otg"; 2318 2319 phys = <&usb2_phy0>, <&usb2_phy1>, 2320 <&usb3_pcie_phy PHY_TYPE_USB3>; 2321 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2322 2323 dwc2: usb@ff400000 { 2324 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2325 reg = <0x0 0xff400000 0x0 0x40000>; 2326 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2327 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2328 clock-names = "otg"; 2329 phys = <&usb2_phy1>; 2330 phy-names = "usb2-phy"; 2331 dr_mode = "peripheral"; 2332 g-rx-fifo-size = <192>; 2333 g-np-tx-fifo-size = <128>; 2334 g-tx-fifo-size = <128 128 16 16 16>; 2335 }; 2336 2337 dwc3: usb@ff500000 { 2338 compatible = "snps,dwc3"; 2339 reg = <0x0 0xff500000 0x0 0x100000>; 2340 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2341 dr_mode = "host"; 2342 snps,dis_u2_susphy_quirk; 2343 snps,quirk-frame-length-adjustment = <0x20>; 2344 snps,parkmode-disable-ss-quirk; 2345 }; 2346 }; 2347 2348 mali: gpu@ffe40000 { 2349 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2350 reg = <0x0 0xffe40000 0x0 0x40000>; 2351 interrupt-parent = <&gic>; 2352 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2353 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2354 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2355 interrupt-names = "job", "mmu", "gpu"; 2356 clocks = <&clkc CLKID_MALI>; 2357 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2358 operating-points-v2 = <&gpu_opp_table>; 2359 #cooling-cells = <2>; 2360 }; 2361 }; 2362 2363 thermal-zones { 2364 cpu_thermal: cpu-thermal { 2365 polling-delay = <1000>; 2366 polling-delay-passive = <100>; 2367 thermal-sensors = <&cpu_temp>; 2368 2369 trips { 2370 cpu_passive: cpu-passive { 2371 temperature = <85000>; /* millicelsius */ 2372 hysteresis = <2000>; /* millicelsius */ 2373 type = "passive"; 2374 }; 2375 2376 cpu_hot: cpu-hot { 2377 temperature = <95000>; /* millicelsius */ 2378 hysteresis = <2000>; /* millicelsius */ 2379 type = "hot"; 2380 }; 2381 2382 cpu_critical: cpu-critical { 2383 temperature = <110000>; /* millicelsius */ 2384 hysteresis = <2000>; /* millicelsius */ 2385 type = "critical"; 2386 }; 2387 }; 2388 }; 2389 2390 ddr_thermal: ddr-thermal { 2391 polling-delay = <1000>; 2392 polling-delay-passive = <100>; 2393 thermal-sensors = <&ddr_temp>; 2394 2395 trips { 2396 ddr_passive: ddr-passive { 2397 temperature = <85000>; /* millicelsius */ 2398 hysteresis = <2000>; /* millicelsius */ 2399 type = "passive"; 2400 }; 2401 2402 ddr_critical: ddr-critical { 2403 temperature = <110000>; /* millicelsius */ 2404 hysteresis = <2000>; /* millicelsius */ 2405 type = "critical"; 2406 }; 2407 }; 2408 2409 cooling-maps { 2410 map { 2411 trip = <&ddr_passive>; 2412 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2413 }; 2414 }; 2415 }; 2416 }; 2417 2418 timer { 2419 compatible = "arm,armv8-timer"; 2420 interrupts = <GIC_PPI 13 2421 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2422 <GIC_PPI 14 2423 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2424 <GIC_PPI 11 2425 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2426 <GIC_PPI 10 2427 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2428 arm,no-tick-in-suspend; 2429 }; 2430 2431 xtal: xtal-clk { 2432 compatible = "fixed-clock"; 2433 clock-frequency = <24000000>; 2434 clock-output-names = "xtal"; 2435 #clock-cells = <0>; 2436 }; 2437 2438}; 2439