1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h> 15#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 tdmif_a: audio-controller-0 { 23 compatible = "amlogic,axg-tdm-iface"; 24 #sound-dai-cells = <0>; 25 sound-name-prefix = "TDM_A"; 26 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 27 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 29 clock-names = "mclk", "sclk", "lrclk"; 30 status = "disabled"; 31 }; 32 33 tdmif_b: audio-controller-1 { 34 compatible = "amlogic,axg-tdm-iface"; 35 #sound-dai-cells = <0>; 36 sound-name-prefix = "TDM_B"; 37 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 38 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 40 clock-names = "mclk", "sclk", "lrclk"; 41 status = "disabled"; 42 }; 43 44 tdmif_c: audio-controller-2 { 45 compatible = "amlogic,axg-tdm-iface"; 46 #sound-dai-cells = <0>; 47 sound-name-prefix = "TDM_C"; 48 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 49 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 51 clock-names = "mclk", "sclk", "lrclk"; 52 status = "disabled"; 53 }; 54 55 efuse: efuse { 56 compatible = "amlogic,meson-gxbb-efuse"; 57 clocks = <&clkc CLKID_EFUSE>; 58 #address-cells = <1>; 59 #size-cells = <1>; 60 read-only; 61 }; 62 63 psci { 64 compatible = "arm,psci-1.0"; 65 method = "smc"; 66 }; 67 68 reserved-memory { 69 #address-cells = <2>; 70 #size-cells = <2>; 71 ranges; 72 73 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 74 secmon_reserved: secmon@5000000 { 75 reg = <0x0 0x05000000 0x0 0x300000>; 76 no-map; 77 }; 78 79 linux,cma { 80 compatible = "shared-dma-pool"; 81 reusable; 82 size = <0x0 0x10000000>; 83 alignment = <0x0 0x400000>; 84 linux,cma-default; 85 }; 86 }; 87 88 sm: secure-monitor { 89 compatible = "amlogic,meson-gxbb-sm"; 90 }; 91 92 soc { 93 compatible = "simple-bus"; 94 #address-cells = <2>; 95 #size-cells = <2>; 96 ranges; 97 98 ethmac: ethernet@ff3f0000 { 99 compatible = "amlogic,meson-axg-dwmac", 100 "snps,dwmac-3.70a", 101 "snps,dwmac"; 102 reg = <0x0 0xff3f0000 0x0 0x10000>, 103 <0x0 0xff634540 0x0 0x8>; 104 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 105 interrupt-names = "macirq"; 106 clocks = <&clkc CLKID_ETH>, 107 <&clkc CLKID_FCLK_DIV2>, 108 <&clkc CLKID_MPLL2>; 109 clock-names = "stmmaceth", "clkin0", "clkin1"; 110 rx-fifo-depth = <4096>; 111 tx-fifo-depth = <2048>; 112 status = "disabled"; 113 114 mdio0: mdio { 115 #address-cells = <1>; 116 #size-cells = <0>; 117 compatible = "snps,dwmac-mdio"; 118 }; 119 }; 120 121 apb: bus@ff600000 { 122 compatible = "simple-bus"; 123 reg = <0x0 0xff600000 0x0 0x200000>; 124 #address-cells = <2>; 125 #size-cells = <2>; 126 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 127 128 hdmi_tx: hdmi-tx@0 { 129 compatible = "amlogic,meson-g12a-dw-hdmi"; 130 reg = <0x0 0x0 0x0 0x10000>; 131 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 132 resets = <&reset RESET_HDMITX_CAPB3>, 133 <&reset RESET_HDMITX_PHY>, 134 <&reset RESET_HDMITX>; 135 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 136 clocks = <&clkc CLKID_HDMI>, 137 <&clkc CLKID_HTX_PCLK>, 138 <&clkc CLKID_VPU_INTR>; 139 clock-names = "isfr", "iahb", "venci"; 140 #address-cells = <1>; 141 #size-cells = <0>; 142 #sound-dai-cells = <0>; 143 status = "disabled"; 144 145 /* VPU VENC Input */ 146 hdmi_tx_venc_port: port@0 { 147 reg = <0>; 148 149 hdmi_tx_in: endpoint { 150 remote-endpoint = <&hdmi_tx_out>; 151 }; 152 }; 153 154 /* TMDS Output */ 155 hdmi_tx_tmds_port: port@1 { 156 reg = <1>; 157 }; 158 }; 159 160 apb_efuse: bus@30000 { 161 compatible = "simple-bus"; 162 reg = <0x0 0x30000 0x0 0x2000>; 163 #address-cells = <2>; 164 #size-cells = <2>; 165 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 166 167 hwrng: rng@218 { 168 compatible = "amlogic,meson-rng"; 169 reg = <0x0 0x218 0x0 0x4>; 170 }; 171 }; 172 173 periphs: bus@34400 { 174 compatible = "simple-bus"; 175 reg = <0x0 0x34400 0x0 0x400>; 176 #address-cells = <2>; 177 #size-cells = <2>; 178 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 179 180 periphs_pinctrl: pinctrl@40 { 181 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 182 #address-cells = <2>; 183 #size-cells = <2>; 184 ranges; 185 186 gpio: bank@40 { 187 reg = <0x0 0x40 0x0 0x4c>, 188 <0x0 0xe8 0x0 0x18>, 189 <0x0 0x120 0x0 0x18>, 190 <0x0 0x2c0 0x0 0x40>, 191 <0x0 0x340 0x0 0x1c>; 192 reg-names = "gpio", 193 "pull", 194 "pull-enable", 195 "mux", 196 "ds"; 197 gpio-controller; 198 #gpio-cells = <2>; 199 gpio-ranges = <&periphs_pinctrl 0 0 86>; 200 }; 201 202 cec_ao_a_h_pins: cec_ao_a_h { 203 mux { 204 groups = "cec_ao_a_h"; 205 function = "cec_ao_a_h"; 206 bias-disable; 207 }; 208 }; 209 210 cec_ao_b_h_pins: cec_ao_b_h { 211 mux { 212 groups = "cec_ao_b_h"; 213 function = "cec_ao_b_h"; 214 bias-disable; 215 }; 216 }; 217 218 emmc_pins: emmc { 219 mux-0 { 220 groups = "emmc_nand_d0", 221 "emmc_nand_d1", 222 "emmc_nand_d2", 223 "emmc_nand_d3", 224 "emmc_nand_d4", 225 "emmc_nand_d5", 226 "emmc_nand_d6", 227 "emmc_nand_d7", 228 "emmc_cmd"; 229 function = "emmc"; 230 bias-pull-up; 231 drive-strength-microamp = <4000>; 232 }; 233 234 mux-1 { 235 groups = "emmc_clk"; 236 function = "emmc"; 237 bias-disable; 238 drive-strength-microamp = <4000>; 239 }; 240 }; 241 242 emmc_ds_pins: emmc-ds { 243 mux { 244 groups = "emmc_nand_ds"; 245 function = "emmc"; 246 bias-pull-down; 247 drive-strength-microamp = <4000>; 248 }; 249 }; 250 251 emmc_clk_gate_pins: emmc_clk_gate { 252 mux { 253 groups = "BOOT_8"; 254 function = "gpio_periphs"; 255 bias-pull-down; 256 drive-strength-microamp = <4000>; 257 }; 258 }; 259 260 hdmitx_ddc_pins: hdmitx_ddc { 261 mux { 262 groups = "hdmitx_sda", 263 "hdmitx_sck"; 264 function = "hdmitx"; 265 bias-disable; 266 drive-strength-microamp = <4000>; 267 }; 268 }; 269 270 hdmitx_hpd_pins: hdmitx_hpd { 271 mux { 272 groups = "hdmitx_hpd_in"; 273 function = "hdmitx"; 274 bias-disable; 275 }; 276 }; 277 278 279 i2c0_sda_c_pins: i2c0-sda-c { 280 mux { 281 groups = "i2c0_sda_c"; 282 function = "i2c0"; 283 bias-disable; 284 drive-strength-microamp = <3000>; 285 286 }; 287 }; 288 289 i2c0_sck_c_pins: i2c0-sck-c { 290 mux { 291 groups = "i2c0_sck_c"; 292 function = "i2c0"; 293 bias-disable; 294 drive-strength-microamp = <3000>; 295 }; 296 }; 297 298 i2c0_sda_z0_pins: i2c0-sda-z0 { 299 mux { 300 groups = "i2c0_sda_z0"; 301 function = "i2c0"; 302 bias-disable; 303 drive-strength-microamp = <3000>; 304 }; 305 }; 306 307 i2c0_sck_z1_pins: i2c0-sck-z1 { 308 mux { 309 groups = "i2c0_sck_z1"; 310 function = "i2c0"; 311 bias-disable; 312 drive-strength-microamp = <3000>; 313 }; 314 }; 315 316 i2c0_sda_z7_pins: i2c0-sda-z7 { 317 mux { 318 groups = "i2c0_sda_z7"; 319 function = "i2c0"; 320 bias-disable; 321 drive-strength-microamp = <3000>; 322 }; 323 }; 324 325 i2c0_sda_z8_pins: i2c0-sda-z8 { 326 mux { 327 groups = "i2c0_sda_z8"; 328 function = "i2c0"; 329 bias-disable; 330 drive-strength-microamp = <3000>; 331 }; 332 }; 333 334 i2c1_sda_x_pins: i2c1-sda-x { 335 mux { 336 groups = "i2c1_sda_x"; 337 function = "i2c1"; 338 bias-disable; 339 drive-strength-microamp = <3000>; 340 }; 341 }; 342 343 i2c1_sck_x_pins: i2c1-sck-x { 344 mux { 345 groups = "i2c1_sck_x"; 346 function = "i2c1"; 347 bias-disable; 348 drive-strength-microamp = <3000>; 349 }; 350 }; 351 352 i2c1_sda_h2_pins: i2c1-sda-h2 { 353 mux { 354 groups = "i2c1_sda_h2"; 355 function = "i2c1"; 356 bias-disable; 357 drive-strength-microamp = <3000>; 358 }; 359 }; 360 361 i2c1_sck_h3_pins: i2c1-sck-h3 { 362 mux { 363 groups = "i2c1_sck_h3"; 364 function = "i2c1"; 365 bias-disable; 366 drive-strength-microamp = <3000>; 367 }; 368 }; 369 370 i2c1_sda_h6_pins: i2c1-sda-h6 { 371 mux { 372 groups = "i2c1_sda_h6"; 373 function = "i2c1"; 374 bias-disable; 375 drive-strength-microamp = <3000>; 376 }; 377 }; 378 379 i2c1_sck_h7_pins: i2c1-sck-h7 { 380 mux { 381 groups = "i2c1_sck_h7"; 382 function = "i2c1"; 383 bias-disable; 384 drive-strength-microamp = <3000>; 385 }; 386 }; 387 388 i2c2_sda_x_pins: i2c2-sda-x { 389 mux { 390 groups = "i2c2_sda_x"; 391 function = "i2c2"; 392 bias-disable; 393 drive-strength-microamp = <3000>; 394 }; 395 }; 396 397 i2c2_sck_x_pins: i2c2-sck-x { 398 mux { 399 groups = "i2c2_sck_x"; 400 function = "i2c2"; 401 bias-disable; 402 drive-strength-microamp = <3000>; 403 }; 404 }; 405 406 i2c2_sda_z_pins: i2c2-sda-z { 407 mux { 408 groups = "i2c2_sda_z"; 409 function = "i2c2"; 410 bias-disable; 411 drive-strength-microamp = <3000>; 412 }; 413 }; 414 415 i2c2_sck_z_pins: i2c2-sck-z { 416 mux { 417 groups = "i2c2_sck_z"; 418 function = "i2c2"; 419 bias-disable; 420 drive-strength-microamp = <3000>; 421 }; 422 }; 423 424 i2c3_sda_h_pins: i2c3-sda-h { 425 mux { 426 groups = "i2c3_sda_h"; 427 function = "i2c3"; 428 bias-disable; 429 drive-strength-microamp = <3000>; 430 }; 431 }; 432 433 i2c3_sck_h_pins: i2c3-sck-h { 434 mux { 435 groups = "i2c3_sck_h"; 436 function = "i2c3"; 437 bias-disable; 438 drive-strength-microamp = <3000>; 439 }; 440 }; 441 442 i2c3_sda_a_pins: i2c3-sda-a { 443 mux { 444 groups = "i2c3_sda_a"; 445 function = "i2c3"; 446 bias-disable; 447 drive-strength-microamp = <3000>; 448 }; 449 }; 450 451 i2c3_sck_a_pins: i2c3-sck-a { 452 mux { 453 groups = "i2c3_sck_a"; 454 function = "i2c3"; 455 bias-disable; 456 drive-strength-microamp = <3000>; 457 }; 458 }; 459 460 mclk0_a_pins: mclk0-a { 461 mux { 462 groups = "mclk0_a"; 463 function = "mclk0"; 464 bias-disable; 465 drive-strength-microamp = <3000>; 466 }; 467 }; 468 469 mclk1_a_pins: mclk1-a { 470 mux { 471 groups = "mclk1_a"; 472 function = "mclk1"; 473 bias-disable; 474 drive-strength-microamp = <3000>; 475 }; 476 }; 477 478 mclk1_x_pins: mclk1-x { 479 mux { 480 groups = "mclk1_x"; 481 function = "mclk1"; 482 bias-disable; 483 drive-strength-microamp = <3000>; 484 }; 485 }; 486 487 mclk1_z_pins: mclk1-z { 488 mux { 489 groups = "mclk1_z"; 490 function = "mclk1"; 491 bias-disable; 492 drive-strength-microamp = <3000>; 493 }; 494 }; 495 496 pdm_din0_a_pins: pdm-din0-a { 497 mux { 498 groups = "pdm_din0_a"; 499 function = "pdm"; 500 bias-disable; 501 }; 502 }; 503 504 pdm_din0_c_pins: pdm-din0-c { 505 mux { 506 groups = "pdm_din0_c"; 507 function = "pdm"; 508 bias-disable; 509 }; 510 }; 511 512 pdm_din0_x_pins: pdm-din0-x { 513 mux { 514 groups = "pdm_din0_x"; 515 function = "pdm"; 516 bias-disable; 517 }; 518 }; 519 520 pdm_din0_z_pins: pdm-din0-z { 521 mux { 522 groups = "pdm_din0_z"; 523 function = "pdm"; 524 bias-disable; 525 }; 526 }; 527 528 pdm_din1_a_pins: pdm-din1-a { 529 mux { 530 groups = "pdm_din1_a"; 531 function = "pdm"; 532 bias-disable; 533 }; 534 }; 535 536 pdm_din1_c_pins: pdm-din1-c { 537 mux { 538 groups = "pdm_din1_c"; 539 function = "pdm"; 540 bias-disable; 541 }; 542 }; 543 544 pdm_din1_x_pins: pdm-din1-x { 545 mux { 546 groups = "pdm_din1_x"; 547 function = "pdm"; 548 bias-disable; 549 }; 550 }; 551 552 pdm_din1_z_pins: pdm-din1-z { 553 mux { 554 groups = "pdm_din1_z"; 555 function = "pdm"; 556 bias-disable; 557 }; 558 }; 559 560 pdm_din2_a_pins: pdm-din2-a { 561 mux { 562 groups = "pdm_din2_a"; 563 function = "pdm"; 564 bias-disable; 565 }; 566 }; 567 568 pdm_din2_c_pins: pdm-din2-c { 569 mux { 570 groups = "pdm_din2_c"; 571 function = "pdm"; 572 bias-disable; 573 }; 574 }; 575 576 pdm_din2_x_pins: pdm-din2-x { 577 mux { 578 groups = "pdm_din2_x"; 579 function = "pdm"; 580 bias-disable; 581 }; 582 }; 583 584 pdm_din2_z_pins: pdm-din2-z { 585 mux { 586 groups = "pdm_din2_z"; 587 function = "pdm"; 588 bias-disable; 589 }; 590 }; 591 592 pdm_din3_a_pins: pdm-din3-a { 593 mux { 594 groups = "pdm_din3_a"; 595 function = "pdm"; 596 bias-disable; 597 }; 598 }; 599 600 pdm_din3_c_pins: pdm-din3-c { 601 mux { 602 groups = "pdm_din3_c"; 603 function = "pdm"; 604 bias-disable; 605 }; 606 }; 607 608 pdm_din3_x_pins: pdm-din3-x { 609 mux { 610 groups = "pdm_din3_x"; 611 function = "pdm"; 612 bias-disable; 613 }; 614 }; 615 616 pdm_din3_z_pins: pdm-din3-z { 617 mux { 618 groups = "pdm_din3_z"; 619 function = "pdm"; 620 bias-disable; 621 }; 622 }; 623 624 pdm_dclk_a_pins: pdm-dclk-a { 625 mux { 626 groups = "pdm_dclk_a"; 627 function = "pdm"; 628 bias-disable; 629 drive-strength-microamp = <500>; 630 }; 631 }; 632 633 pdm_dclk_c_pins: pdm-dclk-c { 634 mux { 635 groups = "pdm_dclk_c"; 636 function = "pdm"; 637 bias-disable; 638 drive-strength-microamp = <500>; 639 }; 640 }; 641 642 pdm_dclk_x_pins: pdm-dclk-x { 643 mux { 644 groups = "pdm_dclk_x"; 645 function = "pdm"; 646 bias-disable; 647 drive-strength-microamp = <500>; 648 }; 649 }; 650 651 pdm_dclk_z_pins: pdm-dclk-z { 652 mux { 653 groups = "pdm_dclk_z"; 654 function = "pdm"; 655 bias-disable; 656 drive-strength-microamp = <500>; 657 }; 658 }; 659 660 pwm_a_pins: pwm-a { 661 mux { 662 groups = "pwm_a"; 663 function = "pwm_a"; 664 bias-disable; 665 }; 666 }; 667 668 pwm_b_x7_pins: pwm-b-x7 { 669 mux { 670 groups = "pwm_b_x7"; 671 function = "pwm_b"; 672 bias-disable; 673 }; 674 }; 675 676 pwm_b_x19_pins: pwm-b-x19 { 677 mux { 678 groups = "pwm_b_x19"; 679 function = "pwm_b"; 680 bias-disable; 681 }; 682 }; 683 684 pwm_c_c_pins: pwm-c-c { 685 mux { 686 groups = "pwm_c_c"; 687 function = "pwm_c"; 688 bias-disable; 689 }; 690 }; 691 692 pwm_c_x5_pins: pwm-c-x5 { 693 mux { 694 groups = "pwm_c_x5"; 695 function = "pwm_c"; 696 bias-disable; 697 }; 698 }; 699 700 pwm_c_x8_pins: pwm-c-x8 { 701 mux { 702 groups = "pwm_c_x8"; 703 function = "pwm_c"; 704 bias-disable; 705 }; 706 }; 707 708 pwm_d_x3_pins: pwm-d-x3 { 709 mux { 710 groups = "pwm_d_x3"; 711 function = "pwm_d"; 712 bias-disable; 713 }; 714 }; 715 716 pwm_d_x6_pins: pwm-d-x6 { 717 mux { 718 groups = "pwm_d_x6"; 719 function = "pwm_d"; 720 bias-disable; 721 }; 722 }; 723 724 pwm_e_pins: pwm-e { 725 mux { 726 groups = "pwm_e"; 727 function = "pwm_e"; 728 bias-disable; 729 }; 730 }; 731 732 pwm_f_x_pins: pwm-f-x { 733 mux { 734 groups = "pwm_f_x"; 735 function = "pwm_f"; 736 bias-disable; 737 }; 738 }; 739 740 pwm_f_h_pins: pwm-f-h { 741 mux { 742 groups = "pwm_f_h"; 743 function = "pwm_f"; 744 bias-disable; 745 }; 746 }; 747 748 sdcard_c_pins: sdcard_c { 749 mux-0 { 750 groups = "sdcard_d0_c", 751 "sdcard_d1_c", 752 "sdcard_d2_c", 753 "sdcard_d3_c", 754 "sdcard_cmd_c"; 755 function = "sdcard"; 756 bias-pull-up; 757 drive-strength-microamp = <4000>; 758 }; 759 760 mux-1 { 761 groups = "sdcard_clk_c"; 762 function = "sdcard"; 763 bias-disable; 764 drive-strength-microamp = <4000>; 765 }; 766 }; 767 768 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 769 mux { 770 groups = "GPIOC_4"; 771 function = "gpio_periphs"; 772 bias-pull-down; 773 drive-strength-microamp = <4000>; 774 }; 775 }; 776 777 sdcard_z_pins: sdcard_z { 778 mux-0 { 779 groups = "sdcard_d0_z", 780 "sdcard_d1_z", 781 "sdcard_d2_z", 782 "sdcard_d3_z", 783 "sdcard_cmd_z"; 784 function = "sdcard"; 785 bias-pull-up; 786 drive-strength-microamp = <4000>; 787 }; 788 789 mux-1 { 790 groups = "sdcard_clk_z"; 791 function = "sdcard"; 792 bias-disable; 793 drive-strength-microamp = <4000>; 794 }; 795 }; 796 797 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 798 mux { 799 groups = "GPIOZ_6"; 800 function = "gpio_periphs"; 801 bias-pull-down; 802 drive-strength-microamp = <4000>; 803 }; 804 }; 805 806 sdio_pins: sdio { 807 mux { 808 groups = "sdio_d0", 809 "sdio_d1", 810 "sdio_d2", 811 "sdio_d3", 812 "sdio_clk", 813 "sdio_cmd"; 814 function = "sdio"; 815 bias-disable; 816 drive-strength-microamp = <4000>; 817 }; 818 }; 819 820 sdio_clk_gate_pins: sdio_clk_gate { 821 mux { 822 groups = "GPIOX_4"; 823 function = "gpio_periphs"; 824 bias-pull-down; 825 drive-strength-microamp = <4000>; 826 }; 827 }; 828 829 spdif_in_a10_pins: spdif-in-a10 { 830 mux { 831 groups = "spdif_in_a10"; 832 function = "spdif_in"; 833 bias-disable; 834 }; 835 }; 836 837 spdif_in_a12_pins: spdif-in-a12 { 838 mux { 839 groups = "spdif_in_a12"; 840 function = "spdif_in"; 841 bias-disable; 842 }; 843 }; 844 845 spdif_in_h_pins: spdif-in-h { 846 mux { 847 groups = "spdif_in_h"; 848 function = "spdif_in"; 849 bias-disable; 850 }; 851 }; 852 853 spdif_out_h_pins: spdif-out-h { 854 mux { 855 groups = "spdif_out_h"; 856 function = "spdif_out"; 857 drive-strength-microamp = <500>; 858 bias-disable; 859 }; 860 }; 861 862 spdif_out_a11_pins: spdif-out-a11 { 863 mux { 864 groups = "spdif_out_a11"; 865 function = "spdif_out"; 866 drive-strength-microamp = <500>; 867 bias-disable; 868 }; 869 }; 870 871 spdif_out_a13_pins: spdif-out-a13 { 872 mux { 873 groups = "spdif_out_a13"; 874 function = "spdif_out"; 875 drive-strength-microamp = <500>; 876 bias-disable; 877 }; 878 }; 879 880 tdm_a_din0_pins: tdm-a-din0 { 881 mux { 882 groups = "tdm_a_din0"; 883 function = "tdm_a"; 884 bias-disable; 885 }; 886 }; 887 888 889 tdm_a_din1_pins: tdm-a-din1 { 890 mux { 891 groups = "tdm_a_din1"; 892 function = "tdm_a"; 893 bias-disable; 894 }; 895 }; 896 897 tdm_a_dout0_pins: tdm-a-dout0 { 898 mux { 899 groups = "tdm_a_dout0"; 900 function = "tdm_a"; 901 bias-disable; 902 drive-strength-microamp = <3000>; 903 }; 904 }; 905 906 tdm_a_dout1_pins: tdm-a-dout1 { 907 mux { 908 groups = "tdm_a_dout1"; 909 function = "tdm_a"; 910 bias-disable; 911 drive-strength-microamp = <3000>; 912 }; 913 }; 914 915 tdm_a_fs_pins: tdm-a-fs { 916 mux { 917 groups = "tdm_a_fs"; 918 function = "tdm_a"; 919 bias-disable; 920 drive-strength-microamp = <3000>; 921 }; 922 }; 923 924 tdm_a_sclk_pins: tdm-a-sclk { 925 mux { 926 groups = "tdm_a_sclk"; 927 function = "tdm_a"; 928 bias-disable; 929 drive-strength-microamp = <3000>; 930 }; 931 }; 932 933 tdm_a_slv_fs_pins: tdm-a-slv-fs { 934 mux { 935 groups = "tdm_a_slv_fs"; 936 function = "tdm_a"; 937 bias-disable; 938 }; 939 }; 940 941 942 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 943 mux { 944 groups = "tdm_a_slv_sclk"; 945 function = "tdm_a"; 946 bias-disable; 947 }; 948 }; 949 950 tdm_b_din0_pins: tdm-b-din0 { 951 mux { 952 groups = "tdm_b_din0"; 953 function = "tdm_b"; 954 bias-disable; 955 }; 956 }; 957 958 tdm_b_din1_pins: tdm-b-din1 { 959 mux { 960 groups = "tdm_b_din1"; 961 function = "tdm_b"; 962 bias-disable; 963 }; 964 }; 965 966 tdm_b_din2_pins: tdm-b-din2 { 967 mux { 968 groups = "tdm_b_din2"; 969 function = "tdm_b"; 970 bias-disable; 971 }; 972 }; 973 974 tdm_b_din3_a_pins: tdm-b-din3-a { 975 mux { 976 groups = "tdm_b_din3_a"; 977 function = "tdm_b"; 978 bias-disable; 979 }; 980 }; 981 982 tdm_b_din3_h_pins: tdm-b-din3-h { 983 mux { 984 groups = "tdm_b_din3_h"; 985 function = "tdm_b"; 986 bias-disable; 987 }; 988 }; 989 990 tdm_b_dout0_pins: tdm-b-dout0 { 991 mux { 992 groups = "tdm_b_dout0"; 993 function = "tdm_b"; 994 bias-disable; 995 drive-strength-microamp = <3000>; 996 }; 997 }; 998 999 tdm_b_dout1_pins: tdm-b-dout1 { 1000 mux { 1001 groups = "tdm_b_dout1"; 1002 function = "tdm_b"; 1003 bias-disable; 1004 drive-strength-microamp = <3000>; 1005 }; 1006 }; 1007 1008 tdm_b_dout2_pins: tdm-b-dout2 { 1009 mux { 1010 groups = "tdm_b_dout2"; 1011 function = "tdm_b"; 1012 bias-disable; 1013 drive-strength-microamp = <3000>; 1014 }; 1015 }; 1016 1017 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1018 mux { 1019 groups = "tdm_b_dout3_a"; 1020 function = "tdm_b"; 1021 bias-disable; 1022 drive-strength-microamp = <3000>; 1023 }; 1024 }; 1025 1026 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1027 mux { 1028 groups = "tdm_b_dout3_h"; 1029 function = "tdm_b"; 1030 bias-disable; 1031 drive-strength-microamp = <3000>; 1032 }; 1033 }; 1034 1035 tdm_b_fs_pins: tdm-b-fs { 1036 mux { 1037 groups = "tdm_b_fs"; 1038 function = "tdm_b"; 1039 bias-disable; 1040 drive-strength-microamp = <3000>; 1041 }; 1042 }; 1043 1044 tdm_b_sclk_pins: tdm-b-sclk { 1045 mux { 1046 groups = "tdm_b_sclk"; 1047 function = "tdm_b"; 1048 bias-disable; 1049 drive-strength-microamp = <3000>; 1050 }; 1051 }; 1052 1053 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1054 mux { 1055 groups = "tdm_b_slv_fs"; 1056 function = "tdm_b"; 1057 bias-disable; 1058 }; 1059 }; 1060 1061 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1062 mux { 1063 groups = "tdm_b_slv_sclk"; 1064 function = "tdm_b"; 1065 bias-disable; 1066 }; 1067 }; 1068 1069 tdm_c_din0_a_pins: tdm-c-din0-a { 1070 mux { 1071 groups = "tdm_c_din0_a"; 1072 function = "tdm_c"; 1073 bias-disable; 1074 }; 1075 }; 1076 1077 tdm_c_din0_z_pins: tdm-c-din0-z { 1078 mux { 1079 groups = "tdm_c_din0_z"; 1080 function = "tdm_c"; 1081 bias-disable; 1082 }; 1083 }; 1084 1085 tdm_c_din1_a_pins: tdm-c-din1-a { 1086 mux { 1087 groups = "tdm_c_din1_a"; 1088 function = "tdm_c"; 1089 bias-disable; 1090 }; 1091 }; 1092 1093 tdm_c_din1_z_pins: tdm-c-din1-z { 1094 mux { 1095 groups = "tdm_c_din1_z"; 1096 function = "tdm_c"; 1097 bias-disable; 1098 }; 1099 }; 1100 1101 tdm_c_din2_a_pins: tdm-c-din2-a { 1102 mux { 1103 groups = "tdm_c_din2_a"; 1104 function = "tdm_c"; 1105 bias-disable; 1106 }; 1107 }; 1108 1109 eth_leds_pins: eth-leds { 1110 mux { 1111 groups = "eth_link_led", 1112 "eth_act_led"; 1113 function = "eth"; 1114 bias-disable; 1115 }; 1116 }; 1117 1118 eth_pins: eth { 1119 mux { 1120 groups = "eth_mdio", 1121 "eth_mdc", 1122 "eth_rgmii_rx_clk", 1123 "eth_rx_dv", 1124 "eth_rxd0", 1125 "eth_rxd1", 1126 "eth_txen", 1127 "eth_txd0", 1128 "eth_txd1"; 1129 function = "eth"; 1130 drive-strength-microamp = <4000>; 1131 bias-disable; 1132 }; 1133 }; 1134 1135 eth_rgmii_pins: eth-rgmii { 1136 mux { 1137 groups = "eth_rxd2_rgmii", 1138 "eth_rxd3_rgmii", 1139 "eth_rgmii_tx_clk", 1140 "eth_txd2_rgmii", 1141 "eth_txd3_rgmii"; 1142 function = "eth"; 1143 drive-strength-microamp = <4000>; 1144 bias-disable; 1145 }; 1146 }; 1147 1148 tdm_c_din2_z_pins: tdm-c-din2-z { 1149 mux { 1150 groups = "tdm_c_din2_z"; 1151 function = "tdm_c"; 1152 bias-disable; 1153 }; 1154 }; 1155 1156 tdm_c_din3_a_pins: tdm-c-din3-a { 1157 mux { 1158 groups = "tdm_c_din3_a"; 1159 function = "tdm_c"; 1160 bias-disable; 1161 }; 1162 }; 1163 1164 tdm_c_din3_z_pins: tdm-c-din3-z { 1165 mux { 1166 groups = "tdm_c_din3_z"; 1167 function = "tdm_c"; 1168 bias-disable; 1169 }; 1170 }; 1171 1172 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1173 mux { 1174 groups = "tdm_c_dout0_a"; 1175 function = "tdm_c"; 1176 bias-disable; 1177 drive-strength-microamp = <3000>; 1178 }; 1179 }; 1180 1181 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1182 mux { 1183 groups = "tdm_c_dout0_z"; 1184 function = "tdm_c"; 1185 bias-disable; 1186 drive-strength-microamp = <3000>; 1187 }; 1188 }; 1189 1190 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1191 mux { 1192 groups = "tdm_c_dout1_a"; 1193 function = "tdm_c"; 1194 bias-disable; 1195 drive-strength-microamp = <3000>; 1196 }; 1197 }; 1198 1199 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1200 mux { 1201 groups = "tdm_c_dout1_z"; 1202 function = "tdm_c"; 1203 bias-disable; 1204 drive-strength-microamp = <3000>; 1205 }; 1206 }; 1207 1208 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1209 mux { 1210 groups = "tdm_c_dout2_a"; 1211 function = "tdm_c"; 1212 bias-disable; 1213 drive-strength-microamp = <3000>; 1214 }; 1215 }; 1216 1217 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1218 mux { 1219 groups = "tdm_c_dout2_z"; 1220 function = "tdm_c"; 1221 bias-disable; 1222 drive-strength-microamp = <3000>; 1223 }; 1224 }; 1225 1226 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1227 mux { 1228 groups = "tdm_c_dout3_a"; 1229 function = "tdm_c"; 1230 bias-disable; 1231 drive-strength-microamp = <3000>; 1232 }; 1233 }; 1234 1235 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1236 mux { 1237 groups = "tdm_c_dout3_z"; 1238 function = "tdm_c"; 1239 bias-disable; 1240 drive-strength-microamp = <3000>; 1241 }; 1242 }; 1243 1244 tdm_c_fs_a_pins: tdm-c-fs-a { 1245 mux { 1246 groups = "tdm_c_fs_a"; 1247 function = "tdm_c"; 1248 bias-disable; 1249 drive-strength-microamp = <3000>; 1250 }; 1251 }; 1252 1253 tdm_c_fs_z_pins: tdm-c-fs-z { 1254 mux { 1255 groups = "tdm_c_fs_z"; 1256 function = "tdm_c"; 1257 bias-disable; 1258 drive-strength-microamp = <3000>; 1259 }; 1260 }; 1261 1262 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1263 mux { 1264 groups = "tdm_c_sclk_a"; 1265 function = "tdm_c"; 1266 bias-disable; 1267 drive-strength-microamp = <3000>; 1268 }; 1269 }; 1270 1271 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1272 mux { 1273 groups = "tdm_c_sclk_z"; 1274 function = "tdm_c"; 1275 bias-disable; 1276 drive-strength-microamp = <3000>; 1277 }; 1278 }; 1279 1280 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1281 mux { 1282 groups = "tdm_c_slv_fs_a"; 1283 function = "tdm_c"; 1284 bias-disable; 1285 }; 1286 }; 1287 1288 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1289 mux { 1290 groups = "tdm_c_slv_fs_z"; 1291 function = "tdm_c"; 1292 bias-disable; 1293 }; 1294 }; 1295 1296 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1297 mux { 1298 groups = "tdm_c_slv_sclk_a"; 1299 function = "tdm_c"; 1300 bias-disable; 1301 }; 1302 }; 1303 1304 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1305 mux { 1306 groups = "tdm_c_slv_sclk_z"; 1307 function = "tdm_c"; 1308 bias-disable; 1309 }; 1310 }; 1311 1312 uart_a_pins: uart-a { 1313 mux { 1314 groups = "uart_a_tx", 1315 "uart_a_rx"; 1316 function = "uart_a"; 1317 bias-disable; 1318 }; 1319 }; 1320 1321 uart_a_cts_rts_pins: uart-a-cts-rts { 1322 mux { 1323 groups = "uart_a_cts", 1324 "uart_a_rts"; 1325 function = "uart_a"; 1326 bias-disable; 1327 }; 1328 }; 1329 1330 uart_b_pins: uart-b { 1331 mux { 1332 groups = "uart_b_tx", 1333 "uart_b_rx"; 1334 function = "uart_b"; 1335 bias-disable; 1336 }; 1337 }; 1338 1339 uart_c_pins: uart-c { 1340 mux { 1341 groups = "uart_c_tx", 1342 "uart_c_rx"; 1343 function = "uart_c"; 1344 bias-disable; 1345 }; 1346 }; 1347 1348 uart_c_cts_rts_pins: uart-c-cts-rts { 1349 mux { 1350 groups = "uart_c_cts", 1351 "uart_c_rts"; 1352 function = "uart_c"; 1353 bias-disable; 1354 }; 1355 }; 1356 }; 1357 }; 1358 1359 usb2_phy0: phy@36000 { 1360 compatible = "amlogic,g12a-usb2-phy"; 1361 reg = <0x0 0x36000 0x0 0x2000>; 1362 clocks = <&xtal>; 1363 clock-names = "xtal"; 1364 resets = <&reset RESET_USB_PHY20>; 1365 reset-names = "phy"; 1366 #phy-cells = <0>; 1367 }; 1368 1369 dmc: bus@38000 { 1370 compatible = "simple-bus"; 1371 reg = <0x0 0x38000 0x0 0x400>; 1372 #address-cells = <2>; 1373 #size-cells = <2>; 1374 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1375 1376 canvas: video-lut@48 { 1377 compatible = "amlogic,canvas"; 1378 reg = <0x0 0x48 0x0 0x14>; 1379 }; 1380 }; 1381 1382 usb2_phy1: phy@3a000 { 1383 compatible = "amlogic,g12a-usb2-phy"; 1384 reg = <0x0 0x3a000 0x0 0x2000>; 1385 clocks = <&xtal>; 1386 clock-names = "xtal"; 1387 resets = <&reset RESET_USB_PHY21>; 1388 reset-names = "phy"; 1389 #phy-cells = <0>; 1390 }; 1391 1392 hiu: bus@3c000 { 1393 compatible = "simple-bus"; 1394 reg = <0x0 0x3c000 0x0 0x1400>; 1395 #address-cells = <2>; 1396 #size-cells = <2>; 1397 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1398 1399 hhi: system-controller@0 { 1400 compatible = "amlogic,meson-gx-hhi-sysctrl", 1401 "simple-mfd", "syscon"; 1402 reg = <0 0 0 0x400>; 1403 1404 clkc: clock-controller { 1405 compatible = "amlogic,g12a-clkc"; 1406 #clock-cells = <1>; 1407 clocks = <&xtal>; 1408 clock-names = "xtal"; 1409 }; 1410 1411 pwrc: power-controller { 1412 compatible = "amlogic,meson-g12a-pwrc"; 1413 #power-domain-cells = <1>; 1414 amlogic,ao-sysctrl = <&rti>; 1415 resets = <&reset RESET_VIU>, 1416 <&reset RESET_VENC>, 1417 <&reset RESET_VCBUS>, 1418 <&reset RESET_BT656>, 1419 <&reset RESET_RDMA>, 1420 <&reset RESET_VENCI>, 1421 <&reset RESET_VENCP>, 1422 <&reset RESET_VDAC>, 1423 <&reset RESET_VDI6>, 1424 <&reset RESET_VENCL>, 1425 <&reset RESET_VID_LOCK>; 1426 reset-names = "viu", "venc", "vcbus", "bt656", 1427 "rdma", "venci", "vencp", "vdac", 1428 "vdi6", "vencl", "vid_lock"; 1429 clocks = <&clkc CLKID_VPU>, 1430 <&clkc CLKID_VAPB>; 1431 clock-names = "vpu", "vapb"; 1432 /* 1433 * VPU clocking is provided by two identical clock paths 1434 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1435 * free mux to safely change frequency while running. 1436 * Same for VAPB but with a final gate after the glitch free mux. 1437 */ 1438 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1439 <&clkc CLKID_VPU_0>, 1440 <&clkc CLKID_VPU>, /* Glitch free mux */ 1441 <&clkc CLKID_VAPB_0_SEL>, 1442 <&clkc CLKID_VAPB_0>, 1443 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1444 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1445 <0>, /* Do Nothing */ 1446 <&clkc CLKID_VPU_0>, 1447 <&clkc CLKID_FCLK_DIV4>, 1448 <0>, /* Do Nothing */ 1449 <&clkc CLKID_VAPB_0>; 1450 assigned-clock-rates = <0>, /* Do Nothing */ 1451 <666666666>, 1452 <0>, /* Do Nothing */ 1453 <0>, /* Do Nothing */ 1454 <250000000>, 1455 <0>; /* Do Nothing */ 1456 }; 1457 }; 1458 }; 1459 1460 pdm: audio-controller@40000 { 1461 compatible = "amlogic,g12a-pdm", 1462 "amlogic,axg-pdm"; 1463 reg = <0x0 0x40000 0x0 0x34>; 1464 #sound-dai-cells = <0>; 1465 sound-name-prefix = "PDM"; 1466 clocks = <&clkc_audio AUD_CLKID_PDM>, 1467 <&clkc_audio AUD_CLKID_PDM_DCLK>, 1468 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 1469 clock-names = "pclk", "dclk", "sysclk"; 1470 status = "disabled"; 1471 }; 1472 1473 audio: bus@42000 { 1474 compatible = "simple-bus"; 1475 reg = <0x0 0x42000 0x0 0x2000>; 1476 #address-cells = <2>; 1477 #size-cells = <2>; 1478 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1479 1480 clkc_audio: clock-controller@0 { 1481 status = "disabled"; 1482 compatible = "amlogic,g12a-audio-clkc"; 1483 reg = <0x0 0x0 0x0 0xb4>; 1484 #clock-cells = <1>; 1485 #reset-cells = <1>; 1486 1487 clocks = <&clkc CLKID_AUDIO>, 1488 <&clkc CLKID_MPLL0>, 1489 <&clkc CLKID_MPLL1>, 1490 <&clkc CLKID_MPLL2>, 1491 <&clkc CLKID_MPLL3>, 1492 <&clkc CLKID_HIFI_PLL>, 1493 <&clkc CLKID_FCLK_DIV3>, 1494 <&clkc CLKID_FCLK_DIV4>, 1495 <&clkc CLKID_GP0_PLL>; 1496 clock-names = "pclk", 1497 "mst_in0", 1498 "mst_in1", 1499 "mst_in2", 1500 "mst_in3", 1501 "mst_in4", 1502 "mst_in5", 1503 "mst_in6", 1504 "mst_in7"; 1505 1506 resets = <&reset RESET_AUDIO>; 1507 }; 1508 1509 toddr_a: audio-controller@100 { 1510 compatible = "amlogic,g12a-toddr", 1511 "amlogic,axg-toddr"; 1512 reg = <0x0 0x100 0x0 0x1c>; 1513 #sound-dai-cells = <0>; 1514 sound-name-prefix = "TODDR_A"; 1515 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1516 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1517 resets = <&arb AXG_ARB_TODDR_A>; 1518 status = "disabled"; 1519 }; 1520 1521 toddr_b: audio-controller@140 { 1522 compatible = "amlogic,g12a-toddr", 1523 "amlogic,axg-toddr"; 1524 reg = <0x0 0x140 0x0 0x1c>; 1525 #sound-dai-cells = <0>; 1526 sound-name-prefix = "TODDR_B"; 1527 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1528 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1529 resets = <&arb AXG_ARB_TODDR_B>; 1530 status = "disabled"; 1531 }; 1532 1533 toddr_c: audio-controller@180 { 1534 compatible = "amlogic,g12a-toddr", 1535 "amlogic,axg-toddr"; 1536 reg = <0x0 0x180 0x0 0x1c>; 1537 #sound-dai-cells = <0>; 1538 sound-name-prefix = "TODDR_C"; 1539 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1540 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1541 resets = <&arb AXG_ARB_TODDR_C>; 1542 status = "disabled"; 1543 }; 1544 1545 frddr_a: audio-controller@1c0 { 1546 compatible = "amlogic,g12a-frddr", 1547 "amlogic,axg-frddr"; 1548 reg = <0x0 0x1c0 0x0 0x1c>; 1549 #sound-dai-cells = <0>; 1550 sound-name-prefix = "FRDDR_A"; 1551 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1552 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1553 resets = <&arb AXG_ARB_FRDDR_A>; 1554 status = "disabled"; 1555 }; 1556 1557 frddr_b: audio-controller@200 { 1558 compatible = "amlogic,g12a-frddr", 1559 "amlogic,axg-frddr"; 1560 reg = <0x0 0x200 0x0 0x1c>; 1561 #sound-dai-cells = <0>; 1562 sound-name-prefix = "FRDDR_B"; 1563 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1564 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1565 resets = <&arb AXG_ARB_FRDDR_B>; 1566 status = "disabled"; 1567 }; 1568 1569 frddr_c: audio-controller@240 { 1570 compatible = "amlogic,g12a-frddr", 1571 "amlogic,axg-frddr"; 1572 reg = <0x0 0x240 0x0 0x1c>; 1573 #sound-dai-cells = <0>; 1574 sound-name-prefix = "FRDDR_C"; 1575 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1576 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1577 resets = <&arb AXG_ARB_FRDDR_C>; 1578 status = "disabled"; 1579 }; 1580 1581 arb: reset-controller@280 { 1582 status = "disabled"; 1583 compatible = "amlogic,meson-axg-audio-arb"; 1584 reg = <0x0 0x280 0x0 0x4>; 1585 #reset-cells = <1>; 1586 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1587 }; 1588 1589 tdmin_a: audio-controller@300 { 1590 compatible = "amlogic,g12a-tdmin", 1591 "amlogic,axg-tdmin"; 1592 reg = <0x0 0x300 0x0 0x40>; 1593 sound-name-prefix = "TDMIN_A"; 1594 resets = <&clkc_audio AUD_RESET_TDMIN_A>; 1595 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1596 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1597 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1598 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1599 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1600 clock-names = "pclk", "sclk", "sclk_sel", 1601 "lrclk", "lrclk_sel"; 1602 status = "disabled"; 1603 }; 1604 1605 tdmin_b: audio-controller@340 { 1606 compatible = "amlogic,g12a-tdmin", 1607 "amlogic,axg-tdmin"; 1608 reg = <0x0 0x340 0x0 0x40>; 1609 sound-name-prefix = "TDMIN_B"; 1610 resets = <&clkc_audio AUD_RESET_TDMIN_B>; 1611 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1612 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1613 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1614 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1615 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1616 clock-names = "pclk", "sclk", "sclk_sel", 1617 "lrclk", "lrclk_sel"; 1618 status = "disabled"; 1619 }; 1620 1621 tdmin_c: audio-controller@380 { 1622 compatible = "amlogic,g12a-tdmin", 1623 "amlogic,axg-tdmin"; 1624 reg = <0x0 0x380 0x0 0x40>; 1625 sound-name-prefix = "TDMIN_C"; 1626 resets = <&clkc_audio AUD_RESET_TDMIN_C>; 1627 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1628 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1629 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1630 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1631 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1632 clock-names = "pclk", "sclk", "sclk_sel", 1633 "lrclk", "lrclk_sel"; 1634 status = "disabled"; 1635 }; 1636 1637 tdmin_lb: audio-controller@3c0 { 1638 compatible = "amlogic,g12a-tdmin", 1639 "amlogic,axg-tdmin"; 1640 reg = <0x0 0x3c0 0x0 0x40>; 1641 sound-name-prefix = "TDMIN_LB"; 1642 resets = <&clkc_audio AUD_RESET_TDMIN_LB>; 1643 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1644 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1645 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1646 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1647 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1648 clock-names = "pclk", "sclk", "sclk_sel", 1649 "lrclk", "lrclk_sel"; 1650 status = "disabled"; 1651 }; 1652 1653 spdifin: audio-controller@400 { 1654 compatible = "amlogic,g12a-spdifin", 1655 "amlogic,axg-spdifin"; 1656 reg = <0x0 0x400 0x0 0x30>; 1657 #sound-dai-cells = <0>; 1658 sound-name-prefix = "SPDIFIN"; 1659 interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 1660 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1661 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1662 clock-names = "pclk", "refclk"; 1663 status = "disabled"; 1664 }; 1665 1666 spdifout: audio-controller@480 { 1667 compatible = "amlogic,g12a-spdifout", 1668 "amlogic,axg-spdifout"; 1669 reg = <0x0 0x480 0x0 0x50>; 1670 #sound-dai-cells = <0>; 1671 sound-name-prefix = "SPDIFOUT"; 1672 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1673 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1674 clock-names = "pclk", "mclk"; 1675 status = "disabled"; 1676 }; 1677 1678 tdmout_a: audio-controller@500 { 1679 compatible = "amlogic,g12a-tdmout"; 1680 reg = <0x0 0x500 0x0 0x40>; 1681 sound-name-prefix = "TDMOUT_A"; 1682 resets = <&clkc_audio AUD_RESET_TDMOUT_A>; 1683 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1684 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1685 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1686 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1687 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1688 clock-names = "pclk", "sclk", "sclk_sel", 1689 "lrclk", "lrclk_sel"; 1690 status = "disabled"; 1691 }; 1692 1693 tdmout_b: audio-controller@540 { 1694 compatible = "amlogic,g12a-tdmout"; 1695 reg = <0x0 0x540 0x0 0x40>; 1696 sound-name-prefix = "TDMOUT_B"; 1697 resets = <&clkc_audio AUD_RESET_TDMOUT_B>; 1698 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1699 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1700 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1701 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1702 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1703 clock-names = "pclk", "sclk", "sclk_sel", 1704 "lrclk", "lrclk_sel"; 1705 status = "disabled"; 1706 }; 1707 1708 tdmout_c: audio-controller@580 { 1709 compatible = "amlogic,g12a-tdmout"; 1710 reg = <0x0 0x580 0x0 0x40>; 1711 sound-name-prefix = "TDMOUT_C"; 1712 resets = <&clkc_audio AUD_RESET_TDMOUT_C>; 1713 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1714 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1715 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1716 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1717 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1718 clock-names = "pclk", "sclk", "sclk_sel", 1719 "lrclk", "lrclk_sel"; 1720 status = "disabled"; 1721 }; 1722 1723 spdifout_b: audio-controller@680 { 1724 compatible = "amlogic,g12a-spdifout", 1725 "amlogic,axg-spdifout"; 1726 reg = <0x0 0x680 0x0 0x50>; 1727 #sound-dai-cells = <0>; 1728 sound-name-prefix = "SPDIFOUT_B"; 1729 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1730 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1731 clock-names = "pclk", "mclk"; 1732 status = "disabled"; 1733 }; 1734 1735 tohdmitx: audio-controller@744 { 1736 compatible = "amlogic,g12a-tohdmitx"; 1737 reg = <0x0 0x744 0x0 0x4>; 1738 #sound-dai-cells = <1>; 1739 sound-name-prefix = "TOHDMITX"; 1740 status = "disabled"; 1741 }; 1742 }; 1743 1744 usb3_pcie_phy: phy@46000 { 1745 compatible = "amlogic,g12a-usb3-pcie-phy"; 1746 reg = <0x0 0x46000 0x0 0x2000>; 1747 clocks = <&clkc CLKID_PCIE_PLL>; 1748 clock-names = "ref_clk"; 1749 resets = <&reset RESET_PCIE_PHY>; 1750 reset-names = "phy"; 1751 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1752 assigned-clock-rates = <100000000>; 1753 #phy-cells = <1>; 1754 }; 1755 1756 eth_phy: mdio-multiplexer@4c000 { 1757 compatible = "amlogic,g12a-mdio-mux"; 1758 reg = <0x0 0x4c000 0x0 0xa4>; 1759 clocks = <&clkc CLKID_ETH_PHY>, 1760 <&xtal>, 1761 <&clkc CLKID_MPLL_50M>; 1762 clock-names = "pclk", "clkin0", "clkin1"; 1763 mdio-parent-bus = <&mdio0>; 1764 #address-cells = <1>; 1765 #size-cells = <0>; 1766 1767 ext_mdio: mdio@0 { 1768 reg = <0>; 1769 #address-cells = <1>; 1770 #size-cells = <0>; 1771 }; 1772 1773 int_mdio: mdio@1 { 1774 reg = <1>; 1775 #address-cells = <1>; 1776 #size-cells = <0>; 1777 1778 internal_ephy: ethernet_phy@8 { 1779 compatible = "ethernet-phy-id0180.3301", 1780 "ethernet-phy-ieee802.3-c22"; 1781 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1782 reg = <8>; 1783 max-speed = <100>; 1784 }; 1785 }; 1786 }; 1787 }; 1788 1789 aobus: bus@ff800000 { 1790 compatible = "simple-bus"; 1791 reg = <0x0 0xff800000 0x0 0x100000>; 1792 #address-cells = <2>; 1793 #size-cells = <2>; 1794 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1795 1796 rti: sys-ctrl@0 { 1797 compatible = "amlogic,meson-gx-ao-sysctrl", 1798 "simple-mfd", "syscon"; 1799 reg = <0x0 0x0 0x0 0x100>; 1800 #address-cells = <2>; 1801 #size-cells = <2>; 1802 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1803 1804 clkc_AO: clock-controller { 1805 compatible = "amlogic,meson-g12a-aoclkc"; 1806 #clock-cells = <1>; 1807 #reset-cells = <1>; 1808 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1809 clock-names = "xtal", "mpeg-clk"; 1810 }; 1811 1812 ao_pinctrl: pinctrl@14 { 1813 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1814 #address-cells = <2>; 1815 #size-cells = <2>; 1816 ranges; 1817 1818 gpio_ao: bank@14 { 1819 reg = <0x0 0x14 0x0 0x8>, 1820 <0x0 0x1c 0x0 0x8>, 1821 <0x0 0x24 0x0 0x14>; 1822 reg-names = "mux", 1823 "ds", 1824 "gpio"; 1825 gpio-controller; 1826 #gpio-cells = <2>; 1827 gpio-ranges = <&ao_pinctrl 0 0 15>; 1828 }; 1829 1830 i2c_ao_sck_pins: i2c_ao_sck_pins { 1831 mux { 1832 groups = "i2c_ao_sck"; 1833 function = "i2c_ao"; 1834 bias-disable; 1835 drive-strength-microamp = <3000>; 1836 }; 1837 }; 1838 1839 i2c_ao_sda_pins: i2c_ao_sda { 1840 mux { 1841 groups = "i2c_ao_sda"; 1842 function = "i2c_ao"; 1843 bias-disable; 1844 drive-strength-microamp = <3000>; 1845 }; 1846 }; 1847 1848 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1849 mux { 1850 groups = "i2c_ao_sck_e"; 1851 function = "i2c_ao"; 1852 bias-disable; 1853 drive-strength-microamp = <3000>; 1854 }; 1855 }; 1856 1857 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1858 mux { 1859 groups = "i2c_ao_sda_e"; 1860 function = "i2c_ao"; 1861 bias-disable; 1862 drive-strength-microamp = <3000>; 1863 }; 1864 }; 1865 1866 mclk0_ao_pins: mclk0-ao { 1867 mux { 1868 groups = "mclk0_ao"; 1869 function = "mclk0_ao"; 1870 bias-disable; 1871 drive-strength-microamp = <3000>; 1872 }; 1873 }; 1874 1875 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1876 mux { 1877 groups = "tdm_ao_b_din0"; 1878 function = "tdm_ao_b"; 1879 bias-disable; 1880 }; 1881 }; 1882 1883 spdif_ao_out_pins: spdif-ao-out { 1884 mux { 1885 groups = "spdif_ao_out"; 1886 function = "spdif_ao_out"; 1887 drive-strength-microamp = <500>; 1888 bias-disable; 1889 }; 1890 }; 1891 1892 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1893 mux { 1894 groups = "tdm_ao_b_din1"; 1895 function = "tdm_ao_b"; 1896 bias-disable; 1897 }; 1898 }; 1899 1900 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1901 mux { 1902 groups = "tdm_ao_b_din2"; 1903 function = "tdm_ao_b"; 1904 bias-disable; 1905 }; 1906 }; 1907 1908 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1909 mux { 1910 groups = "tdm_ao_b_dout0"; 1911 function = "tdm_ao_b"; 1912 bias-disable; 1913 drive-strength-microamp = <3000>; 1914 }; 1915 }; 1916 1917 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1918 mux { 1919 groups = "tdm_ao_b_dout1"; 1920 function = "tdm_ao_b"; 1921 bias-disable; 1922 drive-strength-microamp = <3000>; 1923 }; 1924 }; 1925 1926 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1927 mux { 1928 groups = "tdm_ao_b_dout2"; 1929 function = "tdm_ao_b"; 1930 bias-disable; 1931 drive-strength-microamp = <3000>; 1932 }; 1933 }; 1934 1935 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1936 mux { 1937 groups = "tdm_ao_b_fs"; 1938 function = "tdm_ao_b"; 1939 bias-disable; 1940 drive-strength-microamp = <3000>; 1941 }; 1942 }; 1943 1944 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1945 mux { 1946 groups = "tdm_ao_b_sclk"; 1947 function = "tdm_ao_b"; 1948 bias-disable; 1949 drive-strength-microamp = <3000>; 1950 }; 1951 }; 1952 1953 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1954 mux { 1955 groups = "tdm_ao_b_slv_fs"; 1956 function = "tdm_ao_b"; 1957 bias-disable; 1958 }; 1959 }; 1960 1961 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1962 mux { 1963 groups = "tdm_ao_b_slv_sclk"; 1964 function = "tdm_ao_b"; 1965 bias-disable; 1966 }; 1967 }; 1968 1969 uart_ao_a_pins: uart-a-ao { 1970 mux { 1971 groups = "uart_ao_a_tx", 1972 "uart_ao_a_rx"; 1973 function = "uart_ao_a"; 1974 bias-disable; 1975 }; 1976 }; 1977 1978 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1979 mux { 1980 groups = "uart_ao_a_cts", 1981 "uart_ao_a_rts"; 1982 function = "uart_ao_a"; 1983 bias-disable; 1984 }; 1985 }; 1986 1987 pwm_a_e_pins: pwm-a-e { 1988 mux { 1989 groups = "pwm_a_e"; 1990 function = "pwm_a_e"; 1991 bias-disable; 1992 }; 1993 }; 1994 1995 pwm_ao_a_pins: pwm-ao-a { 1996 mux { 1997 groups = "pwm_ao_a"; 1998 function = "pwm_ao_a"; 1999 bias-disable; 2000 }; 2001 }; 2002 2003 pwm_ao_b_pins: pwm-ao-b { 2004 mux { 2005 groups = "pwm_ao_b"; 2006 function = "pwm_ao_b"; 2007 bias-disable; 2008 }; 2009 }; 2010 2011 pwm_ao_c_4_pins: pwm-ao-c-4 { 2012 mux { 2013 groups = "pwm_ao_c_4"; 2014 function = "pwm_ao_c"; 2015 bias-disable; 2016 }; 2017 }; 2018 2019 pwm_ao_c_6_pins: pwm-ao-c-6 { 2020 mux { 2021 groups = "pwm_ao_c_6"; 2022 function = "pwm_ao_c"; 2023 bias-disable; 2024 }; 2025 }; 2026 2027 pwm_ao_d_5_pins: pwm-ao-d-5 { 2028 mux { 2029 groups = "pwm_ao_d_5"; 2030 function = "pwm_ao_d"; 2031 bias-disable; 2032 }; 2033 }; 2034 2035 pwm_ao_d_10_pins: pwm-ao-d-10 { 2036 mux { 2037 groups = "pwm_ao_d_10"; 2038 function = "pwm_ao_d"; 2039 bias-disable; 2040 }; 2041 }; 2042 2043 pwm_ao_d_e_pins: pwm-ao-d-e { 2044 mux { 2045 groups = "pwm_ao_d_e"; 2046 function = "pwm_ao_d"; 2047 }; 2048 }; 2049 2050 remote_input_ao_pins: remote-input-ao { 2051 mux { 2052 groups = "remote_ao_input"; 2053 function = "remote_ao_input"; 2054 bias-disable; 2055 }; 2056 }; 2057 }; 2058 }; 2059 2060 vrtc: rtc@0a8 { 2061 compatible = "amlogic,meson-vrtc"; 2062 reg = <0x0 0x000a8 0x0 0x4>; 2063 }; 2064 2065 cec_AO: cec@100 { 2066 compatible = "amlogic,meson-gx-ao-cec"; 2067 reg = <0x0 0x00100 0x0 0x14>; 2068 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2069 clocks = <&clkc_AO CLKID_AO_CEC>; 2070 clock-names = "core"; 2071 status = "disabled"; 2072 }; 2073 2074 sec_AO: ao-secure@140 { 2075 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2076 reg = <0x0 0x140 0x0 0x140>; 2077 amlogic,has-chip-id; 2078 }; 2079 2080 cecb_AO: cec@280 { 2081 compatible = "amlogic,meson-g12a-ao-cec"; 2082 reg = <0x0 0x00280 0x0 0x1c>; 2083 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2084 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2085 clock-names = "oscin"; 2086 status = "disabled"; 2087 }; 2088 2089 pwm_AO_cd: pwm@2000 { 2090 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2091 reg = <0x0 0x2000 0x0 0x20>; 2092 #pwm-cells = <3>; 2093 status = "disabled"; 2094 }; 2095 2096 uart_AO: serial@3000 { 2097 compatible = "amlogic,meson-gx-uart", 2098 "amlogic,meson-ao-uart"; 2099 reg = <0x0 0x3000 0x0 0x18>; 2100 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2101 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2102 clock-names = "xtal", "pclk", "baud"; 2103 status = "disabled"; 2104 }; 2105 2106 uart_AO_B: serial@4000 { 2107 compatible = "amlogic,meson-gx-uart", 2108 "amlogic,meson-ao-uart"; 2109 reg = <0x0 0x4000 0x0 0x18>; 2110 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2111 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2112 clock-names = "xtal", "pclk", "baud"; 2113 status = "disabled"; 2114 }; 2115 2116 i2c_AO: i2c@5000 { 2117 compatible = "amlogic,meson-axg-i2c"; 2118 status = "disabled"; 2119 reg = <0x0 0x05000 0x0 0x20>; 2120 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2121 #address-cells = <1>; 2122 #size-cells = <0>; 2123 clocks = <&clkc CLKID_I2C>; 2124 }; 2125 2126 pwm_AO_ab: pwm@7000 { 2127 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2128 reg = <0x0 0x7000 0x0 0x20>; 2129 #pwm-cells = <3>; 2130 status = "disabled"; 2131 }; 2132 2133 ir: ir@8000 { 2134 compatible = "amlogic,meson-gxbb-ir"; 2135 reg = <0x0 0x8000 0x0 0x20>; 2136 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2137 status = "disabled"; 2138 }; 2139 2140 saradc: adc@9000 { 2141 compatible = "amlogic,meson-g12a-saradc", 2142 "amlogic,meson-saradc"; 2143 reg = <0x0 0x9000 0x0 0x48>; 2144 #io-channel-cells = <1>; 2145 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2146 clocks = <&xtal>, 2147 <&clkc_AO CLKID_AO_SAR_ADC>, 2148 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2149 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2150 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2151 status = "disabled"; 2152 }; 2153 }; 2154 2155 vpu: vpu@ff900000 { 2156 compatible = "amlogic,meson-g12a-vpu"; 2157 reg = <0x0 0xff900000 0x0 0x100000>, 2158 <0x0 0xff63c000 0x0 0x1000>; 2159 reg-names = "vpu", "hhi"; 2160 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2161 #address-cells = <1>; 2162 #size-cells = <0>; 2163 amlogic,canvas = <&canvas>; 2164 2165 /* CVBS VDAC output port */ 2166 cvbs_vdac_port: port@0 { 2167 reg = <0>; 2168 }; 2169 2170 /* HDMI-TX output port */ 2171 hdmi_tx_port: port@1 { 2172 reg = <1>; 2173 2174 hdmi_tx_out: endpoint { 2175 remote-endpoint = <&hdmi_tx_in>; 2176 }; 2177 }; 2178 }; 2179 2180 gic: interrupt-controller@ffc01000 { 2181 compatible = "arm,gic-400"; 2182 reg = <0x0 0xffc01000 0 0x1000>, 2183 <0x0 0xffc02000 0 0x2000>, 2184 <0x0 0xffc04000 0 0x2000>, 2185 <0x0 0xffc06000 0 0x2000>; 2186 interrupt-controller; 2187 interrupts = <GIC_PPI 9 2188 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2189 #interrupt-cells = <3>; 2190 #address-cells = <0>; 2191 }; 2192 2193 cbus: bus@ffd00000 { 2194 compatible = "simple-bus"; 2195 reg = <0x0 0xffd00000 0x0 0x100000>; 2196 #address-cells = <2>; 2197 #size-cells = <2>; 2198 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2199 2200 reset: reset-controller@1004 { 2201 compatible = "amlogic,meson-axg-reset"; 2202 reg = <0x0 0x1004 0x0 0x9c>; 2203 #reset-cells = <1>; 2204 }; 2205 2206 gpio_intc: interrupt-controller@f080 { 2207 compatible = "amlogic,meson-g12a-gpio-intc", 2208 "amlogic,meson-gpio-intc"; 2209 reg = <0x0 0xf080 0x0 0x10>; 2210 interrupt-controller; 2211 #interrupt-cells = <2>; 2212 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2213 }; 2214 2215 pwm_ef: pwm@19000 { 2216 compatible = "amlogic,meson-g12a-ee-pwm"; 2217 reg = <0x0 0x19000 0x0 0x20>; 2218 #pwm-cells = <3>; 2219 status = "disabled"; 2220 }; 2221 2222 pwm_cd: pwm@1a000 { 2223 compatible = "amlogic,meson-g12a-ee-pwm"; 2224 reg = <0x0 0x1a000 0x0 0x20>; 2225 #pwm-cells = <3>; 2226 status = "disabled"; 2227 }; 2228 2229 pwm_ab: pwm@1b000 { 2230 compatible = "amlogic,meson-g12a-ee-pwm"; 2231 reg = <0x0 0x1b000 0x0 0x20>; 2232 #pwm-cells = <3>; 2233 status = "disabled"; 2234 }; 2235 2236 i2c3: i2c@1c000 { 2237 compatible = "amlogic,meson-axg-i2c"; 2238 status = "disabled"; 2239 reg = <0x0 0x1c000 0x0 0x20>; 2240 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2241 #address-cells = <1>; 2242 #size-cells = <0>; 2243 clocks = <&clkc CLKID_I2C>; 2244 }; 2245 2246 i2c2: i2c@1d000 { 2247 compatible = "amlogic,meson-axg-i2c"; 2248 status = "disabled"; 2249 reg = <0x0 0x1d000 0x0 0x20>; 2250 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2251 #address-cells = <1>; 2252 #size-cells = <0>; 2253 clocks = <&clkc CLKID_I2C>; 2254 }; 2255 2256 i2c1: i2c@1e000 { 2257 compatible = "amlogic,meson-axg-i2c"; 2258 status = "disabled"; 2259 reg = <0x0 0x1e000 0x0 0x20>; 2260 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2261 #address-cells = <1>; 2262 #size-cells = <0>; 2263 clocks = <&clkc CLKID_I2C>; 2264 }; 2265 2266 i2c0: i2c@1f000 { 2267 compatible = "amlogic,meson-axg-i2c"; 2268 status = "disabled"; 2269 reg = <0x0 0x1f000 0x0 0x20>; 2270 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2271 #address-cells = <1>; 2272 #size-cells = <0>; 2273 clocks = <&clkc CLKID_I2C>; 2274 }; 2275 2276 clk_msr: clock-measure@18000 { 2277 compatible = "amlogic,meson-g12a-clk-measure"; 2278 reg = <0x0 0x18000 0x0 0x10>; 2279 }; 2280 2281 uart_C: serial@22000 { 2282 compatible = "amlogic,meson-gx-uart"; 2283 reg = <0x0 0x22000 0x0 0x18>; 2284 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2285 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2286 clock-names = "xtal", "pclk", "baud"; 2287 status = "disabled"; 2288 }; 2289 2290 uart_B: serial@23000 { 2291 compatible = "amlogic,meson-gx-uart"; 2292 reg = <0x0 0x23000 0x0 0x18>; 2293 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2294 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2295 clock-names = "xtal", "pclk", "baud"; 2296 status = "disabled"; 2297 }; 2298 2299 uart_A: serial@24000 { 2300 compatible = "amlogic,meson-gx-uart"; 2301 reg = <0x0 0x24000 0x0 0x18>; 2302 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2303 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2304 clock-names = "xtal", "pclk", "baud"; 2305 status = "disabled"; 2306 }; 2307 }; 2308 2309 sd_emmc_a: sd@ffe03000 { 2310 compatible = "amlogic,meson-axg-mmc"; 2311 reg = <0x0 0xffe03000 0x0 0x800>; 2312 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; 2313 status = "disabled"; 2314 clocks = <&clkc CLKID_SD_EMMC_A>, 2315 <&clkc CLKID_SD_EMMC_A_CLK0>, 2316 <&clkc CLKID_FCLK_DIV2>; 2317 clock-names = "core", "clkin0", "clkin1"; 2318 resets = <&reset RESET_SD_EMMC_A>; 2319 }; 2320 2321 sd_emmc_b: sd@ffe05000 { 2322 compatible = "amlogic,meson-axg-mmc"; 2323 reg = <0x0 0xffe05000 0x0 0x800>; 2324 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2325 status = "disabled"; 2326 clocks = <&clkc CLKID_SD_EMMC_B>, 2327 <&clkc CLKID_SD_EMMC_B_CLK0>, 2328 <&clkc CLKID_FCLK_DIV2>; 2329 clock-names = "core", "clkin0", "clkin1"; 2330 resets = <&reset RESET_SD_EMMC_B>; 2331 }; 2332 2333 sd_emmc_c: mmc@ffe07000 { 2334 compatible = "amlogic,meson-axg-mmc"; 2335 reg = <0x0 0xffe07000 0x0 0x800>; 2336 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2337 status = "disabled"; 2338 clocks = <&clkc CLKID_SD_EMMC_C>, 2339 <&clkc CLKID_SD_EMMC_C_CLK0>, 2340 <&clkc CLKID_FCLK_DIV2>; 2341 clock-names = "core", "clkin0", "clkin1"; 2342 resets = <&reset RESET_SD_EMMC_C>; 2343 }; 2344 2345 usb: usb@ffe09000 { 2346 status = "disabled"; 2347 compatible = "amlogic,meson-g12a-usb-ctrl"; 2348 reg = <0x0 0xffe09000 0x0 0xa0>; 2349 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2350 #address-cells = <2>; 2351 #size-cells = <2>; 2352 ranges; 2353 2354 clocks = <&clkc CLKID_USB>; 2355 resets = <&reset RESET_USB>; 2356 2357 dr_mode = "otg"; 2358 2359 phys = <&usb2_phy0>, <&usb2_phy1>, 2360 <&usb3_pcie_phy PHY_TYPE_USB3>; 2361 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2362 2363 dwc2: usb@ff400000 { 2364 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2365 reg = <0x0 0xff400000 0x0 0x40000>; 2366 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2367 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2368 clock-names = "ddr"; 2369 phys = <&usb2_phy1>; 2370 phy-names = "usb2-phy"; 2371 dr_mode = "peripheral"; 2372 g-rx-fifo-size = <192>; 2373 g-np-tx-fifo-size = <128>; 2374 g-tx-fifo-size = <128 128 16 16 16>; 2375 }; 2376 2377 dwc3: usb@ff500000 { 2378 compatible = "snps,dwc3"; 2379 reg = <0x0 0xff500000 0x0 0x100000>; 2380 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2381 dr_mode = "host"; 2382 snps,dis_u2_susphy_quirk; 2383 snps,quirk-frame-length-adjustment; 2384 }; 2385 }; 2386 2387 mali: gpu@ffe40000 { 2388 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2389 reg = <0x0 0xffe40000 0x0 0x40000>; 2390 interrupt-parent = <&gic>; 2391 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2392 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2393 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2394 interrupt-names = "gpu", "mmu", "job"; 2395 clocks = <&clkc CLKID_MALI>; 2396 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2397 2398 /* 2399 * Mali clocking is provided by two identical clock paths 2400 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2401 * free mux to safely change frequency while running. 2402 */ 2403 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2404 <&clkc CLKID_MALI_0>, 2405 <&clkc CLKID_MALI>; /* Glitch free mux */ 2406 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2407 <0>, /* Do Nothing */ 2408 <&clkc CLKID_MALI_0>; 2409 assigned-clock-rates = <0>, /* Do Nothing */ 2410 <800000000>, 2411 <0>; /* Do Nothing */ 2412 }; 2413 }; 2414 2415 timer { 2416 compatible = "arm,armv8-timer"; 2417 interrupts = <GIC_PPI 13 2418 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2419 <GIC_PPI 14 2420 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2421 <GIC_PPI 11 2422 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2423 <GIC_PPI 10 2424 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2425 arm,no-tick-in-suspend; 2426 }; 2427 2428 xtal: xtal-clk { 2429 compatible = "fixed-clock"; 2430 clock-frequency = <24000000>; 2431 clock-output-names = "xtal"; 2432 #clock-cells = <0>; 2433 }; 2434 2435}; 2436