1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/g12a-clkc.h> 9#include <dt-bindings/clock/g12a-aoclkc.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 aliases { 21 mmc0 = &sd_emmc_b; /* SD card */ 22 mmc1 = &sd_emmc_c; /* eMMC */ 23 mmc2 = &sd_emmc_a; /* SDIO */ 24 }; 25 26 chosen { 27 #address-cells = <2>; 28 #size-cells = <2>; 29 ranges; 30 31 simplefb_cvbs: framebuffer-cvbs { 32 compatible = "amlogic,simple-framebuffer", 33 "simple-framebuffer"; 34 amlogic,pipeline = "vpu-cvbs"; 35 clocks = <&clkc CLKID_HDMI>, 36 <&clkc CLKID_HTX_PCLK>, 37 <&clkc CLKID_VPU_INTR>; 38 status = "disabled"; 39 }; 40 41 simplefb_hdmi: framebuffer-hdmi { 42 compatible = "amlogic,simple-framebuffer", 43 "simple-framebuffer"; 44 amlogic,pipeline = "vpu-hdmi"; 45 clocks = <&clkc CLKID_HDMI>, 46 <&clkc CLKID_HTX_PCLK>, 47 <&clkc CLKID_VPU_INTR>; 48 status = "disabled"; 49 }; 50 }; 51 52 efuse: efuse { 53 compatible = "amlogic,meson-gxbb-efuse"; 54 clocks = <&clkc CLKID_EFUSE>; 55 #address-cells = <1>; 56 #size-cells = <1>; 57 read-only; 58 secure-monitor = <&sm>; 59 }; 60 61 gpu_opp_table: opp-table-gpu { 62 compatible = "operating-points-v2"; 63 64 opp-124999998 { 65 opp-hz = /bits/ 64 <124999998>; 66 opp-microvolt = <800000>; 67 }; 68 opp-249999996 { 69 opp-hz = /bits/ 64 <249999996>; 70 opp-microvolt = <800000>; 71 }; 72 opp-285714281 { 73 opp-hz = /bits/ 64 <285714281>; 74 opp-microvolt = <800000>; 75 }; 76 opp-399999994 { 77 opp-hz = /bits/ 64 <399999994>; 78 opp-microvolt = <800000>; 79 }; 80 opp-499999992 { 81 opp-hz = /bits/ 64 <499999992>; 82 opp-microvolt = <800000>; 83 }; 84 opp-666666656 { 85 opp-hz = /bits/ 64 <666666656>; 86 opp-microvolt = <800000>; 87 }; 88 opp-799999987 { 89 opp-hz = /bits/ 64 <799999987>; 90 opp-microvolt = <800000>; 91 }; 92 }; 93 94 psci { 95 compatible = "arm,psci-1.0"; 96 method = "smc"; 97 }; 98 99 reserved-memory { 100 #address-cells = <2>; 101 #size-cells = <2>; 102 ranges; 103 104 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 105 secmon_reserved: secmon@5000000 { 106 reg = <0x0 0x05000000 0x0 0x300000>; 107 no-map; 108 }; 109 110 /* 32 MiB reserved for ARM Trusted Firmware (BL32) */ 111 secmon_reserved_bl32: secmon@5300000 { 112 reg = <0x0 0x05300000 0x0 0x2000000>; 113 no-map; 114 }; 115 116 linux,cma { 117 compatible = "shared-dma-pool"; 118 reusable; 119 size = <0x0 0x10000000>; 120 alignment = <0x0 0x400000>; 121 linux,cma-default; 122 }; 123 }; 124 125 sm: secure-monitor { 126 compatible = "amlogic,meson-gxbb-sm"; 127 }; 128 129 soc { 130 compatible = "simple-bus"; 131 #address-cells = <2>; 132 #size-cells = <2>; 133 ranges; 134 135 pcie: pcie@fc000000 { 136 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 137 reg = <0x0 0xfc000000 0x0 0x400000>, 138 <0x0 0xff648000 0x0 0x2000>, 139 <0x0 0xfc400000 0x0 0x200000>; 140 reg-names = "elbi", "cfg", "config"; 141 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 142 #interrupt-cells = <1>; 143 interrupt-map-mask = <0 0 0 0>; 144 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 145 bus-range = <0x0 0xff>; 146 #address-cells = <3>; 147 #size-cells = <2>; 148 device_type = "pci"; 149 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000>, 150 <0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 151 152 clocks = <&clkc CLKID_PCIE_PHY 153 &clkc CLKID_PCIE_COMB 154 &clkc CLKID_PCIE_PLL>; 155 clock-names = "general", 156 "pclk", 157 "port"; 158 resets = <&reset RESET_PCIE_CTRL_A>, 159 <&reset RESET_PCIE_APB>; 160 reset-names = "port", 161 "apb"; 162 num-lanes = <1>; 163 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 164 phy-names = "pcie"; 165 status = "disabled"; 166 }; 167 168 ethmac: ethernet@ff3f0000 { 169 compatible = "amlogic,meson-g12a-dwmac", 170 "snps,dwmac-3.70a", 171 "snps,dwmac"; 172 reg = <0x0 0xff3f0000 0x0 0x10000>, 173 <0x0 0xff634540 0x0 0x8>; 174 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 175 interrupt-names = "macirq"; 176 clocks = <&clkc CLKID_ETH>, 177 <&clkc CLKID_FCLK_DIV2>, 178 <&clkc CLKID_MPLL2>, 179 <&clkc CLKID_FCLK_DIV2>; 180 clock-names = "stmmaceth", "clkin0", "clkin1", 181 "timing-adjustment"; 182 rx-fifo-depth = <4096>; 183 tx-fifo-depth = <2048>; 184 status = "disabled"; 185 186 mdio0: mdio { 187 #address-cells = <1>; 188 #size-cells = <0>; 189 compatible = "snps,dwmac-mdio"; 190 }; 191 }; 192 193 apb: bus@ff600000 { 194 compatible = "simple-bus"; 195 reg = <0x0 0xff600000 0x0 0x200000>; 196 #address-cells = <2>; 197 #size-cells = <2>; 198 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 199 200 hdmi_tx: hdmi-tx@0 { 201 compatible = "amlogic,meson-g12a-dw-hdmi"; 202 reg = <0x0 0x0 0x0 0x10000>; 203 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 204 resets = <&reset RESET_HDMITX_CAPB3>, 205 <&reset RESET_HDMITX_PHY>, 206 <&reset RESET_HDMITX>; 207 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 208 clocks = <&clkc CLKID_HDMI>, 209 <&clkc CLKID_HTX_PCLK>, 210 <&clkc CLKID_VPU_INTR>; 211 clock-names = "isfr", "iahb", "venci"; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 #sound-dai-cells = <0>; 215 status = "disabled"; 216 217 /* VPU VENC Input */ 218 hdmi_tx_venc_port: port@0 { 219 reg = <0>; 220 221 hdmi_tx_in: endpoint { 222 remote-endpoint = <&hdmi_tx_out>; 223 }; 224 }; 225 226 /* TMDS Output */ 227 hdmi_tx_tmds_port: port@1 { 228 reg = <1>; 229 }; 230 }; 231 232 apb_efuse: bus@30000 { 233 compatible = "simple-bus"; 234 reg = <0x0 0x30000 0x0 0x2000>; 235 #address-cells = <2>; 236 #size-cells = <2>; 237 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 238 239 hwrng: rng@218 { 240 compatible = "amlogic,meson-rng"; 241 reg = <0x0 0x218 0x0 0x4>; 242 clocks = <&clkc CLKID_RNG0>; 243 clock-names = "core"; 244 }; 245 }; 246 247 acodec: audio-controller@32000 { 248 compatible = "amlogic,t9015"; 249 reg = <0x0 0x32000 0x0 0x14>; 250 #sound-dai-cells = <0>; 251 sound-name-prefix = "ACODEC"; 252 clocks = <&clkc CLKID_AUDIO_CODEC>; 253 clock-names = "pclk"; 254 resets = <&reset RESET_AUDIO_CODEC>; 255 status = "disabled"; 256 }; 257 258 periphs: bus@34400 { 259 compatible = "simple-bus"; 260 reg = <0x0 0x34400 0x0 0x400>; 261 #address-cells = <2>; 262 #size-cells = <2>; 263 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 264 265 periphs_pinctrl: pinctrl@40 { 266 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 267 #address-cells = <2>; 268 #size-cells = <2>; 269 ranges; 270 271 gpio: bank@40 { 272 reg = <0x0 0x40 0x0 0x4c>, 273 <0x0 0xe8 0x0 0x18>, 274 <0x0 0x120 0x0 0x18>, 275 <0x0 0x2c0 0x0 0x40>, 276 <0x0 0x340 0x0 0x1c>; 277 reg-names = "gpio", 278 "pull", 279 "pull-enable", 280 "mux", 281 "ds"; 282 gpio-controller; 283 #gpio-cells = <2>; 284 gpio-ranges = <&periphs_pinctrl 0 0 86>; 285 }; 286 287 cec_ao_a_h_pins: cec_ao_a_h { 288 mux { 289 groups = "cec_ao_a_h"; 290 function = "cec_ao_a_h"; 291 bias-disable; 292 }; 293 }; 294 295 cec_ao_b_h_pins: cec_ao_b_h { 296 mux { 297 groups = "cec_ao_b_h"; 298 function = "cec_ao_b_h"; 299 bias-disable; 300 }; 301 }; 302 303 emmc_ctrl_pins: emmc-ctrl { 304 mux-0 { 305 groups = "emmc_cmd"; 306 function = "emmc"; 307 bias-pull-up; 308 drive-strength-microamp = <4000>; 309 }; 310 311 mux-1 { 312 groups = "emmc_clk"; 313 function = "emmc"; 314 bias-disable; 315 drive-strength-microamp = <4000>; 316 }; 317 }; 318 319 emmc_data_4b_pins: emmc-data-4b { 320 mux-0 { 321 groups = "emmc_nand_d0", 322 "emmc_nand_d1", 323 "emmc_nand_d2", 324 "emmc_nand_d3"; 325 function = "emmc"; 326 bias-pull-up; 327 drive-strength-microamp = <4000>; 328 }; 329 }; 330 331 emmc_data_8b_pins: emmc-data-8b { 332 mux-0 { 333 groups = "emmc_nand_d0", 334 "emmc_nand_d1", 335 "emmc_nand_d2", 336 "emmc_nand_d3", 337 "emmc_nand_d4", 338 "emmc_nand_d5", 339 "emmc_nand_d6", 340 "emmc_nand_d7"; 341 function = "emmc"; 342 bias-pull-up; 343 drive-strength-microamp = <4000>; 344 }; 345 }; 346 347 emmc_ds_pins: emmc-ds { 348 mux { 349 groups = "emmc_nand_ds"; 350 function = "emmc"; 351 bias-pull-down; 352 drive-strength-microamp = <4000>; 353 }; 354 }; 355 356 emmc_clk_gate_pins: emmc_clk_gate { 357 mux { 358 groups = "BOOT_8"; 359 function = "gpio_periphs"; 360 bias-pull-down; 361 drive-strength-microamp = <4000>; 362 }; 363 }; 364 365 hdmitx_ddc_pins: hdmitx_ddc { 366 mux { 367 groups = "hdmitx_sda", 368 "hdmitx_sck"; 369 function = "hdmitx"; 370 bias-disable; 371 drive-strength-microamp = <4000>; 372 }; 373 }; 374 375 hdmitx_hpd_pins: hdmitx_hpd { 376 mux { 377 groups = "hdmitx_hpd_in"; 378 function = "hdmitx"; 379 bias-disable; 380 }; 381 }; 382 383 384 i2c0_sda_c_pins: i2c0-sda-c { 385 mux { 386 groups = "i2c0_sda_c"; 387 function = "i2c0"; 388 bias-disable; 389 drive-strength-microamp = <3000>; 390 391 }; 392 }; 393 394 i2c0_sck_c_pins: i2c0-sck-c { 395 mux { 396 groups = "i2c0_sck_c"; 397 function = "i2c0"; 398 bias-disable; 399 drive-strength-microamp = <3000>; 400 }; 401 }; 402 403 i2c0_sda_z0_pins: i2c0-sda-z0 { 404 mux { 405 groups = "i2c0_sda_z0"; 406 function = "i2c0"; 407 bias-disable; 408 drive-strength-microamp = <3000>; 409 }; 410 }; 411 412 i2c0_sck_z1_pins: i2c0-sck-z1 { 413 mux { 414 groups = "i2c0_sck_z1"; 415 function = "i2c0"; 416 bias-disable; 417 drive-strength-microamp = <3000>; 418 }; 419 }; 420 421 i2c0_sda_z7_pins: i2c0-sda-z7 { 422 mux { 423 groups = "i2c0_sda_z7"; 424 function = "i2c0"; 425 bias-disable; 426 drive-strength-microamp = <3000>; 427 }; 428 }; 429 430 i2c0_sda_z8_pins: i2c0-sda-z8 { 431 mux { 432 groups = "i2c0_sda_z8"; 433 function = "i2c0"; 434 bias-disable; 435 drive-strength-microamp = <3000>; 436 }; 437 }; 438 439 i2c1_sda_x_pins: i2c1-sda-x { 440 mux { 441 groups = "i2c1_sda_x"; 442 function = "i2c1"; 443 bias-disable; 444 drive-strength-microamp = <3000>; 445 }; 446 }; 447 448 i2c1_sck_x_pins: i2c1-sck-x { 449 mux { 450 groups = "i2c1_sck_x"; 451 function = "i2c1"; 452 bias-disable; 453 drive-strength-microamp = <3000>; 454 }; 455 }; 456 457 i2c1_sda_h2_pins: i2c1-sda-h2 { 458 mux { 459 groups = "i2c1_sda_h2"; 460 function = "i2c1"; 461 bias-disable; 462 drive-strength-microamp = <3000>; 463 }; 464 }; 465 466 i2c1_sck_h3_pins: i2c1-sck-h3 { 467 mux { 468 groups = "i2c1_sck_h3"; 469 function = "i2c1"; 470 bias-disable; 471 drive-strength-microamp = <3000>; 472 }; 473 }; 474 475 i2c1_sda_h6_pins: i2c1-sda-h6 { 476 mux { 477 groups = "i2c1_sda_h6"; 478 function = "i2c1"; 479 bias-disable; 480 drive-strength-microamp = <3000>; 481 }; 482 }; 483 484 i2c1_sck_h7_pins: i2c1-sck-h7 { 485 mux { 486 groups = "i2c1_sck_h7"; 487 function = "i2c1"; 488 bias-disable; 489 drive-strength-microamp = <3000>; 490 }; 491 }; 492 493 i2c2_sda_x_pins: i2c2-sda-x { 494 mux { 495 groups = "i2c2_sda_x"; 496 function = "i2c2"; 497 bias-disable; 498 drive-strength-microamp = <3000>; 499 }; 500 }; 501 502 i2c2_sck_x_pins: i2c2-sck-x { 503 mux { 504 groups = "i2c2_sck_x"; 505 function = "i2c2"; 506 bias-disable; 507 drive-strength-microamp = <3000>; 508 }; 509 }; 510 511 i2c2_sda_z_pins: i2c2-sda-z { 512 mux { 513 groups = "i2c2_sda_z"; 514 function = "i2c2"; 515 bias-disable; 516 drive-strength-microamp = <3000>; 517 }; 518 }; 519 520 i2c2_sck_z_pins: i2c2-sck-z { 521 mux { 522 groups = "i2c2_sck_z"; 523 function = "i2c2"; 524 bias-disable; 525 drive-strength-microamp = <3000>; 526 }; 527 }; 528 529 i2c3_sda_h_pins: i2c3-sda-h { 530 mux { 531 groups = "i2c3_sda_h"; 532 function = "i2c3"; 533 bias-disable; 534 drive-strength-microamp = <3000>; 535 }; 536 }; 537 538 i2c3_sck_h_pins: i2c3-sck-h { 539 mux { 540 groups = "i2c3_sck_h"; 541 function = "i2c3"; 542 bias-disable; 543 drive-strength-microamp = <3000>; 544 }; 545 }; 546 547 i2c3_sda_a_pins: i2c3-sda-a { 548 mux { 549 groups = "i2c3_sda_a"; 550 function = "i2c3"; 551 bias-disable; 552 drive-strength-microamp = <3000>; 553 }; 554 }; 555 556 i2c3_sck_a_pins: i2c3-sck-a { 557 mux { 558 groups = "i2c3_sck_a"; 559 function = "i2c3"; 560 bias-disable; 561 drive-strength-microamp = <3000>; 562 }; 563 }; 564 565 mclk0_a_pins: mclk0-a { 566 mux { 567 groups = "mclk0_a"; 568 function = "mclk0"; 569 bias-disable; 570 drive-strength-microamp = <3000>; 571 }; 572 }; 573 574 mclk1_a_pins: mclk1-a { 575 mux { 576 groups = "mclk1_a"; 577 function = "mclk1"; 578 bias-disable; 579 drive-strength-microamp = <3000>; 580 }; 581 }; 582 583 mclk1_x_pins: mclk1-x { 584 mux { 585 groups = "mclk1_x"; 586 function = "mclk1"; 587 bias-disable; 588 drive-strength-microamp = <3000>; 589 }; 590 }; 591 592 mclk1_z_pins: mclk1-z { 593 mux { 594 groups = "mclk1_z"; 595 function = "mclk1"; 596 bias-disable; 597 drive-strength-microamp = <3000>; 598 }; 599 }; 600 601 nor_pins: nor { 602 mux { 603 groups = "nor_d", 604 "nor_q", 605 "nor_c", 606 "nor_cs"; 607 function = "nor"; 608 bias-disable; 609 }; 610 }; 611 612 pdm_din0_a_pins: pdm-din0-a { 613 mux { 614 groups = "pdm_din0_a"; 615 function = "pdm"; 616 bias-disable; 617 }; 618 }; 619 620 pdm_din0_c_pins: pdm-din0-c { 621 mux { 622 groups = "pdm_din0_c"; 623 function = "pdm"; 624 bias-disable; 625 }; 626 }; 627 628 pdm_din0_x_pins: pdm-din0-x { 629 mux { 630 groups = "pdm_din0_x"; 631 function = "pdm"; 632 bias-disable; 633 }; 634 }; 635 636 pdm_din0_z_pins: pdm-din0-z { 637 mux { 638 groups = "pdm_din0_z"; 639 function = "pdm"; 640 bias-disable; 641 }; 642 }; 643 644 pdm_din1_a_pins: pdm-din1-a { 645 mux { 646 groups = "pdm_din1_a"; 647 function = "pdm"; 648 bias-disable; 649 }; 650 }; 651 652 pdm_din1_c_pins: pdm-din1-c { 653 mux { 654 groups = "pdm_din1_c"; 655 function = "pdm"; 656 bias-disable; 657 }; 658 }; 659 660 pdm_din1_x_pins: pdm-din1-x { 661 mux { 662 groups = "pdm_din1_x"; 663 function = "pdm"; 664 bias-disable; 665 }; 666 }; 667 668 pdm_din1_z_pins: pdm-din1-z { 669 mux { 670 groups = "pdm_din1_z"; 671 function = "pdm"; 672 bias-disable; 673 }; 674 }; 675 676 pdm_din2_a_pins: pdm-din2-a { 677 mux { 678 groups = "pdm_din2_a"; 679 function = "pdm"; 680 bias-disable; 681 }; 682 }; 683 684 pdm_din2_c_pins: pdm-din2-c { 685 mux { 686 groups = "pdm_din2_c"; 687 function = "pdm"; 688 bias-disable; 689 }; 690 }; 691 692 pdm_din2_x_pins: pdm-din2-x { 693 mux { 694 groups = "pdm_din2_x"; 695 function = "pdm"; 696 bias-disable; 697 }; 698 }; 699 700 pdm_din2_z_pins: pdm-din2-z { 701 mux { 702 groups = "pdm_din2_z"; 703 function = "pdm"; 704 bias-disable; 705 }; 706 }; 707 708 pdm_din3_a_pins: pdm-din3-a { 709 mux { 710 groups = "pdm_din3_a"; 711 function = "pdm"; 712 bias-disable; 713 }; 714 }; 715 716 pdm_din3_c_pins: pdm-din3-c { 717 mux { 718 groups = "pdm_din3_c"; 719 function = "pdm"; 720 bias-disable; 721 }; 722 }; 723 724 pdm_din3_x_pins: pdm-din3-x { 725 mux { 726 groups = "pdm_din3_x"; 727 function = "pdm"; 728 bias-disable; 729 }; 730 }; 731 732 pdm_din3_z_pins: pdm-din3-z { 733 mux { 734 groups = "pdm_din3_z"; 735 function = "pdm"; 736 bias-disable; 737 }; 738 }; 739 740 pdm_dclk_a_pins: pdm-dclk-a { 741 mux { 742 groups = "pdm_dclk_a"; 743 function = "pdm"; 744 bias-disable; 745 drive-strength-microamp = <500>; 746 }; 747 }; 748 749 pdm_dclk_c_pins: pdm-dclk-c { 750 mux { 751 groups = "pdm_dclk_c"; 752 function = "pdm"; 753 bias-disable; 754 drive-strength-microamp = <500>; 755 }; 756 }; 757 758 pdm_dclk_x_pins: pdm-dclk-x { 759 mux { 760 groups = "pdm_dclk_x"; 761 function = "pdm"; 762 bias-disable; 763 drive-strength-microamp = <500>; 764 }; 765 }; 766 767 pdm_dclk_z_pins: pdm-dclk-z { 768 mux { 769 groups = "pdm_dclk_z"; 770 function = "pdm"; 771 bias-disable; 772 drive-strength-microamp = <500>; 773 }; 774 }; 775 776 pwm_a_pins: pwm-a { 777 mux { 778 groups = "pwm_a"; 779 function = "pwm_a"; 780 bias-disable; 781 }; 782 }; 783 784 pwm_b_x7_pins: pwm-b-x7 { 785 mux { 786 groups = "pwm_b_x7"; 787 function = "pwm_b"; 788 bias-disable; 789 }; 790 }; 791 792 pwm_b_x19_pins: pwm-b-x19 { 793 mux { 794 groups = "pwm_b_x19"; 795 function = "pwm_b"; 796 bias-disable; 797 }; 798 }; 799 800 pwm_c_c_pins: pwm-c-c { 801 mux { 802 groups = "pwm_c_c"; 803 function = "pwm_c"; 804 bias-disable; 805 }; 806 }; 807 808 pwm_c_x5_pins: pwm-c-x5 { 809 mux { 810 groups = "pwm_c_x5"; 811 function = "pwm_c"; 812 bias-disable; 813 }; 814 }; 815 816 pwm_c_x8_pins: pwm-c-x8 { 817 mux { 818 groups = "pwm_c_x8"; 819 function = "pwm_c"; 820 bias-disable; 821 }; 822 }; 823 824 pwm_d_x3_pins: pwm-d-x3 { 825 mux { 826 groups = "pwm_d_x3"; 827 function = "pwm_d"; 828 bias-disable; 829 }; 830 }; 831 832 pwm_d_x6_pins: pwm-d-x6 { 833 mux { 834 groups = "pwm_d_x6"; 835 function = "pwm_d"; 836 bias-disable; 837 }; 838 }; 839 840 pwm_e_pins: pwm-e { 841 mux { 842 groups = "pwm_e"; 843 function = "pwm_e"; 844 bias-disable; 845 }; 846 }; 847 848 pwm_f_z_pins: pwm-f-z { 849 mux { 850 groups = "pwm_f_z"; 851 function = "pwm_f"; 852 bias-disable; 853 }; 854 }; 855 856 pwm_f_a_pins: pwm-f-a { 857 mux { 858 groups = "pwm_f_a"; 859 function = "pwm_f"; 860 bias-disable; 861 }; 862 }; 863 864 pwm_f_x_pins: pwm-f-x { 865 mux { 866 groups = "pwm_f_x"; 867 function = "pwm_f"; 868 bias-disable; 869 }; 870 }; 871 872 pwm_f_h_pins: pwm-f-h { 873 mux { 874 groups = "pwm_f_h"; 875 function = "pwm_f"; 876 bias-disable; 877 }; 878 }; 879 880 sdcard_c_pins: sdcard_c { 881 mux-0 { 882 groups = "sdcard_d0_c", 883 "sdcard_d1_c", 884 "sdcard_d2_c", 885 "sdcard_d3_c", 886 "sdcard_cmd_c"; 887 function = "sdcard"; 888 bias-pull-up; 889 drive-strength-microamp = <4000>; 890 }; 891 892 mux-1 { 893 groups = "sdcard_clk_c"; 894 function = "sdcard"; 895 bias-disable; 896 drive-strength-microamp = <4000>; 897 }; 898 }; 899 900 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 901 mux { 902 groups = "GPIOC_4"; 903 function = "gpio_periphs"; 904 bias-pull-down; 905 drive-strength-microamp = <4000>; 906 }; 907 }; 908 909 sdcard_z_pins: sdcard_z { 910 mux-0 { 911 groups = "sdcard_d0_z", 912 "sdcard_d1_z", 913 "sdcard_d2_z", 914 "sdcard_d3_z", 915 "sdcard_cmd_z"; 916 function = "sdcard"; 917 bias-pull-up; 918 drive-strength-microamp = <4000>; 919 }; 920 921 mux-1 { 922 groups = "sdcard_clk_z"; 923 function = "sdcard"; 924 bias-disable; 925 drive-strength-microamp = <4000>; 926 }; 927 }; 928 929 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 930 mux { 931 groups = "GPIOZ_6"; 932 function = "gpio_periphs"; 933 bias-pull-down; 934 drive-strength-microamp = <4000>; 935 }; 936 }; 937 938 sdio_pins: sdio { 939 mux { 940 groups = "sdio_d0", 941 "sdio_d1", 942 "sdio_d2", 943 "sdio_d3", 944 "sdio_clk", 945 "sdio_cmd"; 946 function = "sdio"; 947 bias-disable; 948 drive-strength-microamp = <4000>; 949 }; 950 }; 951 952 sdio_clk_gate_pins: sdio_clk_gate { 953 mux { 954 groups = "GPIOX_4"; 955 function = "gpio_periphs"; 956 bias-pull-down; 957 drive-strength-microamp = <4000>; 958 }; 959 }; 960 961 spdif_in_a10_pins: spdif-in-a10 { 962 mux { 963 groups = "spdif_in_a10"; 964 function = "spdif_in"; 965 bias-disable; 966 }; 967 }; 968 969 spdif_in_a12_pins: spdif-in-a12 { 970 mux { 971 groups = "spdif_in_a12"; 972 function = "spdif_in"; 973 bias-disable; 974 }; 975 }; 976 977 spdif_in_h_pins: spdif-in-h { 978 mux { 979 groups = "spdif_in_h"; 980 function = "spdif_in"; 981 bias-disable; 982 }; 983 }; 984 985 spdif_out_h_pins: spdif-out-h { 986 mux { 987 groups = "spdif_out_h"; 988 function = "spdif_out"; 989 drive-strength-microamp = <500>; 990 bias-disable; 991 }; 992 }; 993 994 spdif_out_a11_pins: spdif-out-a11 { 995 mux { 996 groups = "spdif_out_a11"; 997 function = "spdif_out"; 998 drive-strength-microamp = <500>; 999 bias-disable; 1000 }; 1001 }; 1002 1003 spdif_out_a13_pins: spdif-out-a13 { 1004 mux { 1005 groups = "spdif_out_a13"; 1006 function = "spdif_out"; 1007 drive-strength-microamp = <500>; 1008 bias-disable; 1009 }; 1010 }; 1011 1012 spicc0_x_pins: spicc0-x { 1013 mux { 1014 groups = "spi0_mosi_x", 1015 "spi0_miso_x", 1016 "spi0_clk_x"; 1017 function = "spi0"; 1018 drive-strength-microamp = <4000>; 1019 bias-disable; 1020 }; 1021 }; 1022 1023 spicc0_ss0_x_pins: spicc0-ss0-x { 1024 mux { 1025 groups = "spi0_ss0_x"; 1026 function = "spi0"; 1027 drive-strength-microamp = <4000>; 1028 bias-disable; 1029 }; 1030 }; 1031 1032 spicc0_c_pins: spicc0-c { 1033 mux { 1034 groups = "spi0_mosi_c", 1035 "spi0_miso_c", 1036 "spi0_ss0_c", 1037 "spi0_clk_c"; 1038 function = "spi0"; 1039 drive-strength-microamp = <4000>; 1040 bias-disable; 1041 }; 1042 }; 1043 1044 spicc1_pins: spicc1 { 1045 mux { 1046 groups = "spi1_mosi", 1047 "spi1_miso", 1048 "spi1_clk"; 1049 function = "spi1"; 1050 drive-strength-microamp = <4000>; 1051 }; 1052 }; 1053 1054 spicc1_ss0_pins: spicc1-ss0 { 1055 mux { 1056 groups = "spi1_ss0"; 1057 function = "spi1"; 1058 drive-strength-microamp = <4000>; 1059 bias-disable; 1060 }; 1061 }; 1062 1063 tdm_a_din0_pins: tdm-a-din0 { 1064 mux { 1065 groups = "tdm_a_din0"; 1066 function = "tdm_a"; 1067 bias-disable; 1068 }; 1069 }; 1070 1071 1072 tdm_a_din1_pins: tdm-a-din1 { 1073 mux { 1074 groups = "tdm_a_din1"; 1075 function = "tdm_a"; 1076 bias-disable; 1077 }; 1078 }; 1079 1080 tdm_a_dout0_pins: tdm-a-dout0 { 1081 mux { 1082 groups = "tdm_a_dout0"; 1083 function = "tdm_a"; 1084 bias-disable; 1085 drive-strength-microamp = <3000>; 1086 }; 1087 }; 1088 1089 tdm_a_dout1_pins: tdm-a-dout1 { 1090 mux { 1091 groups = "tdm_a_dout1"; 1092 function = "tdm_a"; 1093 bias-disable; 1094 drive-strength-microamp = <3000>; 1095 }; 1096 }; 1097 1098 tdm_a_fs_pins: tdm-a-fs { 1099 mux { 1100 groups = "tdm_a_fs"; 1101 function = "tdm_a"; 1102 bias-disable; 1103 drive-strength-microamp = <3000>; 1104 }; 1105 }; 1106 1107 tdm_a_sclk_pins: tdm-a-sclk { 1108 mux { 1109 groups = "tdm_a_sclk"; 1110 function = "tdm_a"; 1111 bias-disable; 1112 drive-strength-microamp = <3000>; 1113 }; 1114 }; 1115 1116 tdm_a_slv_fs_pins: tdm-a-slv-fs { 1117 mux { 1118 groups = "tdm_a_slv_fs"; 1119 function = "tdm_a"; 1120 bias-disable; 1121 }; 1122 }; 1123 1124 1125 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 1126 mux { 1127 groups = "tdm_a_slv_sclk"; 1128 function = "tdm_a"; 1129 bias-disable; 1130 }; 1131 }; 1132 1133 tdm_b_din0_pins: tdm-b-din0 { 1134 mux { 1135 groups = "tdm_b_din0"; 1136 function = "tdm_b"; 1137 bias-disable; 1138 }; 1139 }; 1140 1141 tdm_b_din1_pins: tdm-b-din1 { 1142 mux { 1143 groups = "tdm_b_din1"; 1144 function = "tdm_b"; 1145 bias-disable; 1146 }; 1147 }; 1148 1149 tdm_b_din2_pins: tdm-b-din2 { 1150 mux { 1151 groups = "tdm_b_din2"; 1152 function = "tdm_b"; 1153 bias-disable; 1154 }; 1155 }; 1156 1157 tdm_b_din3_a_pins: tdm-b-din3-a { 1158 mux { 1159 groups = "tdm_b_din3_a"; 1160 function = "tdm_b"; 1161 bias-disable; 1162 }; 1163 }; 1164 1165 tdm_b_din3_h_pins: tdm-b-din3-h { 1166 mux { 1167 groups = "tdm_b_din3_h"; 1168 function = "tdm_b"; 1169 bias-disable; 1170 }; 1171 }; 1172 1173 tdm_b_dout0_pins: tdm-b-dout0 { 1174 mux { 1175 groups = "tdm_b_dout0"; 1176 function = "tdm_b"; 1177 bias-disable; 1178 drive-strength-microamp = <3000>; 1179 }; 1180 }; 1181 1182 tdm_b_dout1_pins: tdm-b-dout1 { 1183 mux { 1184 groups = "tdm_b_dout1"; 1185 function = "tdm_b"; 1186 bias-disable; 1187 drive-strength-microamp = <3000>; 1188 }; 1189 }; 1190 1191 tdm_b_dout2_pins: tdm-b-dout2 { 1192 mux { 1193 groups = "tdm_b_dout2"; 1194 function = "tdm_b"; 1195 bias-disable; 1196 drive-strength-microamp = <3000>; 1197 }; 1198 }; 1199 1200 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1201 mux { 1202 groups = "tdm_b_dout3_a"; 1203 function = "tdm_b"; 1204 bias-disable; 1205 drive-strength-microamp = <3000>; 1206 }; 1207 }; 1208 1209 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1210 mux { 1211 groups = "tdm_b_dout3_h"; 1212 function = "tdm_b"; 1213 bias-disable; 1214 drive-strength-microamp = <3000>; 1215 }; 1216 }; 1217 1218 tdm_b_fs_pins: tdm-b-fs { 1219 mux { 1220 groups = "tdm_b_fs"; 1221 function = "tdm_b"; 1222 bias-disable; 1223 drive-strength-microamp = <3000>; 1224 }; 1225 }; 1226 1227 tdm_b_sclk_pins: tdm-b-sclk { 1228 mux { 1229 groups = "tdm_b_sclk"; 1230 function = "tdm_b"; 1231 bias-disable; 1232 drive-strength-microamp = <3000>; 1233 }; 1234 }; 1235 1236 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1237 mux { 1238 groups = "tdm_b_slv_fs"; 1239 function = "tdm_b"; 1240 bias-disable; 1241 }; 1242 }; 1243 1244 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1245 mux { 1246 groups = "tdm_b_slv_sclk"; 1247 function = "tdm_b"; 1248 bias-disable; 1249 }; 1250 }; 1251 1252 tdm_c_din0_a_pins: tdm-c-din0-a { 1253 mux { 1254 groups = "tdm_c_din0_a"; 1255 function = "tdm_c"; 1256 bias-disable; 1257 }; 1258 }; 1259 1260 tdm_c_din0_z_pins: tdm-c-din0-z { 1261 mux { 1262 groups = "tdm_c_din0_z"; 1263 function = "tdm_c"; 1264 bias-disable; 1265 }; 1266 }; 1267 1268 tdm_c_din1_a_pins: tdm-c-din1-a { 1269 mux { 1270 groups = "tdm_c_din1_a"; 1271 function = "tdm_c"; 1272 bias-disable; 1273 }; 1274 }; 1275 1276 tdm_c_din1_z_pins: tdm-c-din1-z { 1277 mux { 1278 groups = "tdm_c_din1_z"; 1279 function = "tdm_c"; 1280 bias-disable; 1281 }; 1282 }; 1283 1284 tdm_c_din2_a_pins: tdm-c-din2-a { 1285 mux { 1286 groups = "tdm_c_din2_a"; 1287 function = "tdm_c"; 1288 bias-disable; 1289 }; 1290 }; 1291 1292 eth_leds_pins: eth-leds { 1293 mux { 1294 groups = "eth_link_led", 1295 "eth_act_led"; 1296 function = "eth"; 1297 bias-disable; 1298 }; 1299 }; 1300 1301 eth_pins: eth { 1302 mux { 1303 groups = "eth_mdio", 1304 "eth_mdc", 1305 "eth_rgmii_rx_clk", 1306 "eth_rx_dv", 1307 "eth_rxd0", 1308 "eth_rxd1", 1309 "eth_txen", 1310 "eth_txd0", 1311 "eth_txd1"; 1312 function = "eth"; 1313 drive-strength-microamp = <4000>; 1314 bias-disable; 1315 }; 1316 }; 1317 1318 eth_rgmii_pins: eth-rgmii { 1319 mux { 1320 groups = "eth_rxd2_rgmii", 1321 "eth_rxd3_rgmii", 1322 "eth_rgmii_tx_clk", 1323 "eth_txd2_rgmii", 1324 "eth_txd3_rgmii"; 1325 function = "eth"; 1326 drive-strength-microamp = <4000>; 1327 bias-disable; 1328 }; 1329 }; 1330 1331 tdm_c_din2_z_pins: tdm-c-din2-z { 1332 mux { 1333 groups = "tdm_c_din2_z"; 1334 function = "tdm_c"; 1335 bias-disable; 1336 }; 1337 }; 1338 1339 tdm_c_din3_a_pins: tdm-c-din3-a { 1340 mux { 1341 groups = "tdm_c_din3_a"; 1342 function = "tdm_c"; 1343 bias-disable; 1344 }; 1345 }; 1346 1347 tdm_c_din3_z_pins: tdm-c-din3-z { 1348 mux { 1349 groups = "tdm_c_din3_z"; 1350 function = "tdm_c"; 1351 bias-disable; 1352 }; 1353 }; 1354 1355 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1356 mux { 1357 groups = "tdm_c_dout0_a"; 1358 function = "tdm_c"; 1359 bias-disable; 1360 drive-strength-microamp = <3000>; 1361 }; 1362 }; 1363 1364 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1365 mux { 1366 groups = "tdm_c_dout0_z"; 1367 function = "tdm_c"; 1368 bias-disable; 1369 drive-strength-microamp = <3000>; 1370 }; 1371 }; 1372 1373 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1374 mux { 1375 groups = "tdm_c_dout1_a"; 1376 function = "tdm_c"; 1377 bias-disable; 1378 drive-strength-microamp = <3000>; 1379 }; 1380 }; 1381 1382 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1383 mux { 1384 groups = "tdm_c_dout1_z"; 1385 function = "tdm_c"; 1386 bias-disable; 1387 drive-strength-microamp = <3000>; 1388 }; 1389 }; 1390 1391 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1392 mux { 1393 groups = "tdm_c_dout2_a"; 1394 function = "tdm_c"; 1395 bias-disable; 1396 drive-strength-microamp = <3000>; 1397 }; 1398 }; 1399 1400 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1401 mux { 1402 groups = "tdm_c_dout2_z"; 1403 function = "tdm_c"; 1404 bias-disable; 1405 drive-strength-microamp = <3000>; 1406 }; 1407 }; 1408 1409 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1410 mux { 1411 groups = "tdm_c_dout3_a"; 1412 function = "tdm_c"; 1413 bias-disable; 1414 drive-strength-microamp = <3000>; 1415 }; 1416 }; 1417 1418 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1419 mux { 1420 groups = "tdm_c_dout3_z"; 1421 function = "tdm_c"; 1422 bias-disable; 1423 drive-strength-microamp = <3000>; 1424 }; 1425 }; 1426 1427 tdm_c_fs_a_pins: tdm-c-fs-a { 1428 mux { 1429 groups = "tdm_c_fs_a"; 1430 function = "tdm_c"; 1431 bias-disable; 1432 drive-strength-microamp = <3000>; 1433 }; 1434 }; 1435 1436 tdm_c_fs_z_pins: tdm-c-fs-z { 1437 mux { 1438 groups = "tdm_c_fs_z"; 1439 function = "tdm_c"; 1440 bias-disable; 1441 drive-strength-microamp = <3000>; 1442 }; 1443 }; 1444 1445 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1446 mux { 1447 groups = "tdm_c_sclk_a"; 1448 function = "tdm_c"; 1449 bias-disable; 1450 drive-strength-microamp = <3000>; 1451 }; 1452 }; 1453 1454 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1455 mux { 1456 groups = "tdm_c_sclk_z"; 1457 function = "tdm_c"; 1458 bias-disable; 1459 drive-strength-microamp = <3000>; 1460 }; 1461 }; 1462 1463 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1464 mux { 1465 groups = "tdm_c_slv_fs_a"; 1466 function = "tdm_c"; 1467 bias-disable; 1468 }; 1469 }; 1470 1471 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1472 mux { 1473 groups = "tdm_c_slv_fs_z"; 1474 function = "tdm_c"; 1475 bias-disable; 1476 }; 1477 }; 1478 1479 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1480 mux { 1481 groups = "tdm_c_slv_sclk_a"; 1482 function = "tdm_c"; 1483 bias-disable; 1484 }; 1485 }; 1486 1487 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1488 mux { 1489 groups = "tdm_c_slv_sclk_z"; 1490 function = "tdm_c"; 1491 bias-disable; 1492 }; 1493 }; 1494 1495 uart_a_pins: uart-a { 1496 mux { 1497 groups = "uart_a_tx", 1498 "uart_a_rx"; 1499 function = "uart_a"; 1500 bias-disable; 1501 }; 1502 }; 1503 1504 uart_a_cts_rts_pins: uart-a-cts-rts { 1505 mux { 1506 groups = "uart_a_cts", 1507 "uart_a_rts"; 1508 function = "uart_a"; 1509 bias-disable; 1510 }; 1511 }; 1512 1513 uart_b_pins: uart-b { 1514 mux { 1515 groups = "uart_b_tx", 1516 "uart_b_rx"; 1517 function = "uart_b"; 1518 bias-disable; 1519 }; 1520 }; 1521 1522 uart_c_pins: uart-c { 1523 mux { 1524 groups = "uart_c_tx", 1525 "uart_c_rx"; 1526 function = "uart_c"; 1527 bias-disable; 1528 }; 1529 }; 1530 1531 uart_c_cts_rts_pins: uart-c-cts-rts { 1532 mux { 1533 groups = "uart_c_cts", 1534 "uart_c_rts"; 1535 function = "uart_c"; 1536 bias-disable; 1537 }; 1538 }; 1539 }; 1540 }; 1541 1542 cpu_temp: temperature-sensor@34800 { 1543 compatible = "amlogic,g12a-cpu-thermal", 1544 "amlogic,g12a-thermal"; 1545 reg = <0x0 0x34800 0x0 0x50>; 1546 interrupts = <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>; 1547 clocks = <&clkc CLKID_TS>; 1548 #thermal-sensor-cells = <0>; 1549 amlogic,ao-secure = <&sec_AO>; 1550 }; 1551 1552 ddr_temp: temperature-sensor@34c00 { 1553 compatible = "amlogic,g12a-ddr-thermal", 1554 "amlogic,g12a-thermal"; 1555 reg = <0x0 0x34c00 0x0 0x50>; 1556 interrupts = <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>; 1557 clocks = <&clkc CLKID_TS>; 1558 #thermal-sensor-cells = <0>; 1559 amlogic,ao-secure = <&sec_AO>; 1560 }; 1561 1562 usb2_phy0: phy@36000 { 1563 compatible = "amlogic,g12a-usb2-phy"; 1564 reg = <0x0 0x36000 0x0 0x2000>; 1565 clocks = <&xtal>; 1566 clock-names = "xtal"; 1567 resets = <&reset RESET_USB_PHY20>; 1568 reset-names = "phy"; 1569 #phy-cells = <0>; 1570 }; 1571 1572 dmc: bus@38000 { 1573 compatible = "simple-bus"; 1574 reg = <0x0 0x38000 0x0 0x400>; 1575 #address-cells = <2>; 1576 #size-cells = <2>; 1577 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1578 1579 canvas: video-lut@48 { 1580 compatible = "amlogic,canvas"; 1581 reg = <0x0 0x48 0x0 0x14>; 1582 }; 1583 }; 1584 1585 usb2_phy1: phy@3a000 { 1586 compatible = "amlogic,g12a-usb2-phy"; 1587 reg = <0x0 0x3a000 0x0 0x2000>; 1588 clocks = <&xtal>; 1589 clock-names = "xtal"; 1590 resets = <&reset RESET_USB_PHY21>; 1591 reset-names = "phy"; 1592 #phy-cells = <0>; 1593 }; 1594 1595 hiu: bus@3c000 { 1596 compatible = "simple-bus"; 1597 reg = <0x0 0x3c000 0x0 0x1400>; 1598 #address-cells = <2>; 1599 #size-cells = <2>; 1600 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1601 1602 hhi: system-controller@0 { 1603 compatible = "amlogic,meson-gx-hhi-sysctrl", 1604 "simple-mfd", "syscon"; 1605 reg = <0 0 0 0x400>; 1606 1607 clkc: clock-controller { 1608 compatible = "amlogic,g12a-clkc"; 1609 #clock-cells = <1>; 1610 clocks = <&xtal>; 1611 clock-names = "xtal"; 1612 }; 1613 1614 pwrc: power-controller { 1615 compatible = "amlogic,meson-g12a-pwrc"; 1616 #power-domain-cells = <1>; 1617 amlogic,ao-sysctrl = <&rti>; 1618 resets = <&reset RESET_VIU>, 1619 <&reset RESET_VENC>, 1620 <&reset RESET_VCBUS>, 1621 <&reset RESET_BT656>, 1622 <&reset RESET_RDMA>, 1623 <&reset RESET_VENCI>, 1624 <&reset RESET_VENCP>, 1625 <&reset RESET_VDAC>, 1626 <&reset RESET_VDI6>, 1627 <&reset RESET_VENCL>, 1628 <&reset RESET_VID_LOCK>; 1629 reset-names = "viu", "venc", "vcbus", "bt656", 1630 "rdma", "venci", "vencp", "vdac", 1631 "vdi6", "vencl", "vid_lock"; 1632 clocks = <&clkc CLKID_VPU>, 1633 <&clkc CLKID_VAPB>; 1634 clock-names = "vpu", "vapb"; 1635 /* 1636 * VPU clocking is provided by two identical clock paths 1637 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1638 * free mux to safely change frequency while running. 1639 * Same for VAPB but with a final gate after the glitch free mux. 1640 */ 1641 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1642 <&clkc CLKID_VPU_0>, 1643 <&clkc CLKID_VPU>, /* Glitch free mux */ 1644 <&clkc CLKID_VAPB_0_SEL>, 1645 <&clkc CLKID_VAPB_0>, 1646 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1647 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1648 <0>, /* Do Nothing */ 1649 <&clkc CLKID_VPU_0>, 1650 <&clkc CLKID_FCLK_DIV4>, 1651 <0>, /* Do Nothing */ 1652 <&clkc CLKID_VAPB_0>; 1653 assigned-clock-rates = <0>, /* Do Nothing */ 1654 <666666666>, 1655 <0>, /* Do Nothing */ 1656 <0>, /* Do Nothing */ 1657 <250000000>, 1658 <0>; /* Do Nothing */ 1659 }; 1660 }; 1661 }; 1662 1663 usb3_pcie_phy: phy@46000 { 1664 compatible = "amlogic,g12a-usb3-pcie-phy"; 1665 reg = <0x0 0x46000 0x0 0x2000>; 1666 clocks = <&clkc CLKID_PCIE_PLL>; 1667 clock-names = "ref_clk"; 1668 resets = <&reset RESET_PCIE_PHY>; 1669 reset-names = "phy"; 1670 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1671 assigned-clock-rates = <100000000>; 1672 #phy-cells = <1>; 1673 }; 1674 1675 eth_phy: mdio-multiplexer@4c000 { 1676 compatible = "amlogic,g12a-mdio-mux"; 1677 reg = <0x0 0x4c000 0x0 0xa4>; 1678 clocks = <&clkc CLKID_ETH_PHY>, 1679 <&xtal>, 1680 <&clkc CLKID_MPLL_50M>; 1681 clock-names = "pclk", "clkin0", "clkin1"; 1682 mdio-parent-bus = <&mdio0>; 1683 #address-cells = <1>; 1684 #size-cells = <0>; 1685 1686 ext_mdio: mdio@0 { 1687 reg = <0>; 1688 #address-cells = <1>; 1689 #size-cells = <0>; 1690 }; 1691 1692 int_mdio: mdio@1 { 1693 reg = <1>; 1694 #address-cells = <1>; 1695 #size-cells = <0>; 1696 1697 internal_ephy: ethernet_phy@8 { 1698 compatible = "ethernet-phy-id0180.3301", 1699 "ethernet-phy-ieee802.3-c22"; 1700 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1701 reg = <8>; 1702 max-speed = <100>; 1703 }; 1704 }; 1705 }; 1706 }; 1707 1708 pmu: pmu@ff638000 { 1709 reg = <0x0 0xff638000 0x0 0x100>, 1710 <0x0 0xff638c00 0x0 0x100>; 1711 interrupts = <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>; 1712 }; 1713 1714 aobus: bus@ff800000 { 1715 compatible = "simple-bus"; 1716 reg = <0x0 0xff800000 0x0 0x100000>; 1717 #address-cells = <2>; 1718 #size-cells = <2>; 1719 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1720 1721 rti: sys-ctrl@0 { 1722 compatible = "amlogic,meson-gx-ao-sysctrl", 1723 "simple-mfd", "syscon"; 1724 reg = <0x0 0x0 0x0 0x100>; 1725 #address-cells = <2>; 1726 #size-cells = <2>; 1727 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1728 1729 clkc_AO: clock-controller { 1730 compatible = "amlogic,meson-g12a-aoclkc"; 1731 #clock-cells = <1>; 1732 #reset-cells = <1>; 1733 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1734 clock-names = "xtal", "mpeg-clk"; 1735 }; 1736 1737 ao_pinctrl: pinctrl@14 { 1738 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1739 #address-cells = <2>; 1740 #size-cells = <2>; 1741 ranges; 1742 1743 gpio_ao: bank@14 { 1744 reg = <0x0 0x14 0x0 0x8>, 1745 <0x0 0x1c 0x0 0x8>, 1746 <0x0 0x24 0x0 0x14>; 1747 reg-names = "mux", 1748 "ds", 1749 "gpio"; 1750 gpio-controller; 1751 #gpio-cells = <2>; 1752 gpio-ranges = <&ao_pinctrl 0 0 15>; 1753 }; 1754 1755 i2c_ao_sck_pins: i2c_ao_sck_pins { 1756 mux { 1757 groups = "i2c_ao_sck"; 1758 function = "i2c_ao"; 1759 bias-disable; 1760 drive-strength-microamp = <3000>; 1761 }; 1762 }; 1763 1764 i2c_ao_sda_pins: i2c_ao_sda { 1765 mux { 1766 groups = "i2c_ao_sda"; 1767 function = "i2c_ao"; 1768 bias-disable; 1769 drive-strength-microamp = <3000>; 1770 }; 1771 }; 1772 1773 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1774 mux { 1775 groups = "i2c_ao_sck_e"; 1776 function = "i2c_ao"; 1777 bias-disable; 1778 drive-strength-microamp = <3000>; 1779 }; 1780 }; 1781 1782 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1783 mux { 1784 groups = "i2c_ao_sda_e"; 1785 function = "i2c_ao"; 1786 bias-disable; 1787 drive-strength-microamp = <3000>; 1788 }; 1789 }; 1790 1791 mclk0_ao_pins: mclk0-ao { 1792 mux { 1793 groups = "mclk0_ao"; 1794 function = "mclk0_ao"; 1795 bias-disable; 1796 drive-strength-microamp = <3000>; 1797 }; 1798 }; 1799 1800 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1801 mux { 1802 groups = "tdm_ao_b_din0"; 1803 function = "tdm_ao_b"; 1804 bias-disable; 1805 }; 1806 }; 1807 1808 spdif_ao_out_pins: spdif-ao-out { 1809 mux { 1810 groups = "spdif_ao_out"; 1811 function = "spdif_ao_out"; 1812 drive-strength-microamp = <500>; 1813 bias-disable; 1814 }; 1815 }; 1816 1817 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1818 mux { 1819 groups = "tdm_ao_b_din1"; 1820 function = "tdm_ao_b"; 1821 bias-disable; 1822 }; 1823 }; 1824 1825 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1826 mux { 1827 groups = "tdm_ao_b_din2"; 1828 function = "tdm_ao_b"; 1829 bias-disable; 1830 }; 1831 }; 1832 1833 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1834 mux { 1835 groups = "tdm_ao_b_dout0"; 1836 function = "tdm_ao_b"; 1837 bias-disable; 1838 drive-strength-microamp = <3000>; 1839 }; 1840 }; 1841 1842 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1843 mux { 1844 groups = "tdm_ao_b_dout1"; 1845 function = "tdm_ao_b"; 1846 bias-disable; 1847 drive-strength-microamp = <3000>; 1848 }; 1849 }; 1850 1851 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1852 mux { 1853 groups = "tdm_ao_b_dout2"; 1854 function = "tdm_ao_b"; 1855 bias-disable; 1856 drive-strength-microamp = <3000>; 1857 }; 1858 }; 1859 1860 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1861 mux { 1862 groups = "tdm_ao_b_fs"; 1863 function = "tdm_ao_b"; 1864 bias-disable; 1865 drive-strength-microamp = <3000>; 1866 }; 1867 }; 1868 1869 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1870 mux { 1871 groups = "tdm_ao_b_sclk"; 1872 function = "tdm_ao_b"; 1873 bias-disable; 1874 drive-strength-microamp = <3000>; 1875 }; 1876 }; 1877 1878 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1879 mux { 1880 groups = "tdm_ao_b_slv_fs"; 1881 function = "tdm_ao_b"; 1882 bias-disable; 1883 }; 1884 }; 1885 1886 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1887 mux { 1888 groups = "tdm_ao_b_slv_sclk"; 1889 function = "tdm_ao_b"; 1890 bias-disable; 1891 }; 1892 }; 1893 1894 uart_ao_a_pins: uart-a-ao { 1895 mux { 1896 groups = "uart_ao_a_tx", 1897 "uart_ao_a_rx"; 1898 function = "uart_ao_a"; 1899 bias-disable; 1900 }; 1901 }; 1902 1903 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 1904 mux { 1905 groups = "uart_ao_a_cts", 1906 "uart_ao_a_rts"; 1907 function = "uart_ao_a"; 1908 bias-disable; 1909 }; 1910 }; 1911 1912 uart_ao_b_2_3_pins: uart-ao-b-2-3 { 1913 mux { 1914 groups = "uart_ao_b_tx_2", 1915 "uart_ao_b_rx_3"; 1916 function = "uart_ao_b"; 1917 bias-disable; 1918 }; 1919 }; 1920 1921 uart_ao_b_8_9_pins: uart-ao-b-8-9 { 1922 mux { 1923 groups = "uart_ao_b_tx_8", 1924 "uart_ao_b_rx_9"; 1925 function = "uart_ao_b"; 1926 bias-disable; 1927 }; 1928 }; 1929 1930 uart_ao_b_cts_rts_pins: uart-ao-b-cts-rts { 1931 mux { 1932 groups = "uart_ao_b_cts", 1933 "uart_ao_b_rts"; 1934 function = "uart_ao_b"; 1935 bias-disable; 1936 }; 1937 }; 1938 1939 pwm_a_e_pins: pwm-a-e { 1940 mux { 1941 groups = "pwm_a_e"; 1942 function = "pwm_a_e"; 1943 bias-disable; 1944 }; 1945 }; 1946 1947 pwm_ao_a_pins: pwm-ao-a { 1948 mux { 1949 groups = "pwm_ao_a"; 1950 function = "pwm_ao_a"; 1951 bias-disable; 1952 }; 1953 }; 1954 1955 pwm_ao_b_pins: pwm-ao-b { 1956 mux { 1957 groups = "pwm_ao_b"; 1958 function = "pwm_ao_b"; 1959 bias-disable; 1960 }; 1961 }; 1962 1963 pwm_ao_c_4_pins: pwm-ao-c-4 { 1964 mux { 1965 groups = "pwm_ao_c_4"; 1966 function = "pwm_ao_c"; 1967 bias-disable; 1968 }; 1969 }; 1970 1971 pwm_ao_c_6_pins: pwm-ao-c-6 { 1972 mux { 1973 groups = "pwm_ao_c_6"; 1974 function = "pwm_ao_c"; 1975 bias-disable; 1976 }; 1977 }; 1978 1979 pwm_ao_d_5_pins: pwm-ao-d-5 { 1980 mux { 1981 groups = "pwm_ao_d_5"; 1982 function = "pwm_ao_d"; 1983 bias-disable; 1984 }; 1985 }; 1986 1987 pwm_ao_d_10_pins: pwm-ao-d-10 { 1988 mux { 1989 groups = "pwm_ao_d_10"; 1990 function = "pwm_ao_d"; 1991 bias-disable; 1992 }; 1993 }; 1994 1995 pwm_ao_d_e_pins: pwm-ao-d-e { 1996 mux { 1997 groups = "pwm_ao_d_e"; 1998 function = "pwm_ao_d"; 1999 }; 2000 }; 2001 2002 remote_input_ao_pins: remote-input-ao { 2003 mux { 2004 groups = "remote_ao_input"; 2005 function = "remote_ao_input"; 2006 bias-disable; 2007 }; 2008 }; 2009 }; 2010 }; 2011 2012 vrtc: rtc@a8 { 2013 compatible = "amlogic,meson-vrtc"; 2014 reg = <0x0 0x000a8 0x0 0x4>; 2015 }; 2016 2017 cec_AO: cec@100 { 2018 compatible = "amlogic,meson-gx-ao-cec"; 2019 reg = <0x0 0x00100 0x0 0x14>; 2020 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2021 clocks = <&clkc_AO CLKID_AO_CEC>; 2022 clock-names = "core"; 2023 status = "disabled"; 2024 }; 2025 2026 sec_AO: ao-secure@140 { 2027 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2028 reg = <0x0 0x140 0x0 0x140>; 2029 amlogic,has-chip-id; 2030 }; 2031 2032 cecb_AO: cec@280 { 2033 compatible = "amlogic,meson-g12a-ao-cec"; 2034 reg = <0x0 0x00280 0x0 0x1c>; 2035 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2036 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2037 clock-names = "oscin"; 2038 status = "disabled"; 2039 }; 2040 2041 pwm_AO_cd: pwm@2000 { 2042 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2043 reg = <0x0 0x2000 0x0 0x20>; 2044 #pwm-cells = <3>; 2045 status = "disabled"; 2046 }; 2047 2048 uart_AO: serial@3000 { 2049 compatible = "amlogic,meson-gx-uart", 2050 "amlogic,meson-ao-uart"; 2051 reg = <0x0 0x3000 0x0 0x18>; 2052 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2053 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2054 clock-names = "xtal", "pclk", "baud"; 2055 status = "disabled"; 2056 }; 2057 2058 uart_AO_B: serial@4000 { 2059 compatible = "amlogic,meson-gx-uart", 2060 "amlogic,meson-ao-uart"; 2061 reg = <0x0 0x4000 0x0 0x18>; 2062 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2063 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2064 clock-names = "xtal", "pclk", "baud"; 2065 status = "disabled"; 2066 }; 2067 2068 i2c_AO: i2c@5000 { 2069 compatible = "amlogic,meson-axg-i2c"; 2070 status = "disabled"; 2071 reg = <0x0 0x05000 0x0 0x20>; 2072 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 clocks = <&clkc CLKID_I2C>; 2076 }; 2077 2078 pwm_AO_ab: pwm@7000 { 2079 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2080 reg = <0x0 0x7000 0x0 0x20>; 2081 #pwm-cells = <3>; 2082 status = "disabled"; 2083 }; 2084 2085 ir: ir@8000 { 2086 compatible = "amlogic,meson-gxbb-ir"; 2087 reg = <0x0 0x8000 0x0 0x20>; 2088 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2089 status = "disabled"; 2090 }; 2091 2092 saradc: adc@9000 { 2093 compatible = "amlogic,meson-g12a-saradc", 2094 "amlogic,meson-saradc"; 2095 reg = <0x0 0x9000 0x0 0x48>; 2096 #io-channel-cells = <1>; 2097 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2098 clocks = <&xtal>, 2099 <&clkc_AO CLKID_AO_SAR_ADC>, 2100 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2101 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2102 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2103 status = "disabled"; 2104 }; 2105 }; 2106 2107 vdec: video-decoder@ff620000 { 2108 compatible = "amlogic,g12a-vdec"; 2109 reg = <0x0 0xff620000 0x0 0x10000>, 2110 <0x0 0xffd0e180 0x0 0xe4>; 2111 reg-names = "dos", "esparser"; 2112 interrupts = <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 2113 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>; 2114 interrupt-names = "vdec", "esparser"; 2115 2116 amlogic,ao-sysctrl = <&rti>; 2117 amlogic,canvas = <&canvas>; 2118 2119 clocks = <&clkc CLKID_PARSER>, 2120 <&clkc CLKID_DOS>, 2121 <&clkc CLKID_VDEC_1>, 2122 <&clkc CLKID_VDEC_HEVC>, 2123 <&clkc CLKID_VDEC_HEVCF>; 2124 clock-names = "dos_parser", "dos", "vdec_1", 2125 "vdec_hevc", "vdec_hevcf"; 2126 resets = <&reset RESET_PARSER>; 2127 reset-names = "esparser"; 2128 }; 2129 2130 vpu: vpu@ff900000 { 2131 compatible = "amlogic,meson-g12a-vpu"; 2132 reg = <0x0 0xff900000 0x0 0x100000>, 2133 <0x0 0xff63c000 0x0 0x1000>; 2134 reg-names = "vpu", "hhi"; 2135 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 amlogic,canvas = <&canvas>; 2139 2140 /* CVBS VDAC output port */ 2141 cvbs_vdac_port: port@0 { 2142 reg = <0>; 2143 }; 2144 2145 /* HDMI-TX output port */ 2146 hdmi_tx_port: port@1 { 2147 reg = <1>; 2148 2149 hdmi_tx_out: endpoint { 2150 remote-endpoint = <&hdmi_tx_in>; 2151 }; 2152 }; 2153 }; 2154 2155 gic: interrupt-controller@ffc01000 { 2156 compatible = "arm,gic-400"; 2157 reg = <0x0 0xffc01000 0 0x1000>, 2158 <0x0 0xffc02000 0 0x2000>, 2159 <0x0 0xffc04000 0 0x2000>, 2160 <0x0 0xffc06000 0 0x2000>; 2161 interrupt-controller; 2162 interrupts = <GIC_PPI 9 2163 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2164 #interrupt-cells = <3>; 2165 #address-cells = <0>; 2166 }; 2167 2168 cbus: bus@ffd00000 { 2169 compatible = "simple-bus"; 2170 reg = <0x0 0xffd00000 0x0 0x100000>; 2171 #address-cells = <2>; 2172 #size-cells = <2>; 2173 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2174 2175 reset: reset-controller@1004 { 2176 compatible = "amlogic,meson-axg-reset"; 2177 reg = <0x0 0x1004 0x0 0x9c>; 2178 #reset-cells = <1>; 2179 }; 2180 2181 gpio_intc: interrupt-controller@f080 { 2182 compatible = "amlogic,meson-g12a-gpio-intc", 2183 "amlogic,meson-gpio-intc"; 2184 reg = <0x0 0xf080 0x0 0x10>; 2185 interrupt-controller; 2186 #interrupt-cells = <2>; 2187 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2188 }; 2189 2190 watchdog: watchdog@f0d0 { 2191 compatible = "amlogic,meson-gxbb-wdt"; 2192 reg = <0x0 0xf0d0 0x0 0x10>; 2193 clocks = <&xtal>; 2194 }; 2195 2196 spicc0: spi@13000 { 2197 compatible = "amlogic,meson-g12a-spicc"; 2198 reg = <0x0 0x13000 0x0 0x44>; 2199 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 2200 clocks = <&clkc CLKID_SPICC0>, 2201 <&clkc CLKID_SPICC0_SCLK>; 2202 clock-names = "core", "pclk"; 2203 #address-cells = <1>; 2204 #size-cells = <0>; 2205 status = "disabled"; 2206 }; 2207 2208 spicc1: spi@15000 { 2209 compatible = "amlogic,meson-g12a-spicc"; 2210 reg = <0x0 0x15000 0x0 0x44>; 2211 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 2212 clocks = <&clkc CLKID_SPICC1>, 2213 <&clkc CLKID_SPICC1_SCLK>; 2214 clock-names = "core", "pclk"; 2215 #address-cells = <1>; 2216 #size-cells = <0>; 2217 status = "disabled"; 2218 }; 2219 2220 spifc: spi@14000 { 2221 compatible = "amlogic,meson-gxbb-spifc"; 2222 status = "disabled"; 2223 reg = <0x0 0x14000 0x0 0x80>; 2224 #address-cells = <1>; 2225 #size-cells = <0>; 2226 clocks = <&clkc CLKID_CLK81>; 2227 }; 2228 2229 pwm_ef: pwm@19000 { 2230 compatible = "amlogic,meson-g12a-ee-pwm"; 2231 reg = <0x0 0x19000 0x0 0x20>; 2232 #pwm-cells = <3>; 2233 status = "disabled"; 2234 }; 2235 2236 pwm_cd: pwm@1a000 { 2237 compatible = "amlogic,meson-g12a-ee-pwm"; 2238 reg = <0x0 0x1a000 0x0 0x20>; 2239 #pwm-cells = <3>; 2240 status = "disabled"; 2241 }; 2242 2243 pwm_ab: pwm@1b000 { 2244 compatible = "amlogic,meson-g12a-ee-pwm"; 2245 reg = <0x0 0x1b000 0x0 0x20>; 2246 #pwm-cells = <3>; 2247 status = "disabled"; 2248 }; 2249 2250 i2c3: i2c@1c000 { 2251 compatible = "amlogic,meson-axg-i2c"; 2252 status = "disabled"; 2253 reg = <0x0 0x1c000 0x0 0x20>; 2254 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2255 #address-cells = <1>; 2256 #size-cells = <0>; 2257 clocks = <&clkc CLKID_I2C>; 2258 }; 2259 2260 i2c2: i2c@1d000 { 2261 compatible = "amlogic,meson-axg-i2c"; 2262 status = "disabled"; 2263 reg = <0x0 0x1d000 0x0 0x20>; 2264 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2265 #address-cells = <1>; 2266 #size-cells = <0>; 2267 clocks = <&clkc CLKID_I2C>; 2268 }; 2269 2270 i2c1: i2c@1e000 { 2271 compatible = "amlogic,meson-axg-i2c"; 2272 status = "disabled"; 2273 reg = <0x0 0x1e000 0x0 0x20>; 2274 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2275 #address-cells = <1>; 2276 #size-cells = <0>; 2277 clocks = <&clkc CLKID_I2C>; 2278 }; 2279 2280 i2c0: i2c@1f000 { 2281 compatible = "amlogic,meson-axg-i2c"; 2282 status = "disabled"; 2283 reg = <0x0 0x1f000 0x0 0x20>; 2284 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2285 #address-cells = <1>; 2286 #size-cells = <0>; 2287 clocks = <&clkc CLKID_I2C>; 2288 }; 2289 2290 clk_msr: clock-measure@18000 { 2291 compatible = "amlogic,meson-g12a-clk-measure"; 2292 reg = <0x0 0x18000 0x0 0x10>; 2293 }; 2294 2295 uart_C: serial@22000 { 2296 compatible = "amlogic,meson-gx-uart"; 2297 reg = <0x0 0x22000 0x0 0x18>; 2298 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2299 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2300 clock-names = "xtal", "pclk", "baud"; 2301 status = "disabled"; 2302 }; 2303 2304 uart_B: serial@23000 { 2305 compatible = "amlogic,meson-gx-uart"; 2306 reg = <0x0 0x23000 0x0 0x18>; 2307 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2308 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2309 clock-names = "xtal", "pclk", "baud"; 2310 status = "disabled"; 2311 }; 2312 2313 uart_A: serial@24000 { 2314 compatible = "amlogic,meson-gx-uart"; 2315 reg = <0x0 0x24000 0x0 0x18>; 2316 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2317 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2318 clock-names = "xtal", "pclk", "baud"; 2319 status = "disabled"; 2320 fifo-size = <128>; 2321 }; 2322 }; 2323 2324 sd_emmc_a: sd@ffe03000 { 2325 compatible = "amlogic,meson-axg-mmc"; 2326 reg = <0x0 0xffe03000 0x0 0x800>; 2327 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; 2328 status = "disabled"; 2329 clocks = <&clkc CLKID_SD_EMMC_A>, 2330 <&clkc CLKID_SD_EMMC_A_CLK0>, 2331 <&clkc CLKID_FCLK_DIV2>; 2332 clock-names = "core", "clkin0", "clkin1"; 2333 resets = <&reset RESET_SD_EMMC_A>; 2334 }; 2335 2336 sd_emmc_b: sd@ffe05000 { 2337 compatible = "amlogic,meson-axg-mmc"; 2338 reg = <0x0 0xffe05000 0x0 0x800>; 2339 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2340 status = "disabled"; 2341 clocks = <&clkc CLKID_SD_EMMC_B>, 2342 <&clkc CLKID_SD_EMMC_B_CLK0>, 2343 <&clkc CLKID_FCLK_DIV2>; 2344 clock-names = "core", "clkin0", "clkin1"; 2345 resets = <&reset RESET_SD_EMMC_B>; 2346 }; 2347 2348 sd_emmc_c: mmc@ffe07000 { 2349 compatible = "amlogic,meson-axg-mmc"; 2350 reg = <0x0 0xffe07000 0x0 0x800>; 2351 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2352 status = "disabled"; 2353 clocks = <&clkc CLKID_SD_EMMC_C>, 2354 <&clkc CLKID_SD_EMMC_C_CLK0>, 2355 <&clkc CLKID_FCLK_DIV2>; 2356 clock-names = "core", "clkin0", "clkin1"; 2357 resets = <&reset RESET_SD_EMMC_C>; 2358 }; 2359 2360 usb: usb@ffe09000 { 2361 status = "disabled"; 2362 compatible = "amlogic,meson-g12a-usb-ctrl"; 2363 reg = <0x0 0xffe09000 0x0 0xa0>; 2364 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2365 #address-cells = <2>; 2366 #size-cells = <2>; 2367 ranges; 2368 2369 clocks = <&clkc CLKID_USB>; 2370 resets = <&reset RESET_USB>; 2371 2372 dr_mode = "otg"; 2373 2374 phys = <&usb2_phy0>, <&usb2_phy1>, 2375 <&usb3_pcie_phy PHY_TYPE_USB3>; 2376 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2377 2378 dwc2: usb@ff400000 { 2379 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2380 reg = <0x0 0xff400000 0x0 0x40000>; 2381 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2382 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2383 clock-names = "otg"; 2384 phys = <&usb2_phy1>; 2385 phy-names = "usb2-phy"; 2386 dr_mode = "peripheral"; 2387 g-rx-fifo-size = <192>; 2388 g-np-tx-fifo-size = <128>; 2389 g-tx-fifo-size = <128 128 16 16 16>; 2390 }; 2391 2392 dwc3: usb@ff500000 { 2393 compatible = "snps,dwc3"; 2394 reg = <0x0 0xff500000 0x0 0x100000>; 2395 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2396 dr_mode = "host"; 2397 snps,dis_u2_susphy_quirk; 2398 snps,quirk-frame-length-adjustment = <0x20>; 2399 snps,parkmode-disable-ss-quirk; 2400 }; 2401 }; 2402 2403 mali: gpu@ffe40000 { 2404 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2405 reg = <0x0 0xffe40000 0x0 0x40000>; 2406 interrupt-parent = <&gic>; 2407 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, 2408 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2409 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 2410 interrupt-names = "job", "mmu", "gpu"; 2411 clocks = <&clkc CLKID_MALI>; 2412 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2413 operating-points-v2 = <&gpu_opp_table>; 2414 #cooling-cells = <2>; 2415 }; 2416 }; 2417 2418 thermal-zones { 2419 cpu_thermal: cpu-thermal { 2420 polling-delay = <1000>; 2421 polling-delay-passive = <100>; 2422 thermal-sensors = <&cpu_temp>; 2423 2424 trips { 2425 cpu_passive: cpu-passive { 2426 temperature = <85000>; /* millicelsius */ 2427 hysteresis = <2000>; /* millicelsius */ 2428 type = "passive"; 2429 }; 2430 2431 cpu_hot: cpu-hot { 2432 temperature = <95000>; /* millicelsius */ 2433 hysteresis = <2000>; /* millicelsius */ 2434 type = "hot"; 2435 }; 2436 2437 cpu_critical: cpu-critical { 2438 temperature = <110000>; /* millicelsius */ 2439 hysteresis = <2000>; /* millicelsius */ 2440 type = "critical"; 2441 }; 2442 }; 2443 }; 2444 2445 ddr_thermal: ddr-thermal { 2446 polling-delay = <1000>; 2447 polling-delay-passive = <100>; 2448 thermal-sensors = <&ddr_temp>; 2449 2450 trips { 2451 ddr_passive: ddr-passive { 2452 temperature = <85000>; /* millicelsius */ 2453 hysteresis = <2000>; /* millicelsius */ 2454 type = "passive"; 2455 }; 2456 2457 ddr_critical: ddr-critical { 2458 temperature = <110000>; /* millicelsius */ 2459 hysteresis = <2000>; /* millicelsius */ 2460 type = "critical"; 2461 }; 2462 }; 2463 2464 cooling-maps { 2465 map { 2466 trip = <&ddr_passive>; 2467 cooling-device = <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2468 }; 2469 }; 2470 }; 2471 }; 2472 2473 timer { 2474 compatible = "arm,armv8-timer"; 2475 interrupts = <GIC_PPI 13 2476 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2477 <GIC_PPI 14 2478 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2479 <GIC_PPI 11 2480 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2481 <GIC_PPI 10 2482 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2483 arm,no-tick-in-suspend; 2484 }; 2485 2486 xtal: xtal-clk { 2487 compatible = "fixed-clock"; 2488 clock-frequency = <24000000>; 2489 clock-output-names = "xtal"; 2490 #clock-cells = <0>; 2491 }; 2492 2493}; 2494