1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/phy/phy.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/clock/axg-audio-clkc.h> 9#include <dt-bindings/clock/g12a-clkc.h> 10#include <dt-bindings/clock/g12a-aoclkc.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-g12a-audio-reset.h> 15#include <dt-bindings/reset/amlogic,meson-g12a-reset.h> 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 tdmif_a: audio-controller-0 { 23 compatible = "amlogic,axg-tdm-iface"; 24 #sound-dai-cells = <0>; 25 sound-name-prefix = "TDM_A"; 26 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 27 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 29 clock-names = "mclk", "sclk", "lrclk"; 30 status = "disabled"; 31 }; 32 33 tdmif_b: audio-controller-1 { 34 compatible = "amlogic,axg-tdm-iface"; 35 #sound-dai-cells = <0>; 36 sound-name-prefix = "TDM_B"; 37 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 38 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 40 clock-names = "mclk", "sclk", "lrclk"; 41 status = "disabled"; 42 }; 43 44 tdmif_c: audio-controller-2 { 45 compatible = "amlogic,axg-tdm-iface"; 46 #sound-dai-cells = <0>; 47 sound-name-prefix = "TDM_C"; 48 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 49 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 51 clock-names = "mclk", "sclk", "lrclk"; 52 status = "disabled"; 53 }; 54 55 efuse: efuse { 56 compatible = "amlogic,meson-gxbb-efuse"; 57 clocks = <&clkc CLKID_EFUSE>; 58 #address-cells = <1>; 59 #size-cells = <1>; 60 read-only; 61 }; 62 63 psci { 64 compatible = "arm,psci-1.0"; 65 method = "smc"; 66 }; 67 68 reserved-memory { 69 #address-cells = <2>; 70 #size-cells = <2>; 71 ranges; 72 73 /* 3 MiB reserved for ARM Trusted Firmware (BL31) */ 74 secmon_reserved: secmon@5000000 { 75 reg = <0x0 0x05000000 0x0 0x300000>; 76 no-map; 77 }; 78 79 linux,cma { 80 compatible = "shared-dma-pool"; 81 reusable; 82 size = <0x0 0x10000000>; 83 alignment = <0x0 0x400000>; 84 linux,cma-default; 85 }; 86 }; 87 88 sm: secure-monitor { 89 compatible = "amlogic,meson-gxbb-sm"; 90 }; 91 92 soc { 93 compatible = "simple-bus"; 94 #address-cells = <2>; 95 #size-cells = <2>; 96 ranges; 97 98 pcie: pcie@fc000000 { 99 compatible = "amlogic,g12a-pcie", "snps,dw-pcie"; 100 reg = <0x0 0xfc000000 0x0 0x400000 101 0x0 0xff648000 0x0 0x2000 102 0x0 0xfc400000 0x0 0x200000>; 103 reg-names = "elbi", "cfg", "config"; 104 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 105 #interrupt-cells = <1>; 106 interrupt-map-mask = <0 0 0 0>; 107 interrupt-map = <0 0 0 0 &gic GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 108 bus-range = <0x0 0xff>; 109 #address-cells = <3>; 110 #size-cells = <2>; 111 device_type = "pci"; 112 ranges = <0x81000000 0 0 0x0 0xfc600000 0 0x00100000 113 0x82000000 0 0xfc700000 0x0 0xfc700000 0 0x1900000>; 114 115 clocks = <&clkc CLKID_PCIE_PHY 116 &clkc CLKID_PCIE_COMB 117 &clkc CLKID_PCIE_PLL>; 118 clock-names = "general", 119 "pclk", 120 "port"; 121 resets = <&reset RESET_PCIE_CTRL_A>, 122 <&reset RESET_PCIE_APB>; 123 reset-names = "port", 124 "apb"; 125 num-lanes = <1>; 126 phys = <&usb3_pcie_phy PHY_TYPE_PCIE>; 127 phy-names = "pcie"; 128 status = "disabled"; 129 }; 130 131 ethmac: ethernet@ff3f0000 { 132 compatible = "amlogic,meson-axg-dwmac", 133 "snps,dwmac-3.70a", 134 "snps,dwmac"; 135 reg = <0x0 0xff3f0000 0x0 0x10000>, 136 <0x0 0xff634540 0x0 0x8>; 137 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 138 interrupt-names = "macirq"; 139 clocks = <&clkc CLKID_ETH>, 140 <&clkc CLKID_FCLK_DIV2>, 141 <&clkc CLKID_MPLL2>; 142 clock-names = "stmmaceth", "clkin0", "clkin1"; 143 rx-fifo-depth = <4096>; 144 tx-fifo-depth = <2048>; 145 status = "disabled"; 146 147 mdio0: mdio { 148 #address-cells = <1>; 149 #size-cells = <0>; 150 compatible = "snps,dwmac-mdio"; 151 }; 152 }; 153 154 apb: bus@ff600000 { 155 compatible = "simple-bus"; 156 reg = <0x0 0xff600000 0x0 0x200000>; 157 #address-cells = <2>; 158 #size-cells = <2>; 159 ranges = <0x0 0x0 0x0 0xff600000 0x0 0x200000>; 160 161 hdmi_tx: hdmi-tx@0 { 162 compatible = "amlogic,meson-g12a-dw-hdmi"; 163 reg = <0x0 0x0 0x0 0x10000>; 164 interrupts = <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>; 165 resets = <&reset RESET_HDMITX_CAPB3>, 166 <&reset RESET_HDMITX_PHY>, 167 <&reset RESET_HDMITX>; 168 reset-names = "hdmitx_apb", "hdmitx", "hdmitx_phy"; 169 clocks = <&clkc CLKID_HDMI>, 170 <&clkc CLKID_HTX_PCLK>, 171 <&clkc CLKID_VPU_INTR>; 172 clock-names = "isfr", "iahb", "venci"; 173 #address-cells = <1>; 174 #size-cells = <0>; 175 #sound-dai-cells = <0>; 176 status = "disabled"; 177 178 /* VPU VENC Input */ 179 hdmi_tx_venc_port: port@0 { 180 reg = <0>; 181 182 hdmi_tx_in: endpoint { 183 remote-endpoint = <&hdmi_tx_out>; 184 }; 185 }; 186 187 /* TMDS Output */ 188 hdmi_tx_tmds_port: port@1 { 189 reg = <1>; 190 }; 191 }; 192 193 apb_efuse: bus@30000 { 194 compatible = "simple-bus"; 195 reg = <0x0 0x30000 0x0 0x2000>; 196 #address-cells = <2>; 197 #size-cells = <2>; 198 ranges = <0x0 0x0 0x0 0x30000 0x0 0x2000>; 199 200 hwrng: rng@218 { 201 compatible = "amlogic,meson-rng"; 202 reg = <0x0 0x218 0x0 0x4>; 203 }; 204 }; 205 206 periphs: bus@34400 { 207 compatible = "simple-bus"; 208 reg = <0x0 0x34400 0x0 0x400>; 209 #address-cells = <2>; 210 #size-cells = <2>; 211 ranges = <0x0 0x0 0x0 0x34400 0x0 0x400>; 212 213 periphs_pinctrl: pinctrl@40 { 214 compatible = "amlogic,meson-g12a-periphs-pinctrl"; 215 #address-cells = <2>; 216 #size-cells = <2>; 217 ranges; 218 219 gpio: bank@40 { 220 reg = <0x0 0x40 0x0 0x4c>, 221 <0x0 0xe8 0x0 0x18>, 222 <0x0 0x120 0x0 0x18>, 223 <0x0 0x2c0 0x0 0x40>, 224 <0x0 0x340 0x0 0x1c>; 225 reg-names = "gpio", 226 "pull", 227 "pull-enable", 228 "mux", 229 "ds"; 230 gpio-controller; 231 #gpio-cells = <2>; 232 gpio-ranges = <&periphs_pinctrl 0 0 86>; 233 }; 234 235 cec_ao_a_h_pins: cec_ao_a_h { 236 mux { 237 groups = "cec_ao_a_h"; 238 function = "cec_ao_a_h"; 239 bias-disable; 240 }; 241 }; 242 243 cec_ao_b_h_pins: cec_ao_b_h { 244 mux { 245 groups = "cec_ao_b_h"; 246 function = "cec_ao_b_h"; 247 bias-disable; 248 }; 249 }; 250 251 emmc_pins: emmc { 252 mux-0 { 253 groups = "emmc_nand_d0", 254 "emmc_nand_d1", 255 "emmc_nand_d2", 256 "emmc_nand_d3", 257 "emmc_nand_d4", 258 "emmc_nand_d5", 259 "emmc_nand_d6", 260 "emmc_nand_d7", 261 "emmc_cmd"; 262 function = "emmc"; 263 bias-pull-up; 264 drive-strength-microamp = <4000>; 265 }; 266 267 mux-1 { 268 groups = "emmc_clk"; 269 function = "emmc"; 270 bias-disable; 271 drive-strength-microamp = <4000>; 272 }; 273 }; 274 275 emmc_ds_pins: emmc-ds { 276 mux { 277 groups = "emmc_nand_ds"; 278 function = "emmc"; 279 bias-pull-down; 280 drive-strength-microamp = <4000>; 281 }; 282 }; 283 284 emmc_clk_gate_pins: emmc_clk_gate { 285 mux { 286 groups = "BOOT_8"; 287 function = "gpio_periphs"; 288 bias-pull-down; 289 drive-strength-microamp = <4000>; 290 }; 291 }; 292 293 hdmitx_ddc_pins: hdmitx_ddc { 294 mux { 295 groups = "hdmitx_sda", 296 "hdmitx_sck"; 297 function = "hdmitx"; 298 bias-disable; 299 drive-strength-microamp = <4000>; 300 }; 301 }; 302 303 hdmitx_hpd_pins: hdmitx_hpd { 304 mux { 305 groups = "hdmitx_hpd_in"; 306 function = "hdmitx"; 307 bias-disable; 308 }; 309 }; 310 311 312 i2c0_sda_c_pins: i2c0-sda-c { 313 mux { 314 groups = "i2c0_sda_c"; 315 function = "i2c0"; 316 bias-disable; 317 drive-strength-microamp = <3000>; 318 319 }; 320 }; 321 322 i2c0_sck_c_pins: i2c0-sck-c { 323 mux { 324 groups = "i2c0_sck_c"; 325 function = "i2c0"; 326 bias-disable; 327 drive-strength-microamp = <3000>; 328 }; 329 }; 330 331 i2c0_sda_z0_pins: i2c0-sda-z0 { 332 mux { 333 groups = "i2c0_sda_z0"; 334 function = "i2c0"; 335 bias-disable; 336 drive-strength-microamp = <3000>; 337 }; 338 }; 339 340 i2c0_sck_z1_pins: i2c0-sck-z1 { 341 mux { 342 groups = "i2c0_sck_z1"; 343 function = "i2c0"; 344 bias-disable; 345 drive-strength-microamp = <3000>; 346 }; 347 }; 348 349 i2c0_sda_z7_pins: i2c0-sda-z7 { 350 mux { 351 groups = "i2c0_sda_z7"; 352 function = "i2c0"; 353 bias-disable; 354 drive-strength-microamp = <3000>; 355 }; 356 }; 357 358 i2c0_sda_z8_pins: i2c0-sda-z8 { 359 mux { 360 groups = "i2c0_sda_z8"; 361 function = "i2c0"; 362 bias-disable; 363 drive-strength-microamp = <3000>; 364 }; 365 }; 366 367 i2c1_sda_x_pins: i2c1-sda-x { 368 mux { 369 groups = "i2c1_sda_x"; 370 function = "i2c1"; 371 bias-disable; 372 drive-strength-microamp = <3000>; 373 }; 374 }; 375 376 i2c1_sck_x_pins: i2c1-sck-x { 377 mux { 378 groups = "i2c1_sck_x"; 379 function = "i2c1"; 380 bias-disable; 381 drive-strength-microamp = <3000>; 382 }; 383 }; 384 385 i2c1_sda_h2_pins: i2c1-sda-h2 { 386 mux { 387 groups = "i2c1_sda_h2"; 388 function = "i2c1"; 389 bias-disable; 390 drive-strength-microamp = <3000>; 391 }; 392 }; 393 394 i2c1_sck_h3_pins: i2c1-sck-h3 { 395 mux { 396 groups = "i2c1_sck_h3"; 397 function = "i2c1"; 398 bias-disable; 399 drive-strength-microamp = <3000>; 400 }; 401 }; 402 403 i2c1_sda_h6_pins: i2c1-sda-h6 { 404 mux { 405 groups = "i2c1_sda_h6"; 406 function = "i2c1"; 407 bias-disable; 408 drive-strength-microamp = <3000>; 409 }; 410 }; 411 412 i2c1_sck_h7_pins: i2c1-sck-h7 { 413 mux { 414 groups = "i2c1_sck_h7"; 415 function = "i2c1"; 416 bias-disable; 417 drive-strength-microamp = <3000>; 418 }; 419 }; 420 421 i2c2_sda_x_pins: i2c2-sda-x { 422 mux { 423 groups = "i2c2_sda_x"; 424 function = "i2c2"; 425 bias-disable; 426 drive-strength-microamp = <3000>; 427 }; 428 }; 429 430 i2c2_sck_x_pins: i2c2-sck-x { 431 mux { 432 groups = "i2c2_sck_x"; 433 function = "i2c2"; 434 bias-disable; 435 drive-strength-microamp = <3000>; 436 }; 437 }; 438 439 i2c2_sda_z_pins: i2c2-sda-z { 440 mux { 441 groups = "i2c2_sda_z"; 442 function = "i2c2"; 443 bias-disable; 444 drive-strength-microamp = <3000>; 445 }; 446 }; 447 448 i2c2_sck_z_pins: i2c2-sck-z { 449 mux { 450 groups = "i2c2_sck_z"; 451 function = "i2c2"; 452 bias-disable; 453 drive-strength-microamp = <3000>; 454 }; 455 }; 456 457 i2c3_sda_h_pins: i2c3-sda-h { 458 mux { 459 groups = "i2c3_sda_h"; 460 function = "i2c3"; 461 bias-disable; 462 drive-strength-microamp = <3000>; 463 }; 464 }; 465 466 i2c3_sck_h_pins: i2c3-sck-h { 467 mux { 468 groups = "i2c3_sck_h"; 469 function = "i2c3"; 470 bias-disable; 471 drive-strength-microamp = <3000>; 472 }; 473 }; 474 475 i2c3_sda_a_pins: i2c3-sda-a { 476 mux { 477 groups = "i2c3_sda_a"; 478 function = "i2c3"; 479 bias-disable; 480 drive-strength-microamp = <3000>; 481 }; 482 }; 483 484 i2c3_sck_a_pins: i2c3-sck-a { 485 mux { 486 groups = "i2c3_sck_a"; 487 function = "i2c3"; 488 bias-disable; 489 drive-strength-microamp = <3000>; 490 }; 491 }; 492 493 mclk0_a_pins: mclk0-a { 494 mux { 495 groups = "mclk0_a"; 496 function = "mclk0"; 497 bias-disable; 498 drive-strength-microamp = <3000>; 499 }; 500 }; 501 502 mclk1_a_pins: mclk1-a { 503 mux { 504 groups = "mclk1_a"; 505 function = "mclk1"; 506 bias-disable; 507 drive-strength-microamp = <3000>; 508 }; 509 }; 510 511 mclk1_x_pins: mclk1-x { 512 mux { 513 groups = "mclk1_x"; 514 function = "mclk1"; 515 bias-disable; 516 drive-strength-microamp = <3000>; 517 }; 518 }; 519 520 mclk1_z_pins: mclk1-z { 521 mux { 522 groups = "mclk1_z"; 523 function = "mclk1"; 524 bias-disable; 525 drive-strength-microamp = <3000>; 526 }; 527 }; 528 529 pdm_din0_a_pins: pdm-din0-a { 530 mux { 531 groups = "pdm_din0_a"; 532 function = "pdm"; 533 bias-disable; 534 }; 535 }; 536 537 pdm_din0_c_pins: pdm-din0-c { 538 mux { 539 groups = "pdm_din0_c"; 540 function = "pdm"; 541 bias-disable; 542 }; 543 }; 544 545 pdm_din0_x_pins: pdm-din0-x { 546 mux { 547 groups = "pdm_din0_x"; 548 function = "pdm"; 549 bias-disable; 550 }; 551 }; 552 553 pdm_din0_z_pins: pdm-din0-z { 554 mux { 555 groups = "pdm_din0_z"; 556 function = "pdm"; 557 bias-disable; 558 }; 559 }; 560 561 pdm_din1_a_pins: pdm-din1-a { 562 mux { 563 groups = "pdm_din1_a"; 564 function = "pdm"; 565 bias-disable; 566 }; 567 }; 568 569 pdm_din1_c_pins: pdm-din1-c { 570 mux { 571 groups = "pdm_din1_c"; 572 function = "pdm"; 573 bias-disable; 574 }; 575 }; 576 577 pdm_din1_x_pins: pdm-din1-x { 578 mux { 579 groups = "pdm_din1_x"; 580 function = "pdm"; 581 bias-disable; 582 }; 583 }; 584 585 pdm_din1_z_pins: pdm-din1-z { 586 mux { 587 groups = "pdm_din1_z"; 588 function = "pdm"; 589 bias-disable; 590 }; 591 }; 592 593 pdm_din2_a_pins: pdm-din2-a { 594 mux { 595 groups = "pdm_din2_a"; 596 function = "pdm"; 597 bias-disable; 598 }; 599 }; 600 601 pdm_din2_c_pins: pdm-din2-c { 602 mux { 603 groups = "pdm_din2_c"; 604 function = "pdm"; 605 bias-disable; 606 }; 607 }; 608 609 pdm_din2_x_pins: pdm-din2-x { 610 mux { 611 groups = "pdm_din2_x"; 612 function = "pdm"; 613 bias-disable; 614 }; 615 }; 616 617 pdm_din2_z_pins: pdm-din2-z { 618 mux { 619 groups = "pdm_din2_z"; 620 function = "pdm"; 621 bias-disable; 622 }; 623 }; 624 625 pdm_din3_a_pins: pdm-din3-a { 626 mux { 627 groups = "pdm_din3_a"; 628 function = "pdm"; 629 bias-disable; 630 }; 631 }; 632 633 pdm_din3_c_pins: pdm-din3-c { 634 mux { 635 groups = "pdm_din3_c"; 636 function = "pdm"; 637 bias-disable; 638 }; 639 }; 640 641 pdm_din3_x_pins: pdm-din3-x { 642 mux { 643 groups = "pdm_din3_x"; 644 function = "pdm"; 645 bias-disable; 646 }; 647 }; 648 649 pdm_din3_z_pins: pdm-din3-z { 650 mux { 651 groups = "pdm_din3_z"; 652 function = "pdm"; 653 bias-disable; 654 }; 655 }; 656 657 pdm_dclk_a_pins: pdm-dclk-a { 658 mux { 659 groups = "pdm_dclk_a"; 660 function = "pdm"; 661 bias-disable; 662 drive-strength-microamp = <500>; 663 }; 664 }; 665 666 pdm_dclk_c_pins: pdm-dclk-c { 667 mux { 668 groups = "pdm_dclk_c"; 669 function = "pdm"; 670 bias-disable; 671 drive-strength-microamp = <500>; 672 }; 673 }; 674 675 pdm_dclk_x_pins: pdm-dclk-x { 676 mux { 677 groups = "pdm_dclk_x"; 678 function = "pdm"; 679 bias-disable; 680 drive-strength-microamp = <500>; 681 }; 682 }; 683 684 pdm_dclk_z_pins: pdm-dclk-z { 685 mux { 686 groups = "pdm_dclk_z"; 687 function = "pdm"; 688 bias-disable; 689 drive-strength-microamp = <500>; 690 }; 691 }; 692 693 pwm_a_pins: pwm-a { 694 mux { 695 groups = "pwm_a"; 696 function = "pwm_a"; 697 bias-disable; 698 }; 699 }; 700 701 pwm_b_x7_pins: pwm-b-x7 { 702 mux { 703 groups = "pwm_b_x7"; 704 function = "pwm_b"; 705 bias-disable; 706 }; 707 }; 708 709 pwm_b_x19_pins: pwm-b-x19 { 710 mux { 711 groups = "pwm_b_x19"; 712 function = "pwm_b"; 713 bias-disable; 714 }; 715 }; 716 717 pwm_c_c_pins: pwm-c-c { 718 mux { 719 groups = "pwm_c_c"; 720 function = "pwm_c"; 721 bias-disable; 722 }; 723 }; 724 725 pwm_c_x5_pins: pwm-c-x5 { 726 mux { 727 groups = "pwm_c_x5"; 728 function = "pwm_c"; 729 bias-disable; 730 }; 731 }; 732 733 pwm_c_x8_pins: pwm-c-x8 { 734 mux { 735 groups = "pwm_c_x8"; 736 function = "pwm_c"; 737 bias-disable; 738 }; 739 }; 740 741 pwm_d_x3_pins: pwm-d-x3 { 742 mux { 743 groups = "pwm_d_x3"; 744 function = "pwm_d"; 745 bias-disable; 746 }; 747 }; 748 749 pwm_d_x6_pins: pwm-d-x6 { 750 mux { 751 groups = "pwm_d_x6"; 752 function = "pwm_d"; 753 bias-disable; 754 }; 755 }; 756 757 pwm_e_pins: pwm-e { 758 mux { 759 groups = "pwm_e"; 760 function = "pwm_e"; 761 bias-disable; 762 }; 763 }; 764 765 pwm_f_x_pins: pwm-f-x { 766 mux { 767 groups = "pwm_f_x"; 768 function = "pwm_f"; 769 bias-disable; 770 }; 771 }; 772 773 pwm_f_h_pins: pwm-f-h { 774 mux { 775 groups = "pwm_f_h"; 776 function = "pwm_f"; 777 bias-disable; 778 }; 779 }; 780 781 sdcard_c_pins: sdcard_c { 782 mux-0 { 783 groups = "sdcard_d0_c", 784 "sdcard_d1_c", 785 "sdcard_d2_c", 786 "sdcard_d3_c", 787 "sdcard_cmd_c"; 788 function = "sdcard"; 789 bias-pull-up; 790 drive-strength-microamp = <4000>; 791 }; 792 793 mux-1 { 794 groups = "sdcard_clk_c"; 795 function = "sdcard"; 796 bias-disable; 797 drive-strength-microamp = <4000>; 798 }; 799 }; 800 801 sdcard_clk_gate_c_pins: sdcard_clk_gate_c { 802 mux { 803 groups = "GPIOC_4"; 804 function = "gpio_periphs"; 805 bias-pull-down; 806 drive-strength-microamp = <4000>; 807 }; 808 }; 809 810 sdcard_z_pins: sdcard_z { 811 mux-0 { 812 groups = "sdcard_d0_z", 813 "sdcard_d1_z", 814 "sdcard_d2_z", 815 "sdcard_d3_z", 816 "sdcard_cmd_z"; 817 function = "sdcard"; 818 bias-pull-up; 819 drive-strength-microamp = <4000>; 820 }; 821 822 mux-1 { 823 groups = "sdcard_clk_z"; 824 function = "sdcard"; 825 bias-disable; 826 drive-strength-microamp = <4000>; 827 }; 828 }; 829 830 sdcard_clk_gate_z_pins: sdcard_clk_gate_z { 831 mux { 832 groups = "GPIOZ_6"; 833 function = "gpio_periphs"; 834 bias-pull-down; 835 drive-strength-microamp = <4000>; 836 }; 837 }; 838 839 sdio_pins: sdio { 840 mux { 841 groups = "sdio_d0", 842 "sdio_d1", 843 "sdio_d2", 844 "sdio_d3", 845 "sdio_clk", 846 "sdio_cmd"; 847 function = "sdio"; 848 bias-disable; 849 drive-strength-microamp = <4000>; 850 }; 851 }; 852 853 sdio_clk_gate_pins: sdio_clk_gate { 854 mux { 855 groups = "GPIOX_4"; 856 function = "gpio_periphs"; 857 bias-pull-down; 858 drive-strength-microamp = <4000>; 859 }; 860 }; 861 862 spdif_in_a10_pins: spdif-in-a10 { 863 mux { 864 groups = "spdif_in_a10"; 865 function = "spdif_in"; 866 bias-disable; 867 }; 868 }; 869 870 spdif_in_a12_pins: spdif-in-a12 { 871 mux { 872 groups = "spdif_in_a12"; 873 function = "spdif_in"; 874 bias-disable; 875 }; 876 }; 877 878 spdif_in_h_pins: spdif-in-h { 879 mux { 880 groups = "spdif_in_h"; 881 function = "spdif_in"; 882 bias-disable; 883 }; 884 }; 885 886 spdif_out_h_pins: spdif-out-h { 887 mux { 888 groups = "spdif_out_h"; 889 function = "spdif_out"; 890 drive-strength-microamp = <500>; 891 bias-disable; 892 }; 893 }; 894 895 spdif_out_a11_pins: spdif-out-a11 { 896 mux { 897 groups = "spdif_out_a11"; 898 function = "spdif_out"; 899 drive-strength-microamp = <500>; 900 bias-disable; 901 }; 902 }; 903 904 spdif_out_a13_pins: spdif-out-a13 { 905 mux { 906 groups = "spdif_out_a13"; 907 function = "spdif_out"; 908 drive-strength-microamp = <500>; 909 bias-disable; 910 }; 911 }; 912 913 tdm_a_din0_pins: tdm-a-din0 { 914 mux { 915 groups = "tdm_a_din0"; 916 function = "tdm_a"; 917 bias-disable; 918 }; 919 }; 920 921 922 tdm_a_din1_pins: tdm-a-din1 { 923 mux { 924 groups = "tdm_a_din1"; 925 function = "tdm_a"; 926 bias-disable; 927 }; 928 }; 929 930 tdm_a_dout0_pins: tdm-a-dout0 { 931 mux { 932 groups = "tdm_a_dout0"; 933 function = "tdm_a"; 934 bias-disable; 935 drive-strength-microamp = <3000>; 936 }; 937 }; 938 939 tdm_a_dout1_pins: tdm-a-dout1 { 940 mux { 941 groups = "tdm_a_dout1"; 942 function = "tdm_a"; 943 bias-disable; 944 drive-strength-microamp = <3000>; 945 }; 946 }; 947 948 tdm_a_fs_pins: tdm-a-fs { 949 mux { 950 groups = "tdm_a_fs"; 951 function = "tdm_a"; 952 bias-disable; 953 drive-strength-microamp = <3000>; 954 }; 955 }; 956 957 tdm_a_sclk_pins: tdm-a-sclk { 958 mux { 959 groups = "tdm_a_sclk"; 960 function = "tdm_a"; 961 bias-disable; 962 drive-strength-microamp = <3000>; 963 }; 964 }; 965 966 tdm_a_slv_fs_pins: tdm-a-slv-fs { 967 mux { 968 groups = "tdm_a_slv_fs"; 969 function = "tdm_a"; 970 bias-disable; 971 }; 972 }; 973 974 975 tdm_a_slv_sclk_pins: tdm-a-slv-sclk { 976 mux { 977 groups = "tdm_a_slv_sclk"; 978 function = "tdm_a"; 979 bias-disable; 980 }; 981 }; 982 983 tdm_b_din0_pins: tdm-b-din0 { 984 mux { 985 groups = "tdm_b_din0"; 986 function = "tdm_b"; 987 bias-disable; 988 }; 989 }; 990 991 tdm_b_din1_pins: tdm-b-din1 { 992 mux { 993 groups = "tdm_b_din1"; 994 function = "tdm_b"; 995 bias-disable; 996 }; 997 }; 998 999 tdm_b_din2_pins: tdm-b-din2 { 1000 mux { 1001 groups = "tdm_b_din2"; 1002 function = "tdm_b"; 1003 bias-disable; 1004 }; 1005 }; 1006 1007 tdm_b_din3_a_pins: tdm-b-din3-a { 1008 mux { 1009 groups = "tdm_b_din3_a"; 1010 function = "tdm_b"; 1011 bias-disable; 1012 }; 1013 }; 1014 1015 tdm_b_din3_h_pins: tdm-b-din3-h { 1016 mux { 1017 groups = "tdm_b_din3_h"; 1018 function = "tdm_b"; 1019 bias-disable; 1020 }; 1021 }; 1022 1023 tdm_b_dout0_pins: tdm-b-dout0 { 1024 mux { 1025 groups = "tdm_b_dout0"; 1026 function = "tdm_b"; 1027 bias-disable; 1028 drive-strength-microamp = <3000>; 1029 }; 1030 }; 1031 1032 tdm_b_dout1_pins: tdm-b-dout1 { 1033 mux { 1034 groups = "tdm_b_dout1"; 1035 function = "tdm_b"; 1036 bias-disable; 1037 drive-strength-microamp = <3000>; 1038 }; 1039 }; 1040 1041 tdm_b_dout2_pins: tdm-b-dout2 { 1042 mux { 1043 groups = "tdm_b_dout2"; 1044 function = "tdm_b"; 1045 bias-disable; 1046 drive-strength-microamp = <3000>; 1047 }; 1048 }; 1049 1050 tdm_b_dout3_a_pins: tdm-b-dout3-a { 1051 mux { 1052 groups = "tdm_b_dout3_a"; 1053 function = "tdm_b"; 1054 bias-disable; 1055 drive-strength-microamp = <3000>; 1056 }; 1057 }; 1058 1059 tdm_b_dout3_h_pins: tdm-b-dout3-h { 1060 mux { 1061 groups = "tdm_b_dout3_h"; 1062 function = "tdm_b"; 1063 bias-disable; 1064 drive-strength-microamp = <3000>; 1065 }; 1066 }; 1067 1068 tdm_b_fs_pins: tdm-b-fs { 1069 mux { 1070 groups = "tdm_b_fs"; 1071 function = "tdm_b"; 1072 bias-disable; 1073 drive-strength-microamp = <3000>; 1074 }; 1075 }; 1076 1077 tdm_b_sclk_pins: tdm-b-sclk { 1078 mux { 1079 groups = "tdm_b_sclk"; 1080 function = "tdm_b"; 1081 bias-disable; 1082 drive-strength-microamp = <3000>; 1083 }; 1084 }; 1085 1086 tdm_b_slv_fs_pins: tdm-b-slv-fs { 1087 mux { 1088 groups = "tdm_b_slv_fs"; 1089 function = "tdm_b"; 1090 bias-disable; 1091 }; 1092 }; 1093 1094 tdm_b_slv_sclk_pins: tdm-b-slv-sclk { 1095 mux { 1096 groups = "tdm_b_slv_sclk"; 1097 function = "tdm_b"; 1098 bias-disable; 1099 }; 1100 }; 1101 1102 tdm_c_din0_a_pins: tdm-c-din0-a { 1103 mux { 1104 groups = "tdm_c_din0_a"; 1105 function = "tdm_c"; 1106 bias-disable; 1107 }; 1108 }; 1109 1110 tdm_c_din0_z_pins: tdm-c-din0-z { 1111 mux { 1112 groups = "tdm_c_din0_z"; 1113 function = "tdm_c"; 1114 bias-disable; 1115 }; 1116 }; 1117 1118 tdm_c_din1_a_pins: tdm-c-din1-a { 1119 mux { 1120 groups = "tdm_c_din1_a"; 1121 function = "tdm_c"; 1122 bias-disable; 1123 }; 1124 }; 1125 1126 tdm_c_din1_z_pins: tdm-c-din1-z { 1127 mux { 1128 groups = "tdm_c_din1_z"; 1129 function = "tdm_c"; 1130 bias-disable; 1131 }; 1132 }; 1133 1134 tdm_c_din2_a_pins: tdm-c-din2-a { 1135 mux { 1136 groups = "tdm_c_din2_a"; 1137 function = "tdm_c"; 1138 bias-disable; 1139 }; 1140 }; 1141 1142 eth_leds_pins: eth-leds { 1143 mux { 1144 groups = "eth_link_led", 1145 "eth_act_led"; 1146 function = "eth"; 1147 bias-disable; 1148 }; 1149 }; 1150 1151 eth_pins: eth { 1152 mux { 1153 groups = "eth_mdio", 1154 "eth_mdc", 1155 "eth_rgmii_rx_clk", 1156 "eth_rx_dv", 1157 "eth_rxd0", 1158 "eth_rxd1", 1159 "eth_txen", 1160 "eth_txd0", 1161 "eth_txd1"; 1162 function = "eth"; 1163 drive-strength-microamp = <4000>; 1164 bias-disable; 1165 }; 1166 }; 1167 1168 eth_rgmii_pins: eth-rgmii { 1169 mux { 1170 groups = "eth_rxd2_rgmii", 1171 "eth_rxd3_rgmii", 1172 "eth_rgmii_tx_clk", 1173 "eth_txd2_rgmii", 1174 "eth_txd3_rgmii"; 1175 function = "eth"; 1176 drive-strength-microamp = <4000>; 1177 bias-disable; 1178 }; 1179 }; 1180 1181 tdm_c_din2_z_pins: tdm-c-din2-z { 1182 mux { 1183 groups = "tdm_c_din2_z"; 1184 function = "tdm_c"; 1185 bias-disable; 1186 }; 1187 }; 1188 1189 tdm_c_din3_a_pins: tdm-c-din3-a { 1190 mux { 1191 groups = "tdm_c_din3_a"; 1192 function = "tdm_c"; 1193 bias-disable; 1194 }; 1195 }; 1196 1197 tdm_c_din3_z_pins: tdm-c-din3-z { 1198 mux { 1199 groups = "tdm_c_din3_z"; 1200 function = "tdm_c"; 1201 bias-disable; 1202 }; 1203 }; 1204 1205 tdm_c_dout0_a_pins: tdm-c-dout0-a { 1206 mux { 1207 groups = "tdm_c_dout0_a"; 1208 function = "tdm_c"; 1209 bias-disable; 1210 drive-strength-microamp = <3000>; 1211 }; 1212 }; 1213 1214 tdm_c_dout0_z_pins: tdm-c-dout0-z { 1215 mux { 1216 groups = "tdm_c_dout0_z"; 1217 function = "tdm_c"; 1218 bias-disable; 1219 drive-strength-microamp = <3000>; 1220 }; 1221 }; 1222 1223 tdm_c_dout1_a_pins: tdm-c-dout1-a { 1224 mux { 1225 groups = "tdm_c_dout1_a"; 1226 function = "tdm_c"; 1227 bias-disable; 1228 drive-strength-microamp = <3000>; 1229 }; 1230 }; 1231 1232 tdm_c_dout1_z_pins: tdm-c-dout1-z { 1233 mux { 1234 groups = "tdm_c_dout1_z"; 1235 function = "tdm_c"; 1236 bias-disable; 1237 drive-strength-microamp = <3000>; 1238 }; 1239 }; 1240 1241 tdm_c_dout2_a_pins: tdm-c-dout2-a { 1242 mux { 1243 groups = "tdm_c_dout2_a"; 1244 function = "tdm_c"; 1245 bias-disable; 1246 drive-strength-microamp = <3000>; 1247 }; 1248 }; 1249 1250 tdm_c_dout2_z_pins: tdm-c-dout2-z { 1251 mux { 1252 groups = "tdm_c_dout2_z"; 1253 function = "tdm_c"; 1254 bias-disable; 1255 drive-strength-microamp = <3000>; 1256 }; 1257 }; 1258 1259 tdm_c_dout3_a_pins: tdm-c-dout3-a { 1260 mux { 1261 groups = "tdm_c_dout3_a"; 1262 function = "tdm_c"; 1263 bias-disable; 1264 drive-strength-microamp = <3000>; 1265 }; 1266 }; 1267 1268 tdm_c_dout3_z_pins: tdm-c-dout3-z { 1269 mux { 1270 groups = "tdm_c_dout3_z"; 1271 function = "tdm_c"; 1272 bias-disable; 1273 drive-strength-microamp = <3000>; 1274 }; 1275 }; 1276 1277 tdm_c_fs_a_pins: tdm-c-fs-a { 1278 mux { 1279 groups = "tdm_c_fs_a"; 1280 function = "tdm_c"; 1281 bias-disable; 1282 drive-strength-microamp = <3000>; 1283 }; 1284 }; 1285 1286 tdm_c_fs_z_pins: tdm-c-fs-z { 1287 mux { 1288 groups = "tdm_c_fs_z"; 1289 function = "tdm_c"; 1290 bias-disable; 1291 drive-strength-microamp = <3000>; 1292 }; 1293 }; 1294 1295 tdm_c_sclk_a_pins: tdm-c-sclk-a { 1296 mux { 1297 groups = "tdm_c_sclk_a"; 1298 function = "tdm_c"; 1299 bias-disable; 1300 drive-strength-microamp = <3000>; 1301 }; 1302 }; 1303 1304 tdm_c_sclk_z_pins: tdm-c-sclk-z { 1305 mux { 1306 groups = "tdm_c_sclk_z"; 1307 function = "tdm_c"; 1308 bias-disable; 1309 drive-strength-microamp = <3000>; 1310 }; 1311 }; 1312 1313 tdm_c_slv_fs_a_pins: tdm-c-slv-fs-a { 1314 mux { 1315 groups = "tdm_c_slv_fs_a"; 1316 function = "tdm_c"; 1317 bias-disable; 1318 }; 1319 }; 1320 1321 tdm_c_slv_fs_z_pins: tdm-c-slv-fs-z { 1322 mux { 1323 groups = "tdm_c_slv_fs_z"; 1324 function = "tdm_c"; 1325 bias-disable; 1326 }; 1327 }; 1328 1329 tdm_c_slv_sclk_a_pins: tdm-c-slv-sclk-a { 1330 mux { 1331 groups = "tdm_c_slv_sclk_a"; 1332 function = "tdm_c"; 1333 bias-disable; 1334 }; 1335 }; 1336 1337 tdm_c_slv_sclk_z_pins: tdm-c-slv-sclk-z { 1338 mux { 1339 groups = "tdm_c_slv_sclk_z"; 1340 function = "tdm_c"; 1341 bias-disable; 1342 }; 1343 }; 1344 1345 uart_a_pins: uart-a { 1346 mux { 1347 groups = "uart_a_tx", 1348 "uart_a_rx"; 1349 function = "uart_a"; 1350 bias-disable; 1351 }; 1352 }; 1353 1354 uart_a_cts_rts_pins: uart-a-cts-rts { 1355 mux { 1356 groups = "uart_a_cts", 1357 "uart_a_rts"; 1358 function = "uart_a"; 1359 bias-disable; 1360 }; 1361 }; 1362 1363 uart_b_pins: uart-b { 1364 mux { 1365 groups = "uart_b_tx", 1366 "uart_b_rx"; 1367 function = "uart_b"; 1368 bias-disable; 1369 }; 1370 }; 1371 1372 uart_c_pins: uart-c { 1373 mux { 1374 groups = "uart_c_tx", 1375 "uart_c_rx"; 1376 function = "uart_c"; 1377 bias-disable; 1378 }; 1379 }; 1380 1381 uart_c_cts_rts_pins: uart-c-cts-rts { 1382 mux { 1383 groups = "uart_c_cts", 1384 "uart_c_rts"; 1385 function = "uart_c"; 1386 bias-disable; 1387 }; 1388 }; 1389 }; 1390 }; 1391 1392 usb2_phy0: phy@36000 { 1393 compatible = "amlogic,g12a-usb2-phy"; 1394 reg = <0x0 0x36000 0x0 0x2000>; 1395 clocks = <&xtal>; 1396 clock-names = "xtal"; 1397 resets = <&reset RESET_USB_PHY20>; 1398 reset-names = "phy"; 1399 #phy-cells = <0>; 1400 }; 1401 1402 dmc: bus@38000 { 1403 compatible = "simple-bus"; 1404 reg = <0x0 0x38000 0x0 0x400>; 1405 #address-cells = <2>; 1406 #size-cells = <2>; 1407 ranges = <0x0 0x0 0x0 0x38000 0x0 0x400>; 1408 1409 canvas: video-lut@48 { 1410 compatible = "amlogic,canvas"; 1411 reg = <0x0 0x48 0x0 0x14>; 1412 }; 1413 }; 1414 1415 usb2_phy1: phy@3a000 { 1416 compatible = "amlogic,g12a-usb2-phy"; 1417 reg = <0x0 0x3a000 0x0 0x2000>; 1418 clocks = <&xtal>; 1419 clock-names = "xtal"; 1420 resets = <&reset RESET_USB_PHY21>; 1421 reset-names = "phy"; 1422 #phy-cells = <0>; 1423 }; 1424 1425 hiu: bus@3c000 { 1426 compatible = "simple-bus"; 1427 reg = <0x0 0x3c000 0x0 0x1400>; 1428 #address-cells = <2>; 1429 #size-cells = <2>; 1430 ranges = <0x0 0x0 0x0 0x3c000 0x0 0x1400>; 1431 1432 hhi: system-controller@0 { 1433 compatible = "amlogic,meson-gx-hhi-sysctrl", 1434 "simple-mfd", "syscon"; 1435 reg = <0 0 0 0x400>; 1436 1437 clkc: clock-controller { 1438 compatible = "amlogic,g12a-clkc"; 1439 #clock-cells = <1>; 1440 clocks = <&xtal>; 1441 clock-names = "xtal"; 1442 }; 1443 1444 pwrc: power-controller { 1445 compatible = "amlogic,meson-g12a-pwrc"; 1446 #power-domain-cells = <1>; 1447 amlogic,ao-sysctrl = <&rti>; 1448 resets = <&reset RESET_VIU>, 1449 <&reset RESET_VENC>, 1450 <&reset RESET_VCBUS>, 1451 <&reset RESET_BT656>, 1452 <&reset RESET_RDMA>, 1453 <&reset RESET_VENCI>, 1454 <&reset RESET_VENCP>, 1455 <&reset RESET_VDAC>, 1456 <&reset RESET_VDI6>, 1457 <&reset RESET_VENCL>, 1458 <&reset RESET_VID_LOCK>; 1459 reset-names = "viu", "venc", "vcbus", "bt656", 1460 "rdma", "venci", "vencp", "vdac", 1461 "vdi6", "vencl", "vid_lock"; 1462 clocks = <&clkc CLKID_VPU>, 1463 <&clkc CLKID_VAPB>; 1464 clock-names = "vpu", "vapb"; 1465 /* 1466 * VPU clocking is provided by two identical clock paths 1467 * VPU_0 and VPU_1 muxed to a single clock by a glitch 1468 * free mux to safely change frequency while running. 1469 * Same for VAPB but with a final gate after the glitch free mux. 1470 */ 1471 assigned-clocks = <&clkc CLKID_VPU_0_SEL>, 1472 <&clkc CLKID_VPU_0>, 1473 <&clkc CLKID_VPU>, /* Glitch free mux */ 1474 <&clkc CLKID_VAPB_0_SEL>, 1475 <&clkc CLKID_VAPB_0>, 1476 <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */ 1477 assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>, 1478 <0>, /* Do Nothing */ 1479 <&clkc CLKID_VPU_0>, 1480 <&clkc CLKID_FCLK_DIV4>, 1481 <0>, /* Do Nothing */ 1482 <&clkc CLKID_VAPB_0>; 1483 assigned-clock-rates = <0>, /* Do Nothing */ 1484 <666666666>, 1485 <0>, /* Do Nothing */ 1486 <0>, /* Do Nothing */ 1487 <250000000>, 1488 <0>; /* Do Nothing */ 1489 }; 1490 }; 1491 }; 1492 1493 pdm: audio-controller@40000 { 1494 compatible = "amlogic,g12a-pdm", 1495 "amlogic,axg-pdm"; 1496 reg = <0x0 0x40000 0x0 0x34>; 1497 #sound-dai-cells = <0>; 1498 sound-name-prefix = "PDM"; 1499 clocks = <&clkc_audio AUD_CLKID_PDM>, 1500 <&clkc_audio AUD_CLKID_PDM_DCLK>, 1501 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 1502 clock-names = "pclk", "dclk", "sysclk"; 1503 status = "disabled"; 1504 }; 1505 1506 audio: bus@42000 { 1507 compatible = "simple-bus"; 1508 reg = <0x0 0x42000 0x0 0x2000>; 1509 #address-cells = <2>; 1510 #size-cells = <2>; 1511 ranges = <0x0 0x0 0x0 0x42000 0x0 0x2000>; 1512 1513 clkc_audio: clock-controller@0 { 1514 status = "disabled"; 1515 compatible = "amlogic,g12a-audio-clkc"; 1516 reg = <0x0 0x0 0x0 0xb4>; 1517 #clock-cells = <1>; 1518 #reset-cells = <1>; 1519 1520 clocks = <&clkc CLKID_AUDIO>, 1521 <&clkc CLKID_MPLL0>, 1522 <&clkc CLKID_MPLL1>, 1523 <&clkc CLKID_MPLL2>, 1524 <&clkc CLKID_MPLL3>, 1525 <&clkc CLKID_HIFI_PLL>, 1526 <&clkc CLKID_FCLK_DIV3>, 1527 <&clkc CLKID_FCLK_DIV4>, 1528 <&clkc CLKID_GP0_PLL>; 1529 clock-names = "pclk", 1530 "mst_in0", 1531 "mst_in1", 1532 "mst_in2", 1533 "mst_in3", 1534 "mst_in4", 1535 "mst_in5", 1536 "mst_in6", 1537 "mst_in7"; 1538 1539 resets = <&reset RESET_AUDIO>; 1540 }; 1541 1542 toddr_a: audio-controller@100 { 1543 compatible = "amlogic,g12a-toddr", 1544 "amlogic,axg-toddr"; 1545 reg = <0x0 0x100 0x0 0x1c>; 1546 #sound-dai-cells = <0>; 1547 sound-name-prefix = "TODDR_A"; 1548 interrupts = <GIC_SPI 148 IRQ_TYPE_EDGE_RISING>; 1549 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1550 resets = <&arb AXG_ARB_TODDR_A>; 1551 status = "disabled"; 1552 }; 1553 1554 toddr_b: audio-controller@140 { 1555 compatible = "amlogic,g12a-toddr", 1556 "amlogic,axg-toddr"; 1557 reg = <0x0 0x140 0x0 0x1c>; 1558 #sound-dai-cells = <0>; 1559 sound-name-prefix = "TODDR_B"; 1560 interrupts = <GIC_SPI 149 IRQ_TYPE_EDGE_RISING>; 1561 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1562 resets = <&arb AXG_ARB_TODDR_B>; 1563 status = "disabled"; 1564 }; 1565 1566 toddr_c: audio-controller@180 { 1567 compatible = "amlogic,g12a-toddr", 1568 "amlogic,axg-toddr"; 1569 reg = <0x0 0x180 0x0 0x1c>; 1570 #sound-dai-cells = <0>; 1571 sound-name-prefix = "TODDR_C"; 1572 interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; 1573 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1574 resets = <&arb AXG_ARB_TODDR_C>; 1575 status = "disabled"; 1576 }; 1577 1578 frddr_a: audio-controller@1c0 { 1579 compatible = "amlogic,g12a-frddr", 1580 "amlogic,axg-frddr"; 1581 reg = <0x0 0x1c0 0x0 0x1c>; 1582 #sound-dai-cells = <0>; 1583 sound-name-prefix = "FRDDR_A"; 1584 interrupts = <GIC_SPI 152 IRQ_TYPE_EDGE_RISING>; 1585 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1586 resets = <&arb AXG_ARB_FRDDR_A>; 1587 status = "disabled"; 1588 }; 1589 1590 frddr_b: audio-controller@200 { 1591 compatible = "amlogic,g12a-frddr", 1592 "amlogic,axg-frddr"; 1593 reg = <0x0 0x200 0x0 0x1c>; 1594 #sound-dai-cells = <0>; 1595 sound-name-prefix = "FRDDR_B"; 1596 interrupts = <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>; 1597 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1598 resets = <&arb AXG_ARB_FRDDR_B>; 1599 status = "disabled"; 1600 }; 1601 1602 frddr_c: audio-controller@240 { 1603 compatible = "amlogic,g12a-frddr", 1604 "amlogic,axg-frddr"; 1605 reg = <0x0 0x240 0x0 0x1c>; 1606 #sound-dai-cells = <0>; 1607 sound-name-prefix = "FRDDR_C"; 1608 interrupts = <GIC_SPI 154 IRQ_TYPE_EDGE_RISING>; 1609 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1610 resets = <&arb AXG_ARB_FRDDR_C>; 1611 status = "disabled"; 1612 }; 1613 1614 arb: reset-controller@280 { 1615 status = "disabled"; 1616 compatible = "amlogic,meson-axg-audio-arb"; 1617 reg = <0x0 0x280 0x0 0x4>; 1618 #reset-cells = <1>; 1619 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1620 }; 1621 1622 tdmin_a: audio-controller@300 { 1623 compatible = "amlogic,g12a-tdmin", 1624 "amlogic,axg-tdmin"; 1625 reg = <0x0 0x300 0x0 0x40>; 1626 sound-name-prefix = "TDMIN_A"; 1627 resets = <&clkc_audio AUD_RESET_TDMIN_A>; 1628 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1629 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1630 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1631 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1632 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1633 clock-names = "pclk", "sclk", "sclk_sel", 1634 "lrclk", "lrclk_sel"; 1635 status = "disabled"; 1636 }; 1637 1638 tdmin_b: audio-controller@340 { 1639 compatible = "amlogic,g12a-tdmin", 1640 "amlogic,axg-tdmin"; 1641 reg = <0x0 0x340 0x0 0x40>; 1642 sound-name-prefix = "TDMIN_B"; 1643 resets = <&clkc_audio AUD_RESET_TDMIN_B>; 1644 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1645 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1646 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1647 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1648 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1649 clock-names = "pclk", "sclk", "sclk_sel", 1650 "lrclk", "lrclk_sel"; 1651 status = "disabled"; 1652 }; 1653 1654 tdmin_c: audio-controller@380 { 1655 compatible = "amlogic,g12a-tdmin", 1656 "amlogic,axg-tdmin"; 1657 reg = <0x0 0x380 0x0 0x40>; 1658 sound-name-prefix = "TDMIN_C"; 1659 resets = <&clkc_audio AUD_RESET_TDMIN_C>; 1660 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1661 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1662 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1663 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1664 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1665 clock-names = "pclk", "sclk", "sclk_sel", 1666 "lrclk", "lrclk_sel"; 1667 status = "disabled"; 1668 }; 1669 1670 tdmin_lb: audio-controller@3c0 { 1671 compatible = "amlogic,g12a-tdmin", 1672 "amlogic,axg-tdmin"; 1673 reg = <0x0 0x3c0 0x0 0x40>; 1674 sound-name-prefix = "TDMIN_LB"; 1675 resets = <&clkc_audio AUD_RESET_TDMIN_LB>; 1676 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1677 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1678 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1679 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1680 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1681 clock-names = "pclk", "sclk", "sclk_sel", 1682 "lrclk", "lrclk_sel"; 1683 status = "disabled"; 1684 }; 1685 1686 spdifin: audio-controller@400 { 1687 compatible = "amlogic,g12a-spdifin", 1688 "amlogic,axg-spdifin"; 1689 reg = <0x0 0x400 0x0 0x30>; 1690 #sound-dai-cells = <0>; 1691 sound-name-prefix = "SPDIFIN"; 1692 interrupts = <GIC_SPI 151 IRQ_TYPE_EDGE_RISING>; 1693 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1694 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1695 clock-names = "pclk", "refclk"; 1696 status = "disabled"; 1697 }; 1698 1699 spdifout: audio-controller@480 { 1700 compatible = "amlogic,g12a-spdifout", 1701 "amlogic,axg-spdifout"; 1702 reg = <0x0 0x480 0x0 0x50>; 1703 #sound-dai-cells = <0>; 1704 sound-name-prefix = "SPDIFOUT"; 1705 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1706 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1707 clock-names = "pclk", "mclk"; 1708 status = "disabled"; 1709 }; 1710 1711 tdmout_a: audio-controller@500 { 1712 compatible = "amlogic,g12a-tdmout"; 1713 reg = <0x0 0x500 0x0 0x40>; 1714 sound-name-prefix = "TDMOUT_A"; 1715 resets = <&clkc_audio AUD_RESET_TDMOUT_A>; 1716 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1717 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1718 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1719 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1720 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1721 clock-names = "pclk", "sclk", "sclk_sel", 1722 "lrclk", "lrclk_sel"; 1723 status = "disabled"; 1724 }; 1725 1726 tdmout_b: audio-controller@540 { 1727 compatible = "amlogic,g12a-tdmout"; 1728 reg = <0x0 0x540 0x0 0x40>; 1729 sound-name-prefix = "TDMOUT_B"; 1730 resets = <&clkc_audio AUD_RESET_TDMOUT_B>; 1731 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1732 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1733 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1734 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1735 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1736 clock-names = "pclk", "sclk", "sclk_sel", 1737 "lrclk", "lrclk_sel"; 1738 status = "disabled"; 1739 }; 1740 1741 tdmout_c: audio-controller@580 { 1742 compatible = "amlogic,g12a-tdmout"; 1743 reg = <0x0 0x580 0x0 0x40>; 1744 sound-name-prefix = "TDMOUT_C"; 1745 resets = <&clkc_audio AUD_RESET_TDMOUT_C>; 1746 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1747 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1748 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1749 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1750 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1751 clock-names = "pclk", "sclk", "sclk_sel", 1752 "lrclk", "lrclk_sel"; 1753 status = "disabled"; 1754 }; 1755 1756 spdifout_b: audio-controller@680 { 1757 compatible = "amlogic,g12a-spdifout", 1758 "amlogic,axg-spdifout"; 1759 reg = <0x0 0x680 0x0 0x50>; 1760 #sound-dai-cells = <0>; 1761 sound-name-prefix = "SPDIFOUT_B"; 1762 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT_B>, 1763 <&clkc_audio AUD_CLKID_SPDIFOUT_B_CLK>; 1764 clock-names = "pclk", "mclk"; 1765 status = "disabled"; 1766 }; 1767 1768 tohdmitx: audio-controller@744 { 1769 compatible = "amlogic,g12a-tohdmitx"; 1770 reg = <0x0 0x744 0x0 0x4>; 1771 #sound-dai-cells = <1>; 1772 sound-name-prefix = "TOHDMITX"; 1773 status = "disabled"; 1774 }; 1775 }; 1776 1777 usb3_pcie_phy: phy@46000 { 1778 compatible = "amlogic,g12a-usb3-pcie-phy"; 1779 reg = <0x0 0x46000 0x0 0x2000>; 1780 clocks = <&clkc CLKID_PCIE_PLL>; 1781 clock-names = "ref_clk"; 1782 resets = <&reset RESET_PCIE_PHY>; 1783 reset-names = "phy"; 1784 assigned-clocks = <&clkc CLKID_PCIE_PLL>; 1785 assigned-clock-rates = <100000000>; 1786 #phy-cells = <1>; 1787 }; 1788 1789 eth_phy: mdio-multiplexer@4c000 { 1790 compatible = "amlogic,g12a-mdio-mux"; 1791 reg = <0x0 0x4c000 0x0 0xa4>; 1792 clocks = <&clkc CLKID_ETH_PHY>, 1793 <&xtal>, 1794 <&clkc CLKID_MPLL_50M>; 1795 clock-names = "pclk", "clkin0", "clkin1"; 1796 mdio-parent-bus = <&mdio0>; 1797 #address-cells = <1>; 1798 #size-cells = <0>; 1799 1800 ext_mdio: mdio@0 { 1801 reg = <0>; 1802 #address-cells = <1>; 1803 #size-cells = <0>; 1804 }; 1805 1806 int_mdio: mdio@1 { 1807 reg = <1>; 1808 #address-cells = <1>; 1809 #size-cells = <0>; 1810 1811 internal_ephy: ethernet_phy@8 { 1812 compatible = "ethernet-phy-id0180.3301", 1813 "ethernet-phy-ieee802.3-c22"; 1814 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1815 reg = <8>; 1816 max-speed = <100>; 1817 }; 1818 }; 1819 }; 1820 }; 1821 1822 aobus: bus@ff800000 { 1823 compatible = "simple-bus"; 1824 reg = <0x0 0xff800000 0x0 0x100000>; 1825 #address-cells = <2>; 1826 #size-cells = <2>; 1827 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1828 1829 rti: sys-ctrl@0 { 1830 compatible = "amlogic,meson-gx-ao-sysctrl", 1831 "simple-mfd", "syscon"; 1832 reg = <0x0 0x0 0x0 0x100>; 1833 #address-cells = <2>; 1834 #size-cells = <2>; 1835 ranges = <0x0 0x0 0x0 0x0 0x0 0x100>; 1836 1837 clkc_AO: clock-controller { 1838 compatible = "amlogic,meson-g12a-aoclkc"; 1839 #clock-cells = <1>; 1840 #reset-cells = <1>; 1841 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1842 clock-names = "xtal", "mpeg-clk"; 1843 }; 1844 1845 ao_pinctrl: pinctrl@14 { 1846 compatible = "amlogic,meson-g12a-aobus-pinctrl"; 1847 #address-cells = <2>; 1848 #size-cells = <2>; 1849 ranges; 1850 1851 gpio_ao: bank@14 { 1852 reg = <0x0 0x14 0x0 0x8>, 1853 <0x0 0x1c 0x0 0x8>, 1854 <0x0 0x24 0x0 0x14>; 1855 reg-names = "mux", 1856 "ds", 1857 "gpio"; 1858 gpio-controller; 1859 #gpio-cells = <2>; 1860 gpio-ranges = <&ao_pinctrl 0 0 15>; 1861 }; 1862 1863 i2c_ao_sck_pins: i2c_ao_sck_pins { 1864 mux { 1865 groups = "i2c_ao_sck"; 1866 function = "i2c_ao"; 1867 bias-disable; 1868 drive-strength-microamp = <3000>; 1869 }; 1870 }; 1871 1872 i2c_ao_sda_pins: i2c_ao_sda { 1873 mux { 1874 groups = "i2c_ao_sda"; 1875 function = "i2c_ao"; 1876 bias-disable; 1877 drive-strength-microamp = <3000>; 1878 }; 1879 }; 1880 1881 i2c_ao_sck_e_pins: i2c_ao_sck_e { 1882 mux { 1883 groups = "i2c_ao_sck_e"; 1884 function = "i2c_ao"; 1885 bias-disable; 1886 drive-strength-microamp = <3000>; 1887 }; 1888 }; 1889 1890 i2c_ao_sda_e_pins: i2c_ao_sda_e { 1891 mux { 1892 groups = "i2c_ao_sda_e"; 1893 function = "i2c_ao"; 1894 bias-disable; 1895 drive-strength-microamp = <3000>; 1896 }; 1897 }; 1898 1899 mclk0_ao_pins: mclk0-ao { 1900 mux { 1901 groups = "mclk0_ao"; 1902 function = "mclk0_ao"; 1903 bias-disable; 1904 drive-strength-microamp = <3000>; 1905 }; 1906 }; 1907 1908 tdm_ao_b_din0_pins: tdm-ao-b-din0 { 1909 mux { 1910 groups = "tdm_ao_b_din0"; 1911 function = "tdm_ao_b"; 1912 bias-disable; 1913 }; 1914 }; 1915 1916 spdif_ao_out_pins: spdif-ao-out { 1917 mux { 1918 groups = "spdif_ao_out"; 1919 function = "spdif_ao_out"; 1920 drive-strength-microamp = <500>; 1921 bias-disable; 1922 }; 1923 }; 1924 1925 tdm_ao_b_din1_pins: tdm-ao-b-din1 { 1926 mux { 1927 groups = "tdm_ao_b_din1"; 1928 function = "tdm_ao_b"; 1929 bias-disable; 1930 }; 1931 }; 1932 1933 tdm_ao_b_din2_pins: tdm-ao-b-din2 { 1934 mux { 1935 groups = "tdm_ao_b_din2"; 1936 function = "tdm_ao_b"; 1937 bias-disable; 1938 }; 1939 }; 1940 1941 tdm_ao_b_dout0_pins: tdm-ao-b-dout0 { 1942 mux { 1943 groups = "tdm_ao_b_dout0"; 1944 function = "tdm_ao_b"; 1945 bias-disable; 1946 drive-strength-microamp = <3000>; 1947 }; 1948 }; 1949 1950 tdm_ao_b_dout1_pins: tdm-ao-b-dout1 { 1951 mux { 1952 groups = "tdm_ao_b_dout1"; 1953 function = "tdm_ao_b"; 1954 bias-disable; 1955 drive-strength-microamp = <3000>; 1956 }; 1957 }; 1958 1959 tdm_ao_b_dout2_pins: tdm-ao-b-dout2 { 1960 mux { 1961 groups = "tdm_ao_b_dout2"; 1962 function = "tdm_ao_b"; 1963 bias-disable; 1964 drive-strength-microamp = <3000>; 1965 }; 1966 }; 1967 1968 tdm_ao_b_fs_pins: tdm-ao-b-fs { 1969 mux { 1970 groups = "tdm_ao_b_fs"; 1971 function = "tdm_ao_b"; 1972 bias-disable; 1973 drive-strength-microamp = <3000>; 1974 }; 1975 }; 1976 1977 tdm_ao_b_sclk_pins: tdm-ao-b-sclk { 1978 mux { 1979 groups = "tdm_ao_b_sclk"; 1980 function = "tdm_ao_b"; 1981 bias-disable; 1982 drive-strength-microamp = <3000>; 1983 }; 1984 }; 1985 1986 tdm_ao_b_slv_fs_pins: tdm-ao-b-slv-fs { 1987 mux { 1988 groups = "tdm_ao_b_slv_fs"; 1989 function = "tdm_ao_b"; 1990 bias-disable; 1991 }; 1992 }; 1993 1994 tdm_ao_b_slv_sclk_pins: tdm-ao-b-slv-sclk { 1995 mux { 1996 groups = "tdm_ao_b_slv_sclk"; 1997 function = "tdm_ao_b"; 1998 bias-disable; 1999 }; 2000 }; 2001 2002 uart_ao_a_pins: uart-a-ao { 2003 mux { 2004 groups = "uart_ao_a_tx", 2005 "uart_ao_a_rx"; 2006 function = "uart_ao_a"; 2007 bias-disable; 2008 }; 2009 }; 2010 2011 uart_ao_a_cts_rts_pins: uart-ao-a-cts-rts { 2012 mux { 2013 groups = "uart_ao_a_cts", 2014 "uart_ao_a_rts"; 2015 function = "uart_ao_a"; 2016 bias-disable; 2017 }; 2018 }; 2019 2020 pwm_a_e_pins: pwm-a-e { 2021 mux { 2022 groups = "pwm_a_e"; 2023 function = "pwm_a_e"; 2024 bias-disable; 2025 }; 2026 }; 2027 2028 pwm_ao_a_pins: pwm-ao-a { 2029 mux { 2030 groups = "pwm_ao_a"; 2031 function = "pwm_ao_a"; 2032 bias-disable; 2033 }; 2034 }; 2035 2036 pwm_ao_b_pins: pwm-ao-b { 2037 mux { 2038 groups = "pwm_ao_b"; 2039 function = "pwm_ao_b"; 2040 bias-disable; 2041 }; 2042 }; 2043 2044 pwm_ao_c_4_pins: pwm-ao-c-4 { 2045 mux { 2046 groups = "pwm_ao_c_4"; 2047 function = "pwm_ao_c"; 2048 bias-disable; 2049 }; 2050 }; 2051 2052 pwm_ao_c_6_pins: pwm-ao-c-6 { 2053 mux { 2054 groups = "pwm_ao_c_6"; 2055 function = "pwm_ao_c"; 2056 bias-disable; 2057 }; 2058 }; 2059 2060 pwm_ao_d_5_pins: pwm-ao-d-5 { 2061 mux { 2062 groups = "pwm_ao_d_5"; 2063 function = "pwm_ao_d"; 2064 bias-disable; 2065 }; 2066 }; 2067 2068 pwm_ao_d_10_pins: pwm-ao-d-10 { 2069 mux { 2070 groups = "pwm_ao_d_10"; 2071 function = "pwm_ao_d"; 2072 bias-disable; 2073 }; 2074 }; 2075 2076 pwm_ao_d_e_pins: pwm-ao-d-e { 2077 mux { 2078 groups = "pwm_ao_d_e"; 2079 function = "pwm_ao_d"; 2080 }; 2081 }; 2082 2083 remote_input_ao_pins: remote-input-ao { 2084 mux { 2085 groups = "remote_ao_input"; 2086 function = "remote_ao_input"; 2087 bias-disable; 2088 }; 2089 }; 2090 }; 2091 }; 2092 2093 vrtc: rtc@0a8 { 2094 compatible = "amlogic,meson-vrtc"; 2095 reg = <0x0 0x000a8 0x0 0x4>; 2096 }; 2097 2098 cec_AO: cec@100 { 2099 compatible = "amlogic,meson-gx-ao-cec"; 2100 reg = <0x0 0x00100 0x0 0x14>; 2101 interrupts = <GIC_SPI 199 IRQ_TYPE_EDGE_RISING>; 2102 clocks = <&clkc_AO CLKID_AO_CEC>; 2103 clock-names = "core"; 2104 status = "disabled"; 2105 }; 2106 2107 sec_AO: ao-secure@140 { 2108 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 2109 reg = <0x0 0x140 0x0 0x140>; 2110 amlogic,has-chip-id; 2111 }; 2112 2113 cecb_AO: cec@280 { 2114 compatible = "amlogic,meson-g12a-ao-cec"; 2115 reg = <0x0 0x00280 0x0 0x1c>; 2116 interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>; 2117 clocks = <&clkc_AO CLKID_AO_CTS_OSCIN>; 2118 clock-names = "oscin"; 2119 status = "disabled"; 2120 }; 2121 2122 pwm_AO_cd: pwm@2000 { 2123 compatible = "amlogic,meson-g12a-ao-pwm-cd"; 2124 reg = <0x0 0x2000 0x0 0x20>; 2125 #pwm-cells = <3>; 2126 status = "disabled"; 2127 }; 2128 2129 uart_AO: serial@3000 { 2130 compatible = "amlogic,meson-gx-uart", 2131 "amlogic,meson-ao-uart"; 2132 reg = <0x0 0x3000 0x0 0x18>; 2133 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 2134 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART>, <&xtal>; 2135 clock-names = "xtal", "pclk", "baud"; 2136 status = "disabled"; 2137 }; 2138 2139 uart_AO_B: serial@4000 { 2140 compatible = "amlogic,meson-gx-uart", 2141 "amlogic,meson-ao-uart"; 2142 reg = <0x0 0x4000 0x0 0x18>; 2143 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 2144 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 2145 clock-names = "xtal", "pclk", "baud"; 2146 status = "disabled"; 2147 }; 2148 2149 i2c_AO: i2c@5000 { 2150 compatible = "amlogic,meson-axg-i2c"; 2151 status = "disabled"; 2152 reg = <0x0 0x05000 0x0 0x20>; 2153 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 2154 #address-cells = <1>; 2155 #size-cells = <0>; 2156 clocks = <&clkc CLKID_I2C>; 2157 }; 2158 2159 pwm_AO_ab: pwm@7000 { 2160 compatible = "amlogic,meson-g12a-ao-pwm-ab"; 2161 reg = <0x0 0x7000 0x0 0x20>; 2162 #pwm-cells = <3>; 2163 status = "disabled"; 2164 }; 2165 2166 ir: ir@8000 { 2167 compatible = "amlogic,meson-gxbb-ir"; 2168 reg = <0x0 0x8000 0x0 0x20>; 2169 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 2170 status = "disabled"; 2171 }; 2172 2173 saradc: adc@9000 { 2174 compatible = "amlogic,meson-g12a-saradc", 2175 "amlogic,meson-saradc"; 2176 reg = <0x0 0x9000 0x0 0x48>; 2177 #io-channel-cells = <1>; 2178 interrupts = <GIC_SPI 200 IRQ_TYPE_EDGE_RISING>; 2179 clocks = <&xtal>, 2180 <&clkc_AO CLKID_AO_SAR_ADC>, 2181 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 2182 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 2183 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 2184 status = "disabled"; 2185 }; 2186 }; 2187 2188 vpu: vpu@ff900000 { 2189 compatible = "amlogic,meson-g12a-vpu"; 2190 reg = <0x0 0xff900000 0x0 0x100000>, 2191 <0x0 0xff63c000 0x0 0x1000>; 2192 reg-names = "vpu", "hhi"; 2193 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 2194 #address-cells = <1>; 2195 #size-cells = <0>; 2196 amlogic,canvas = <&canvas>; 2197 2198 /* CVBS VDAC output port */ 2199 cvbs_vdac_port: port@0 { 2200 reg = <0>; 2201 }; 2202 2203 /* HDMI-TX output port */ 2204 hdmi_tx_port: port@1 { 2205 reg = <1>; 2206 2207 hdmi_tx_out: endpoint { 2208 remote-endpoint = <&hdmi_tx_in>; 2209 }; 2210 }; 2211 }; 2212 2213 gic: interrupt-controller@ffc01000 { 2214 compatible = "arm,gic-400"; 2215 reg = <0x0 0xffc01000 0 0x1000>, 2216 <0x0 0xffc02000 0 0x2000>, 2217 <0x0 0xffc04000 0 0x2000>, 2218 <0x0 0xffc06000 0 0x2000>; 2219 interrupt-controller; 2220 interrupts = <GIC_PPI 9 2221 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2222 #interrupt-cells = <3>; 2223 #address-cells = <0>; 2224 }; 2225 2226 cbus: bus@ffd00000 { 2227 compatible = "simple-bus"; 2228 reg = <0x0 0xffd00000 0x0 0x100000>; 2229 #address-cells = <2>; 2230 #size-cells = <2>; 2231 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x100000>; 2232 2233 reset: reset-controller@1004 { 2234 compatible = "amlogic,meson-axg-reset"; 2235 reg = <0x0 0x1004 0x0 0x9c>; 2236 #reset-cells = <1>; 2237 }; 2238 2239 gpio_intc: interrupt-controller@f080 { 2240 compatible = "amlogic,meson-g12a-gpio-intc", 2241 "amlogic,meson-gpio-intc"; 2242 reg = <0x0 0xf080 0x0 0x10>; 2243 interrupt-controller; 2244 #interrupt-cells = <2>; 2245 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 2246 }; 2247 2248 pwm_ef: pwm@19000 { 2249 compatible = "amlogic,meson-g12a-ee-pwm"; 2250 reg = <0x0 0x19000 0x0 0x20>; 2251 #pwm-cells = <3>; 2252 status = "disabled"; 2253 }; 2254 2255 pwm_cd: pwm@1a000 { 2256 compatible = "amlogic,meson-g12a-ee-pwm"; 2257 reg = <0x0 0x1a000 0x0 0x20>; 2258 #pwm-cells = <3>; 2259 status = "disabled"; 2260 }; 2261 2262 pwm_ab: pwm@1b000 { 2263 compatible = "amlogic,meson-g12a-ee-pwm"; 2264 reg = <0x0 0x1b000 0x0 0x20>; 2265 #pwm-cells = <3>; 2266 status = "disabled"; 2267 }; 2268 2269 i2c3: i2c@1c000 { 2270 compatible = "amlogic,meson-axg-i2c"; 2271 status = "disabled"; 2272 reg = <0x0 0x1c000 0x0 0x20>; 2273 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 2274 #address-cells = <1>; 2275 #size-cells = <0>; 2276 clocks = <&clkc CLKID_I2C>; 2277 }; 2278 2279 i2c2: i2c@1d000 { 2280 compatible = "amlogic,meson-axg-i2c"; 2281 status = "disabled"; 2282 reg = <0x0 0x1d000 0x0 0x20>; 2283 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 2284 #address-cells = <1>; 2285 #size-cells = <0>; 2286 clocks = <&clkc CLKID_I2C>; 2287 }; 2288 2289 i2c1: i2c@1e000 { 2290 compatible = "amlogic,meson-axg-i2c"; 2291 status = "disabled"; 2292 reg = <0x0 0x1e000 0x0 0x20>; 2293 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 2294 #address-cells = <1>; 2295 #size-cells = <0>; 2296 clocks = <&clkc CLKID_I2C>; 2297 }; 2298 2299 i2c0: i2c@1f000 { 2300 compatible = "amlogic,meson-axg-i2c"; 2301 status = "disabled"; 2302 reg = <0x0 0x1f000 0x0 0x20>; 2303 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 2304 #address-cells = <1>; 2305 #size-cells = <0>; 2306 clocks = <&clkc CLKID_I2C>; 2307 }; 2308 2309 clk_msr: clock-measure@18000 { 2310 compatible = "amlogic,meson-g12a-clk-measure"; 2311 reg = <0x0 0x18000 0x0 0x10>; 2312 }; 2313 2314 uart_C: serial@22000 { 2315 compatible = "amlogic,meson-gx-uart"; 2316 reg = <0x0 0x22000 0x0 0x18>; 2317 interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; 2318 clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>; 2319 clock-names = "xtal", "pclk", "baud"; 2320 status = "disabled"; 2321 }; 2322 2323 uart_B: serial@23000 { 2324 compatible = "amlogic,meson-gx-uart"; 2325 reg = <0x0 0x23000 0x0 0x18>; 2326 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 2327 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 2328 clock-names = "xtal", "pclk", "baud"; 2329 status = "disabled"; 2330 }; 2331 2332 uart_A: serial@24000 { 2333 compatible = "amlogic,meson-gx-uart"; 2334 reg = <0x0 0x24000 0x0 0x18>; 2335 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 2336 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 2337 clock-names = "xtal", "pclk", "baud"; 2338 status = "disabled"; 2339 }; 2340 }; 2341 2342 sd_emmc_a: sd@ffe03000 { 2343 compatible = "amlogic,meson-axg-mmc"; 2344 reg = <0x0 0xffe03000 0x0 0x800>; 2345 interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>; 2346 status = "disabled"; 2347 clocks = <&clkc CLKID_SD_EMMC_A>, 2348 <&clkc CLKID_SD_EMMC_A_CLK0>, 2349 <&clkc CLKID_FCLK_DIV2>; 2350 clock-names = "core", "clkin0", "clkin1"; 2351 resets = <&reset RESET_SD_EMMC_A>; 2352 }; 2353 2354 sd_emmc_b: sd@ffe05000 { 2355 compatible = "amlogic,meson-axg-mmc"; 2356 reg = <0x0 0xffe05000 0x0 0x800>; 2357 interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>; 2358 status = "disabled"; 2359 clocks = <&clkc CLKID_SD_EMMC_B>, 2360 <&clkc CLKID_SD_EMMC_B_CLK0>, 2361 <&clkc CLKID_FCLK_DIV2>; 2362 clock-names = "core", "clkin0", "clkin1"; 2363 resets = <&reset RESET_SD_EMMC_B>; 2364 }; 2365 2366 sd_emmc_c: mmc@ffe07000 { 2367 compatible = "amlogic,meson-axg-mmc"; 2368 reg = <0x0 0xffe07000 0x0 0x800>; 2369 interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>; 2370 status = "disabled"; 2371 clocks = <&clkc CLKID_SD_EMMC_C>, 2372 <&clkc CLKID_SD_EMMC_C_CLK0>, 2373 <&clkc CLKID_FCLK_DIV2>; 2374 clock-names = "core", "clkin0", "clkin1"; 2375 resets = <&reset RESET_SD_EMMC_C>; 2376 }; 2377 2378 usb: usb@ffe09000 { 2379 status = "disabled"; 2380 compatible = "amlogic,meson-g12a-usb-ctrl"; 2381 reg = <0x0 0xffe09000 0x0 0xa0>; 2382 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 2383 #address-cells = <2>; 2384 #size-cells = <2>; 2385 ranges; 2386 2387 clocks = <&clkc CLKID_USB>; 2388 resets = <&reset RESET_USB>; 2389 2390 dr_mode = "otg"; 2391 2392 phys = <&usb2_phy0>, <&usb2_phy1>, 2393 <&usb3_pcie_phy PHY_TYPE_USB3>; 2394 phy-names = "usb2-phy0", "usb2-phy1", "usb3-phy0"; 2395 2396 dwc2: usb@ff400000 { 2397 compatible = "amlogic,meson-g12a-usb", "snps,dwc2"; 2398 reg = <0x0 0xff400000 0x0 0x40000>; 2399 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 2400 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; 2401 clock-names = "ddr"; 2402 phys = <&usb2_phy1>; 2403 phy-names = "usb2-phy"; 2404 dr_mode = "peripheral"; 2405 g-rx-fifo-size = <192>; 2406 g-np-tx-fifo-size = <128>; 2407 g-tx-fifo-size = <128 128 16 16 16>; 2408 }; 2409 2410 dwc3: usb@ff500000 { 2411 compatible = "snps,dwc3"; 2412 reg = <0x0 0xff500000 0x0 0x100000>; 2413 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 2414 dr_mode = "host"; 2415 snps,dis_u2_susphy_quirk; 2416 snps,quirk-frame-length-adjustment; 2417 }; 2418 }; 2419 2420 mali: gpu@ffe40000 { 2421 compatible = "amlogic,meson-g12a-mali", "arm,mali-bifrost"; 2422 reg = <0x0 0xffe40000 0x0 0x40000>; 2423 interrupt-parent = <&gic>; 2424 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2425 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 2427 interrupt-names = "gpu", "mmu", "job"; 2428 clocks = <&clkc CLKID_MALI>; 2429 resets = <&reset RESET_DVALIN_CAPB3>, <&reset RESET_DVALIN>; 2430 2431 /* 2432 * Mali clocking is provided by two identical clock paths 2433 * MALI_0 and MALI_1 muxed to a single clock by a glitch 2434 * free mux to safely change frequency while running. 2435 */ 2436 assigned-clocks = <&clkc CLKID_MALI_0_SEL>, 2437 <&clkc CLKID_MALI_0>, 2438 <&clkc CLKID_MALI>; /* Glitch free mux */ 2439 assigned-clock-parents = <&clkc CLKID_FCLK_DIV2P5>, 2440 <0>, /* Do Nothing */ 2441 <&clkc CLKID_MALI_0>; 2442 assigned-clock-rates = <0>, /* Do Nothing */ 2443 <800000000>, 2444 <0>; /* Do Nothing */ 2445 }; 2446 }; 2447 2448 timer { 2449 compatible = "arm,armv8-timer"; 2450 interrupts = <GIC_PPI 13 2451 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2452 <GIC_PPI 14 2453 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2454 <GIC_PPI 11 2455 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 2456 <GIC_PPI 10 2457 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 2458 arm,no-tick-in-suspend; 2459 }; 2460 2461 xtal: xtal-clk { 2462 compatible = "fixed-clock"; 2463 clock-frequency = <24000000>; 2464 clock-output-names = "xtal"; 2465 #clock-cells = <0>; 2466 }; 2467 2468}; 2469