1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/clock/axg-aoclkc.h>
7#include <dt-bindings/clock/axg-audio-clkc.h>
8#include <dt-bindings/clock/axg-clkc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/gpio/meson-axg-gpio.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15#include <dt-bindings/power/meson-axg-power.h>
16
17/ {
18	compatible = "amlogic,meson-axg";
19
20	interrupt-parent = <&gic>;
21	#address-cells = <2>;
22	#size-cells = <2>;
23
24	tdmif_a: audio-controller-0 {
25		compatible = "amlogic,axg-tdm-iface";
26		#sound-dai-cells = <0>;
27		sound-name-prefix = "TDM_A";
28		clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29			 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30			 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31		clock-names = "mclk", "sclk", "lrclk";
32		status = "disabled";
33	};
34
35	tdmif_b: audio-controller-1 {
36		compatible = "amlogic,axg-tdm-iface";
37		#sound-dai-cells = <0>;
38		sound-name-prefix = "TDM_B";
39		clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40			 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41			 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42		clock-names = "mclk", "sclk", "lrclk";
43		status = "disabled";
44	};
45
46	tdmif_c: audio-controller-2 {
47		compatible = "amlogic,axg-tdm-iface";
48		#sound-dai-cells = <0>;
49		sound-name-prefix = "TDM_C";
50		clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51			 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52			 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53		clock-names = "mclk", "sclk", "lrclk";
54		status = "disabled";
55	};
56
57	arm-pmu {
58		compatible = "arm,cortex-a53-pmu";
59		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64	};
65
66	cpus {
67		#address-cells = <0x2>;
68		#size-cells = <0x0>;
69
70		cpu0: cpu@0 {
71			device_type = "cpu";
72			compatible = "arm,cortex-a53";
73			reg = <0x0 0x0>;
74			enable-method = "psci";
75			next-level-cache = <&l2>;
76			clocks = <&scpi_dvfs 0>;
77		};
78
79		cpu1: cpu@1 {
80			device_type = "cpu";
81			compatible = "arm,cortex-a53";
82			reg = <0x0 0x1>;
83			enable-method = "psci";
84			next-level-cache = <&l2>;
85			clocks = <&scpi_dvfs 0>;
86		};
87
88		cpu2: cpu@2 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a53";
91			reg = <0x0 0x2>;
92			enable-method = "psci";
93			next-level-cache = <&l2>;
94			clocks = <&scpi_dvfs 0>;
95		};
96
97		cpu3: cpu@3 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a53";
100			reg = <0x0 0x3>;
101			enable-method = "psci";
102			next-level-cache = <&l2>;
103			clocks = <&scpi_dvfs 0>;
104		};
105
106		l2: l2-cache0 {
107			compatible = "cache";
108		};
109	};
110
111	sm: secure-monitor {
112		compatible = "amlogic,meson-gxbb-sm";
113	};
114
115	efuse: efuse {
116		compatible = "amlogic,meson-gxbb-efuse";
117		clocks = <&clkc CLKID_EFUSE>;
118		#address-cells = <1>;
119		#size-cells = <1>;
120		read-only;
121		secure-monitor = <&sm>;
122	};
123
124	psci {
125		compatible = "arm,psci-1.0";
126		method = "smc";
127	};
128
129	reserved-memory {
130		#address-cells = <2>;
131		#size-cells = <2>;
132		ranges;
133
134		/* 16 MiB reserved for Hardware ROM Firmware */
135		hwrom_reserved: hwrom@0 {
136			reg = <0x0 0x0 0x0 0x1000000>;
137			no-map;
138		};
139
140		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
141		secmon_reserved: secmon@5000000 {
142			reg = <0x0 0x05000000 0x0 0x300000>;
143			no-map;
144		};
145	};
146
147	scpi {
148		compatible = "arm,scpi-pre-1.0";
149		mboxes = <&mailbox 1 &mailbox 2>;
150		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
151
152		scpi_clocks: clocks {
153			compatible = "arm,scpi-clocks";
154
155			scpi_dvfs: clock-controller {
156				compatible = "arm,scpi-dvfs-clocks";
157				#clock-cells = <1>;
158				clock-indices = <0>;
159				clock-output-names = "vcpu";
160			};
161		};
162
163		scpi_sensors: sensors {
164			compatible = "amlogic,meson-gxbb-scpi-sensors";
165			#thermal-sensor-cells = <1>;
166		};
167	};
168
169	soc {
170		compatible = "simple-bus";
171		#address-cells = <2>;
172		#size-cells = <2>;
173		ranges;
174
175		pcieA: pcie@f9800000 {
176			compatible = "amlogic,axg-pcie", "snps,dw-pcie";
177			reg = <0x0 0xf9800000 0x0 0x400000>,
178			      <0x0 0xff646000 0x0 0x2000>,
179			      <0x0 0xf9f00000 0x0 0x100000>;
180			reg-names = "elbi", "cfg", "config";
181			interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
182			#interrupt-cells = <1>;
183			interrupt-map-mask = <0 0 0 0>;
184			interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
185			bus-range = <0x0 0xff>;
186			#address-cells = <3>;
187			#size-cells = <2>;
188			device_type = "pci";
189			ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
190
191			clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
192			clock-names = "general", "pclk", "port";
193			resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
194			reset-names = "port", "apb";
195			num-lanes = <1>;
196			phys = <&pcie_phy>;
197			phy-names = "pcie";
198			status = "disabled";
199		};
200
201		pcieB: pcie@fa000000 {
202			compatible = "amlogic,axg-pcie", "snps,dw-pcie";
203			reg = <0x0 0xfa000000 0x0 0x400000>,
204			      <0x0 0xff648000 0x0 0x2000>,
205			      <0x0 0xfa400000 0x0 0x100000>;
206			reg-names = "elbi", "cfg", "config";
207			interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
208			#interrupt-cells = <1>;
209			interrupt-map-mask = <0 0 0 0>;
210			interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
211			bus-range = <0x0 0xff>;
212			#address-cells = <3>;
213			#size-cells = <2>;
214			device_type = "pci";
215			ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
216
217			clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
218			clock-names = "general", "pclk", "port";
219			resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
220			reset-names = "port", "apb";
221			num-lanes = <1>;
222			phys = <&pcie_phy>;
223			phy-names = "pcie";
224			status = "disabled";
225		};
226
227		usb: usb@ffe09080 {
228			compatible = "amlogic,meson-axg-usb-ctrl";
229			reg = <0x0 0xffe09080 0x0 0x20>;
230			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
231			#address-cells = <2>;
232			#size-cells = <2>;
233			ranges;
234
235			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
236			clock-names = "usb_ctrl", "ddr";
237			resets = <&reset RESET_USB_OTG>;
238
239			dr_mode = "otg";
240
241			phys = <&usb2_phy1>;
242			phy-names = "usb2-phy1";
243
244			dwc2: usb@ff400000 {
245				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
246				reg = <0x0 0xff400000 0x0 0x40000>;
247				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
248				clocks = <&clkc CLKID_USB1>;
249				clock-names = "otg";
250				phys = <&usb2_phy1>;
251				dr_mode = "peripheral";
252				g-rx-fifo-size = <192>;
253				g-np-tx-fifo-size = <128>;
254				g-tx-fifo-size = <128 128 16 16 16>;
255			};
256
257			dwc3: usb@ff500000 {
258				compatible = "snps,dwc3";
259				reg = <0x0 0xff500000 0x0 0x100000>;
260				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
261				dr_mode = "host";
262				maximum-speed = "high-speed";
263				snps,dis_u2_susphy_quirk;
264			};
265		};
266
267		ethmac: ethernet@ff3f0000 {
268			compatible = "amlogic,meson-axg-dwmac",
269				     "snps,dwmac-3.70a",
270				     "snps,dwmac";
271			reg = <0x0 0xff3f0000 0x0 0x10000>,
272			      <0x0 0xff634540 0x0 0x8>;
273			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
274			interrupt-names = "macirq";
275			clocks = <&clkc CLKID_ETH>,
276				 <&clkc CLKID_FCLK_DIV2>,
277				 <&clkc CLKID_MPLL2>,
278				 <&clkc CLKID_FCLK_DIV2>;
279			clock-names = "stmmaceth", "clkin0", "clkin1",
280				      "timing-adjustment";
281			rx-fifo-depth = <4096>;
282			tx-fifo-depth = <2048>;
283			power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
284			status = "disabled";
285		};
286
287		pcie_phy: phy@ff644000 {
288			compatible = "amlogic,axg-pcie-phy";
289			reg = <0x0 0xff644000 0x0 0x1c>;
290			resets = <&reset RESET_PCIE_PHY>;
291			phys = <&mipi_pcie_analog_dphy>;
292			phy-names = "analog";
293			#phy-cells = <0>;
294		};
295
296		pdm: audio-controller@ff632000 {
297			compatible = "amlogic,axg-pdm";
298			reg = <0x0 0xff632000 0x0 0x34>;
299			#sound-dai-cells = <0>;
300			sound-name-prefix = "PDM";
301			clocks = <&clkc_audio AUD_CLKID_PDM>,
302				 <&clkc_audio AUD_CLKID_PDM_DCLK>,
303				 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
304			clock-names = "pclk", "dclk", "sysclk";
305			status = "disabled";
306		};
307
308		periphs: bus@ff634000 {
309			compatible = "simple-bus";
310			reg = <0x0 0xff634000 0x0 0x2000>;
311			#address-cells = <2>;
312			#size-cells = <2>;
313			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
314
315			hwrng: rng@18 {
316				compatible = "amlogic,meson-rng";
317				reg = <0x0 0x18 0x0 0x4>;
318				clocks = <&clkc CLKID_RNG0>;
319				clock-names = "core";
320			};
321
322			pinctrl_periphs: pinctrl@480 {
323				compatible = "amlogic,meson-axg-periphs-pinctrl";
324				#address-cells = <2>;
325				#size-cells = <2>;
326				ranges;
327
328				gpio: bank@480 {
329					reg = <0x0 0x00480 0x0 0x40>,
330					      <0x0 0x004e8 0x0 0x14>,
331					      <0x0 0x00520 0x0 0x14>,
332					      <0x0 0x00430 0x0 0x3c>;
333					reg-names = "mux", "pull", "pull-enable", "gpio";
334					gpio-controller;
335					#gpio-cells = <2>;
336					gpio-ranges = <&pinctrl_periphs 0 0 86>;
337				};
338
339				i2c0_pins: i2c0 {
340					mux {
341						groups = "i2c0_sck",
342							 "i2c0_sda";
343						function = "i2c0";
344						bias-disable;
345					};
346				};
347
348				i2c1_x_pins: i2c1_x {
349					mux {
350						groups = "i2c1_sck_x",
351							 "i2c1_sda_x";
352						function = "i2c1";
353						bias-disable;
354					};
355				};
356
357				i2c1_z_pins: i2c1_z {
358					mux {
359						groups = "i2c1_sck_z",
360							 "i2c1_sda_z";
361						function = "i2c1";
362						bias-disable;
363					};
364				};
365
366				i2c2_a_pins: i2c2_a {
367					mux {
368						groups = "i2c2_sck_a",
369							 "i2c2_sda_a";
370						function = "i2c2";
371						bias-disable;
372					};
373				};
374
375				i2c2_x_pins: i2c2_x {
376					mux {
377						groups = "i2c2_sck_x",
378							 "i2c2_sda_x";
379						function = "i2c2";
380						bias-disable;
381					};
382				};
383
384				i2c3_a6_pins: i2c3_a6 {
385					mux {
386						groups = "i2c3_sda_a6",
387							 "i2c3_sck_a7";
388						function = "i2c3";
389						bias-disable;
390					};
391				};
392
393				i2c3_a12_pins: i2c3_a12 {
394					mux {
395						groups = "i2c3_sda_a12",
396							 "i2c3_sck_a13";
397						function = "i2c3";
398						bias-disable;
399					};
400				};
401
402				i2c3_a19_pins: i2c3_a19 {
403					mux {
404						groups = "i2c3_sda_a19",
405							 "i2c3_sck_a20";
406						function = "i2c3";
407						bias-disable;
408					};
409				};
410
411				emmc_pins: emmc {
412					mux-0 {
413						groups = "emmc_nand_d0",
414							 "emmc_nand_d1",
415							 "emmc_nand_d2",
416							 "emmc_nand_d3",
417							 "emmc_nand_d4",
418							 "emmc_nand_d5",
419							 "emmc_nand_d6",
420							 "emmc_nand_d7",
421							 "emmc_cmd";
422						function = "emmc";
423						bias-pull-up;
424					};
425
426					mux-1 {
427						groups = "emmc_clk";
428						function = "emmc";
429						bias-disable;
430					};
431				};
432
433				emmc_ds_pins: emmc_ds {
434					mux {
435						groups = "emmc_ds";
436						function = "emmc";
437						bias-pull-down;
438					};
439				};
440
441				emmc_clk_gate_pins: emmc_clk_gate {
442					mux {
443						groups = "BOOT_8";
444						function = "gpio_periphs";
445						bias-pull-down;
446					};
447				};
448
449				eth_rgmii_x_pins: eth-x-rgmii {
450					mux {
451						groups = "eth_mdio_x",
452							 "eth_mdc_x",
453							 "eth_rgmii_rx_clk_x",
454							 "eth_rx_dv_x",
455							 "eth_rxd0_x",
456							 "eth_rxd1_x",
457							 "eth_rxd2_rgmii",
458							 "eth_rxd3_rgmii",
459							 "eth_rgmii_tx_clk",
460							 "eth_txen_x",
461							 "eth_txd0_x",
462							 "eth_txd1_x",
463							 "eth_txd2_rgmii",
464							 "eth_txd3_rgmii";
465						function = "eth";
466						bias-disable;
467					};
468				};
469
470				eth_rgmii_y_pins: eth-y-rgmii {
471					mux {
472						groups = "eth_mdio_y",
473							 "eth_mdc_y",
474							 "eth_rgmii_rx_clk_y",
475							 "eth_rx_dv_y",
476							 "eth_rxd0_y",
477							 "eth_rxd1_y",
478							 "eth_rxd2_rgmii",
479							 "eth_rxd3_rgmii",
480							 "eth_rgmii_tx_clk",
481							 "eth_txen_y",
482							 "eth_txd0_y",
483							 "eth_txd1_y",
484							 "eth_txd2_rgmii",
485							 "eth_txd3_rgmii";
486						function = "eth";
487						bias-disable;
488					};
489				};
490
491				eth_rmii_x_pins: eth-x-rmii {
492					mux {
493						groups = "eth_mdio_x",
494							 "eth_mdc_x",
495							 "eth_rgmii_rx_clk_x",
496							 "eth_rx_dv_x",
497							 "eth_rxd0_x",
498							 "eth_rxd1_x",
499							 "eth_txen_x",
500							 "eth_txd0_x",
501							 "eth_txd1_x";
502						function = "eth";
503						bias-disable;
504					};
505				};
506
507				eth_rmii_y_pins: eth-y-rmii {
508					mux {
509						groups = "eth_mdio_y",
510							 "eth_mdc_y",
511							 "eth_rgmii_rx_clk_y",
512							 "eth_rx_dv_y",
513							 "eth_rxd0_y",
514							 "eth_rxd1_y",
515							 "eth_txen_y",
516							 "eth_txd0_y",
517							 "eth_txd1_y";
518						function = "eth";
519						bias-disable;
520					};
521				};
522
523				mclk_b_pins: mclk_b {
524					mux {
525						groups = "mclk_b";
526						function = "mclk_b";
527						bias-disable;
528					};
529				};
530
531				mclk_c_pins: mclk_c {
532					mux {
533						groups = "mclk_c";
534						function = "mclk_c";
535						bias-disable;
536					};
537				};
538
539				pdm_dclk_a14_pins: pdm_dclk_a14 {
540					mux {
541						groups = "pdm_dclk_a14";
542						function = "pdm";
543						bias-disable;
544					};
545				};
546
547				pdm_dclk_a19_pins: pdm_dclk_a19 {
548					mux {
549						groups = "pdm_dclk_a19";
550						function = "pdm";
551						bias-disable;
552					};
553				};
554
555				pdm_din0_pins: pdm_din0 {
556					mux {
557						groups = "pdm_din0";
558						function = "pdm";
559						bias-disable;
560					};
561				};
562
563				pdm_din1_pins: pdm_din1 {
564					mux {
565						groups = "pdm_din1";
566						function = "pdm";
567						bias-disable;
568					};
569				};
570
571				pdm_din2_pins: pdm_din2 {
572					mux {
573						groups = "pdm_din2";
574						function = "pdm";
575						bias-disable;
576					};
577				};
578
579				pdm_din3_pins: pdm_din3 {
580					mux {
581						groups = "pdm_din3";
582						function = "pdm";
583						bias-disable;
584					};
585				};
586
587				pwm_a_a_pins: pwm_a_a {
588					mux {
589						groups = "pwm_a_a";
590						function = "pwm_a";
591						bias-disable;
592					};
593				};
594
595				pwm_a_x18_pins: pwm_a_x18 {
596					mux {
597						groups = "pwm_a_x18";
598						function = "pwm_a";
599						bias-disable;
600					};
601				};
602
603				pwm_a_x20_pins: pwm_a_x20 {
604					mux {
605						groups = "pwm_a_x20";
606						function = "pwm_a";
607						bias-disable;
608					};
609				};
610
611				pwm_a_z_pins: pwm_a_z {
612					mux {
613						groups = "pwm_a_z";
614						function = "pwm_a";
615						bias-disable;
616					};
617				};
618
619				pwm_b_a_pins: pwm_b_a {
620					mux {
621						groups = "pwm_b_a";
622						function = "pwm_b";
623						bias-disable;
624					};
625				};
626
627				pwm_b_x_pins: pwm_b_x {
628					mux {
629						groups = "pwm_b_x";
630						function = "pwm_b";
631						bias-disable;
632					};
633				};
634
635				pwm_b_z_pins: pwm_b_z {
636					mux {
637						groups = "pwm_b_z";
638						function = "pwm_b";
639						bias-disable;
640					};
641				};
642
643				pwm_c_a_pins: pwm_c_a {
644					mux {
645						groups = "pwm_c_a";
646						function = "pwm_c";
647						bias-disable;
648					};
649				};
650
651				pwm_c_x10_pins: pwm_c_x10 {
652					mux {
653						groups = "pwm_c_x10";
654						function = "pwm_c";
655						bias-disable;
656					};
657				};
658
659				pwm_c_x17_pins: pwm_c_x17 {
660					mux {
661						groups = "pwm_c_x17";
662						function = "pwm_c";
663						bias-disable;
664					};
665				};
666
667				pwm_d_x11_pins: pwm_d_x11 {
668					mux {
669						groups = "pwm_d_x11";
670						function = "pwm_d";
671						bias-disable;
672					};
673				};
674
675				pwm_d_x16_pins: pwm_d_x16 {
676					mux {
677						groups = "pwm_d_x16";
678						function = "pwm_d";
679						bias-disable;
680					};
681				};
682
683				sdio_pins: sdio {
684					mux-0 {
685						groups = "sdio_d0",
686							 "sdio_d1",
687							 "sdio_d2",
688							 "sdio_d3",
689							 "sdio_cmd";
690						function = "sdio";
691						bias-pull-up;
692					};
693
694					mux-1 {
695						groups = "sdio_clk";
696						function = "sdio";
697						bias-disable;
698					};
699				};
700
701				sdio_clk_gate_pins: sdio_clk_gate {
702					mux {
703						groups = "GPIOX_4";
704						function = "gpio_periphs";
705						bias-pull-down;
706					};
707				};
708
709				spdif_in_z_pins: spdif_in_z {
710					mux {
711						groups = "spdif_in_z";
712						function = "spdif_in";
713						bias-disable;
714					};
715				};
716
717				spdif_in_a1_pins: spdif_in_a1 {
718					mux {
719						groups = "spdif_in_a1";
720						function = "spdif_in";
721						bias-disable;
722					};
723				};
724
725				spdif_in_a7_pins: spdif_in_a7 {
726					mux {
727						groups = "spdif_in_a7";
728						function = "spdif_in";
729						bias-disable;
730					};
731				};
732
733				spdif_in_a19_pins: spdif_in_a19 {
734					mux {
735						groups = "spdif_in_a19";
736						function = "spdif_in";
737						bias-disable;
738					};
739				};
740
741				spdif_in_a20_pins: spdif_in_a20 {
742					mux {
743						groups = "spdif_in_a20";
744						function = "spdif_in";
745						bias-disable;
746					};
747				};
748
749				spdif_out_a1_pins: spdif_out_a1 {
750					mux {
751						groups = "spdif_out_a1";
752						function = "spdif_out";
753						bias-disable;
754					};
755				};
756
757				spdif_out_a11_pins: spdif_out_a11 {
758					mux {
759						groups = "spdif_out_a11";
760						function = "spdif_out";
761						bias-disable;
762					};
763				};
764
765				spdif_out_a19_pins: spdif_out_a19 {
766					mux {
767						groups = "spdif_out_a19";
768						function = "spdif_out";
769						bias-disable;
770					};
771				};
772
773				spdif_out_a20_pins: spdif_out_a20 {
774					mux {
775						groups = "spdif_out_a20";
776						function = "spdif_out";
777						bias-disable;
778					};
779				};
780
781				spdif_out_z_pins: spdif_out_z {
782					mux {
783						groups = "spdif_out_z";
784						function = "spdif_out";
785						bias-disable;
786					};
787				};
788
789				spi0_pins: spi0 {
790					mux {
791						groups = "spi0_miso",
792							 "spi0_mosi",
793							 "spi0_clk";
794						function = "spi0";
795						bias-disable;
796					};
797				};
798
799				spi0_ss0_pins: spi0_ss0 {
800					mux {
801						groups = "spi0_ss0";
802						function = "spi0";
803						bias-disable;
804					};
805				};
806
807				spi0_ss1_pins: spi0_ss1 {
808					mux {
809						groups = "spi0_ss1";
810						function = "spi0";
811						bias-disable;
812					};
813				};
814
815				spi0_ss2_pins: spi0_ss2 {
816					mux {
817						groups = "spi0_ss2";
818						function = "spi0";
819						bias-disable;
820					};
821				};
822
823				spi1_a_pins: spi1_a {
824					mux {
825						groups = "spi1_miso_a",
826							 "spi1_mosi_a",
827							 "spi1_clk_a";
828						function = "spi1";
829						bias-disable;
830					};
831				};
832
833				spi1_ss0_a_pins: spi1_ss0_a {
834					mux {
835						groups = "spi1_ss0_a";
836						function = "spi1";
837						bias-disable;
838					};
839				};
840
841				spi1_ss1_pins: spi1_ss1 {
842					mux {
843						groups = "spi1_ss1";
844						function = "spi1";
845						bias-disable;
846					};
847				};
848
849				spi1_x_pins: spi1_x {
850					mux {
851						groups = "spi1_miso_x",
852							 "spi1_mosi_x",
853							 "spi1_clk_x";
854						function = "spi1";
855						bias-disable;
856					};
857				};
858
859				spi1_ss0_x_pins: spi1_ss0_x {
860					mux {
861						groups = "spi1_ss0_x";
862						function = "spi1";
863						bias-disable;
864					};
865				};
866
867				tdma_din0_pins: tdma_din0 {
868					mux {
869						groups = "tdma_din0";
870						function = "tdma";
871						bias-disable;
872					};
873				};
874
875				tdma_dout0_x14_pins: tdma_dout0_x14 {
876					mux {
877						groups = "tdma_dout0_x14";
878						function = "tdma";
879						bias-disable;
880					};
881				};
882
883				tdma_dout0_x15_pins: tdma_dout0_x15 {
884					mux {
885						groups = "tdma_dout0_x15";
886						function = "tdma";
887						bias-disable;
888					};
889				};
890
891				tdma_dout1_pins: tdma_dout1 {
892					mux {
893						groups = "tdma_dout1";
894						function = "tdma";
895						bias-disable;
896					};
897				};
898
899				tdma_din1_pins: tdma_din1 {
900					mux {
901						groups = "tdma_din1";
902						function = "tdma";
903						bias-disable;
904					};
905				};
906
907				tdma_fs_pins: tdma_fs {
908					mux {
909						groups = "tdma_fs";
910						function = "tdma";
911						bias-disable;
912					};
913				};
914
915				tdma_fs_slv_pins: tdma_fs_slv {
916					mux {
917						groups = "tdma_fs_slv";
918						function = "tdma";
919						bias-disable;
920					};
921				};
922
923				tdma_sclk_pins: tdma_sclk {
924					mux {
925						groups = "tdma_sclk";
926						function = "tdma";
927						bias-disable;
928					};
929				};
930
931				tdma_sclk_slv_pins: tdma_sclk_slv {
932					mux {
933						groups = "tdma_sclk_slv";
934						function = "tdma";
935						bias-disable;
936					};
937				};
938
939				tdmb_din0_pins: tdmb_din0 {
940					mux {
941						groups = "tdmb_din0";
942						function = "tdmb";
943						bias-disable;
944					};
945				};
946
947				tdmb_din1_pins: tdmb_din1 {
948					mux {
949						groups = "tdmb_din1";
950						function = "tdmb";
951						bias-disable;
952					};
953				};
954
955				tdmb_din2_pins: tdmb_din2 {
956					mux {
957						groups = "tdmb_din2";
958						function = "tdmb";
959						bias-disable;
960					};
961				};
962
963				tdmb_din3_pins: tdmb_din3 {
964					mux {
965						groups = "tdmb_din3";
966						function = "tdmb";
967						bias-disable;
968					};
969				};
970
971				tdmb_dout0_pins: tdmb_dout0 {
972					mux {
973						groups = "tdmb_dout0";
974						function = "tdmb";
975						bias-disable;
976					};
977				};
978
979				tdmb_dout1_pins: tdmb_dout1 {
980					mux {
981						groups = "tdmb_dout1";
982						function = "tdmb";
983						bias-disable;
984					};
985				};
986
987				tdmb_dout2_pins: tdmb_dout2 {
988					mux {
989						groups = "tdmb_dout2";
990						function = "tdmb";
991						bias-disable;
992					};
993				};
994
995				tdmb_dout3_pins: tdmb_dout3 {
996					mux {
997						groups = "tdmb_dout3";
998						function = "tdmb";
999						bias-disable;
1000					};
1001				};
1002
1003				tdmb_fs_pins: tdmb_fs {
1004					mux {
1005						groups = "tdmb_fs";
1006						function = "tdmb";
1007						bias-disable;
1008					};
1009				};
1010
1011				tdmb_fs_slv_pins: tdmb_fs_slv {
1012					mux {
1013						groups = "tdmb_fs_slv";
1014						function = "tdmb";
1015						bias-disable;
1016					};
1017				};
1018
1019				tdmb_sclk_pins: tdmb_sclk {
1020					mux {
1021						groups = "tdmb_sclk";
1022						function = "tdmb";
1023						bias-disable;
1024					};
1025				};
1026
1027				tdmb_sclk_slv_pins: tdmb_sclk_slv {
1028					mux {
1029						groups = "tdmb_sclk_slv";
1030						function = "tdmb";
1031						bias-disable;
1032					};
1033				};
1034
1035				tdmc_fs_pins: tdmc_fs {
1036					mux {
1037						groups = "tdmc_fs";
1038						function = "tdmc";
1039						bias-disable;
1040					};
1041				};
1042
1043				tdmc_fs_slv_pins: tdmc_fs_slv {
1044					mux {
1045						groups = "tdmc_fs_slv";
1046						function = "tdmc";
1047						bias-disable;
1048					};
1049				};
1050
1051				tdmc_sclk_pins: tdmc_sclk {
1052					mux {
1053						groups = "tdmc_sclk";
1054						function = "tdmc";
1055						bias-disable;
1056					};
1057				};
1058
1059				tdmc_sclk_slv_pins: tdmc_sclk_slv {
1060					mux {
1061						groups = "tdmc_sclk_slv";
1062						function = "tdmc";
1063						bias-disable;
1064					};
1065				};
1066
1067				tdmc_din0_pins: tdmc_din0 {
1068					mux {
1069						groups = "tdmc_din0";
1070						function = "tdmc";
1071						bias-disable;
1072					};
1073				};
1074
1075				tdmc_din1_pins: tdmc_din1 {
1076					mux {
1077						groups = "tdmc_din1";
1078						function = "tdmc";
1079						bias-disable;
1080					};
1081				};
1082
1083				tdmc_din2_pins: tdmc_din2 {
1084					mux {
1085						groups = "tdmc_din2";
1086						function = "tdmc";
1087						bias-disable;
1088					};
1089				};
1090
1091				tdmc_din3_pins: tdmc_din3 {
1092					mux {
1093						groups = "tdmc_din3";
1094						function = "tdmc";
1095						bias-disable;
1096					};
1097				};
1098
1099				tdmc_dout0_pins: tdmc_dout0 {
1100					mux {
1101						groups = "tdmc_dout0";
1102						function = "tdmc";
1103						bias-disable;
1104					};
1105				};
1106
1107				tdmc_dout1_pins: tdmc_dout1 {
1108					mux {
1109						groups = "tdmc_dout1";
1110						function = "tdmc";
1111						bias-disable;
1112					};
1113				};
1114
1115				tdmc_dout2_pins: tdmc_dout2 {
1116					mux {
1117						groups = "tdmc_dout2";
1118						function = "tdmc";
1119						bias-disable;
1120					};
1121				};
1122
1123				tdmc_dout3_pins: tdmc_dout3 {
1124					mux {
1125						groups = "tdmc_dout3";
1126						function = "tdmc";
1127						bias-disable;
1128					};
1129				};
1130
1131				uart_a_pins: uart_a {
1132					mux {
1133						groups = "uart_tx_a",
1134							 "uart_rx_a";
1135						function = "uart_a";
1136						bias-disable;
1137					};
1138				};
1139
1140				uart_a_cts_rts_pins: uart_a_cts_rts {
1141					mux {
1142						groups = "uart_cts_a",
1143							 "uart_rts_a";
1144						function = "uart_a";
1145						bias-disable;
1146					};
1147				};
1148
1149				uart_b_x_pins: uart_b_x {
1150					mux {
1151						groups = "uart_tx_b_x",
1152							 "uart_rx_b_x";
1153						function = "uart_b";
1154						bias-disable;
1155					};
1156				};
1157
1158				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1159					mux {
1160						groups = "uart_cts_b_x",
1161							 "uart_rts_b_x";
1162						function = "uart_b";
1163						bias-disable;
1164					};
1165				};
1166
1167				uart_b_z_pins: uart_b_z {
1168					mux {
1169						groups = "uart_tx_b_z",
1170							 "uart_rx_b_z";
1171						function = "uart_b";
1172						bias-disable;
1173					};
1174				};
1175
1176				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1177					mux {
1178						groups = "uart_cts_b_z",
1179							 "uart_rts_b_z";
1180						function = "uart_b";
1181						bias-disable;
1182					};
1183				};
1184
1185				uart_ao_b_z_pins: uart_ao_b_z {
1186					mux {
1187						groups = "uart_ao_tx_b_z",
1188							 "uart_ao_rx_b_z";
1189						function = "uart_ao_b_z";
1190						bias-disable;
1191					};
1192				};
1193
1194				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1195					mux {
1196						groups = "uart_ao_cts_b_z",
1197							 "uart_ao_rts_b_z";
1198						function = "uart_ao_b_z";
1199						bias-disable;
1200					};
1201				};
1202			};
1203		};
1204
1205		hiubus: bus@ff63c000 {
1206			compatible = "simple-bus";
1207			reg = <0x0 0xff63c000 0x0 0x1c00>;
1208			#address-cells = <2>;
1209			#size-cells = <2>;
1210			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1211
1212			sysctrl: system-controller@0 {
1213				compatible = "amlogic,meson-axg-hhi-sysctrl",
1214					     "simple-mfd", "syscon";
1215				reg = <0 0 0 0x400>;
1216
1217				clkc: clock-controller {
1218					compatible = "amlogic,axg-clkc";
1219					#clock-cells = <1>;
1220					clocks = <&xtal>;
1221					clock-names = "xtal";
1222				};
1223
1224				pwrc: power-controller {
1225					compatible = "amlogic,meson-axg-pwrc";
1226					#power-domain-cells = <1>;
1227					amlogic,ao-sysctrl = <&sysctrl_AO>;
1228					resets = <&reset RESET_VIU>,
1229						 <&reset RESET_VENC>,
1230						 <&reset RESET_VCBUS>,
1231						 <&reset RESET_VENCL>,
1232						 <&reset RESET_VID_LOCK>;
1233					reset-names = "viu", "venc", "vcbus",
1234						      "vencl", "vid_lock";
1235					clocks = <&clkc CLKID_VPU>,
1236						 <&clkc CLKID_VAPB>;
1237					clock-names = "vpu", "vapb";
1238					/*
1239					 * VPU clocking is provided by two identical clock paths
1240					 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1241					 * free mux to safely change frequency while running.
1242					 * Same for VAPB but with a final gate after the glitch free mux.
1243					 */
1244					assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1245							  <&clkc CLKID_VPU_0>,
1246							  <&clkc CLKID_VPU>, /* Glitch free mux */
1247							  <&clkc CLKID_VAPB_0_SEL>,
1248							  <&clkc CLKID_VAPB_0>,
1249							  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1250					assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
1251								 <0>, /* Do Nothing */
1252								 <&clkc CLKID_VPU_0>,
1253								 <&clkc CLKID_FCLK_DIV4>,
1254								 <0>, /* Do Nothing */
1255								 <&clkc CLKID_VAPB_0>;
1256					assigned-clock-rates = <0>, /* Do Nothing */
1257							       <250000000>,
1258							       <0>, /* Do Nothing */
1259							       <0>, /* Do Nothing */
1260							       <250000000>,
1261							       <0>; /* Do Nothing */
1262				};
1263
1264				mipi_pcie_analog_dphy: phy {
1265					compatible = "amlogic,axg-mipi-pcie-analog-phy";
1266					#phy-cells = <0>;
1267					status = "disabled";
1268				};
1269			};
1270		};
1271
1272		mailbox: mailbox@ff63c404 {
1273			compatible = "amlogic,meson-gxbb-mhu";
1274			reg = <0 0xff63c404 0 0x4c>;
1275			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1276				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1277				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1278			#mbox-cells = <1>;
1279		};
1280
1281		mipi_dphy: phy@ff640000 {
1282			compatible = "amlogic,axg-mipi-dphy";
1283			reg = <0x0 0xff640000 0x0 0x100>;
1284			clocks = <&clkc CLKID_MIPI_DSI_PHY>;
1285			clock-names = "pclk";
1286			resets = <&reset RESET_MIPI_PHY>;
1287			reset-names = "phy";
1288			phys = <&mipi_pcie_analog_dphy>;
1289			phy-names = "analog";
1290			#phy-cells = <0>;
1291			status = "disabled";
1292		};
1293
1294		audio: bus@ff642000 {
1295			compatible = "simple-bus";
1296			reg = <0x0 0xff642000 0x0 0x2000>;
1297			#address-cells = <2>;
1298			#size-cells = <2>;
1299			ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1300
1301			clkc_audio: clock-controller@0 {
1302				compatible = "amlogic,axg-audio-clkc";
1303				reg = <0x0 0x0 0x0 0xb4>;
1304				#clock-cells = <1>;
1305
1306				clocks = <&clkc CLKID_AUDIO>,
1307					 <&clkc CLKID_MPLL0>,
1308					 <&clkc CLKID_MPLL1>,
1309					 <&clkc CLKID_MPLL2>,
1310					 <&clkc CLKID_MPLL3>,
1311					 <&clkc CLKID_HIFI_PLL>,
1312					 <&clkc CLKID_FCLK_DIV3>,
1313					 <&clkc CLKID_FCLK_DIV4>,
1314					 <&clkc CLKID_GP0_PLL>;
1315				clock-names = "pclk",
1316					      "mst_in0",
1317					      "mst_in1",
1318					      "mst_in2",
1319					      "mst_in3",
1320					      "mst_in4",
1321					      "mst_in5",
1322					      "mst_in6",
1323					      "mst_in7";
1324
1325				resets = <&reset RESET_AUDIO>;
1326			};
1327
1328			toddr_a: audio-controller@100 {
1329				compatible = "amlogic,axg-toddr";
1330				reg = <0x0 0x100 0x0 0x2c>;
1331				#sound-dai-cells = <0>;
1332				sound-name-prefix = "TODDR_A";
1333				interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1334				clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1335				resets = <&arb AXG_ARB_TODDR_A>;
1336				amlogic,fifo-depth = <512>;
1337				status = "disabled";
1338			};
1339
1340			toddr_b: audio-controller@140 {
1341				compatible = "amlogic,axg-toddr";
1342				reg = <0x0 0x140 0x0 0x2c>;
1343				#sound-dai-cells = <0>;
1344				sound-name-prefix = "TODDR_B";
1345				interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1346				clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1347				resets = <&arb AXG_ARB_TODDR_B>;
1348				amlogic,fifo-depth = <256>;
1349				status = "disabled";
1350			};
1351
1352			toddr_c: audio-controller@180 {
1353				compatible = "amlogic,axg-toddr";
1354				reg = <0x0 0x180 0x0 0x2c>;
1355				#sound-dai-cells = <0>;
1356				sound-name-prefix = "TODDR_C";
1357				interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1358				clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1359				resets = <&arb AXG_ARB_TODDR_C>;
1360				amlogic,fifo-depth = <256>;
1361				status = "disabled";
1362			};
1363
1364			frddr_a: audio-controller@1c0 {
1365				compatible = "amlogic,axg-frddr";
1366				reg = <0x0 0x1c0 0x0 0x2c>;
1367				#sound-dai-cells = <0>;
1368				sound-name-prefix = "FRDDR_A";
1369				interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1370				clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1371				resets = <&arb AXG_ARB_FRDDR_A>;
1372				amlogic,fifo-depth = <512>;
1373				status = "disabled";
1374			};
1375
1376			frddr_b: audio-controller@200 {
1377				compatible = "amlogic,axg-frddr";
1378				reg = <0x0 0x200 0x0 0x2c>;
1379				#sound-dai-cells = <0>;
1380				sound-name-prefix = "FRDDR_B";
1381				interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1382				clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1383				resets = <&arb AXG_ARB_FRDDR_B>;
1384				amlogic,fifo-depth = <256>;
1385				status = "disabled";
1386			};
1387
1388			frddr_c: audio-controller@240 {
1389				compatible = "amlogic,axg-frddr";
1390				reg = <0x0 0x240 0x0 0x2c>;
1391				#sound-dai-cells = <0>;
1392				sound-name-prefix = "FRDDR_C";
1393				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1394				clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1395				resets = <&arb AXG_ARB_FRDDR_C>;
1396				amlogic,fifo-depth = <256>;
1397				status = "disabled";
1398			};
1399
1400			arb: reset-controller@280 {
1401				compatible = "amlogic,meson-axg-audio-arb";
1402				reg = <0x0 0x280 0x0 0x4>;
1403				#reset-cells = <1>;
1404				clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1405			};
1406
1407			tdmin_a: audio-controller@300 {
1408				compatible = "amlogic,axg-tdmin";
1409				reg = <0x0 0x300 0x0 0x40>;
1410				sound-name-prefix = "TDMIN_A";
1411				clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1412					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1413					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1414					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1415					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1416				clock-names = "pclk", "sclk", "sclk_sel",
1417					      "lrclk", "lrclk_sel";
1418				status = "disabled";
1419			};
1420
1421			tdmin_b: audio-controller@340 {
1422				compatible = "amlogic,axg-tdmin";
1423				reg = <0x0 0x340 0x0 0x40>;
1424				sound-name-prefix = "TDMIN_B";
1425				clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1426					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1427					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1428					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1429					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1430				clock-names = "pclk", "sclk", "sclk_sel",
1431					      "lrclk", "lrclk_sel";
1432				status = "disabled";
1433			};
1434
1435			tdmin_c: audio-controller@380 {
1436				compatible = "amlogic,axg-tdmin";
1437				reg = <0x0 0x380 0x0 0x40>;
1438				sound-name-prefix = "TDMIN_C";
1439				clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1440					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1441					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1442					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1443					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1444				clock-names = "pclk", "sclk", "sclk_sel",
1445					      "lrclk", "lrclk_sel";
1446				status = "disabled";
1447			};
1448
1449			tdmin_lb: audio-controller@3c0 {
1450				compatible = "amlogic,axg-tdmin";
1451				reg = <0x0 0x3c0 0x0 0x40>;
1452				sound-name-prefix = "TDMIN_LB";
1453				clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1454					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1455					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1456					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1457					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1458				clock-names = "pclk", "sclk", "sclk_sel",
1459					      "lrclk", "lrclk_sel";
1460				status = "disabled";
1461			};
1462
1463			spdifin: audio-controller@400 {
1464				compatible = "amlogic,axg-spdifin";
1465				reg = <0x0 0x400 0x0 0x30>;
1466				#sound-dai-cells = <0>;
1467				sound-name-prefix = "SPDIFIN";
1468				interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1469				clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1470					 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1471				clock-names = "pclk", "refclk";
1472				status = "disabled";
1473			};
1474
1475			spdifout: audio-controller@480 {
1476				compatible = "amlogic,axg-spdifout";
1477				reg = <0x0 0x480 0x0 0x50>;
1478				#sound-dai-cells = <0>;
1479				sound-name-prefix = "SPDIFOUT";
1480				clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1481					 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1482				clock-names = "pclk", "mclk";
1483				status = "disabled";
1484			};
1485
1486			tdmout_a: audio-controller@500 {
1487				compatible = "amlogic,axg-tdmout";
1488				reg = <0x0 0x500 0x0 0x40>;
1489				sound-name-prefix = "TDMOUT_A";
1490				clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1491					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1492					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1493					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1494					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1495				clock-names = "pclk", "sclk", "sclk_sel",
1496					      "lrclk", "lrclk_sel";
1497				status = "disabled";
1498			};
1499
1500			tdmout_b: audio-controller@540 {
1501				compatible = "amlogic,axg-tdmout";
1502				reg = <0x0 0x540 0x0 0x40>;
1503				sound-name-prefix = "TDMOUT_B";
1504				clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1505					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1506					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1507					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1508					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1509				clock-names = "pclk", "sclk", "sclk_sel",
1510					      "lrclk", "lrclk_sel";
1511				status = "disabled";
1512			};
1513
1514			tdmout_c: audio-controller@580 {
1515				compatible = "amlogic,axg-tdmout";
1516				reg = <0x0 0x580 0x0 0x40>;
1517				sound-name-prefix = "TDMOUT_C";
1518				clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1519					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1520					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1521					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1522					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1523				clock-names = "pclk", "sclk", "sclk_sel",
1524					      "lrclk", "lrclk_sel";
1525				status = "disabled";
1526			};
1527		};
1528
1529		aobus: bus@ff800000 {
1530			compatible = "simple-bus";
1531			reg = <0x0 0xff800000 0x0 0x100000>;
1532			#address-cells = <2>;
1533			#size-cells = <2>;
1534			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1535
1536			sysctrl_AO: sys-ctrl@0 {
1537				compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1538				reg =  <0x0 0x0 0x0 0x100>;
1539
1540				clkc_AO: clock-controller {
1541					compatible = "amlogic,meson-axg-aoclkc";
1542					#clock-cells = <1>;
1543					#reset-cells = <1>;
1544					clocks = <&xtal>, <&clkc CLKID_CLK81>;
1545					clock-names = "xtal", "mpeg-clk";
1546				};
1547			};
1548
1549			pinctrl_aobus: pinctrl@14 {
1550				compatible = "amlogic,meson-axg-aobus-pinctrl";
1551				#address-cells = <2>;
1552				#size-cells = <2>;
1553				ranges;
1554
1555				gpio_ao: bank@14 {
1556					reg = <0x0 0x00014 0x0 0x8>,
1557					      <0x0 0x0002c 0x0 0x4>,
1558					      <0x0 0x00024 0x0 0x8>;
1559					reg-names = "mux", "pull", "gpio";
1560					gpio-controller;
1561					#gpio-cells = <2>;
1562					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1563				};
1564
1565				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1566					mux {
1567						groups = "i2c_ao_sck_4";
1568						function = "i2c_ao";
1569						bias-disable;
1570					};
1571				};
1572
1573				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1574					mux {
1575						groups = "i2c_ao_sck_8";
1576						function = "i2c_ao";
1577						bias-disable;
1578					};
1579				};
1580
1581				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1582					mux {
1583						groups = "i2c_ao_sck_10";
1584						function = "i2c_ao";
1585						bias-disable;
1586					};
1587				};
1588
1589				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1590					mux {
1591						groups = "i2c_ao_sda_5";
1592						function = "i2c_ao";
1593						bias-disable;
1594					};
1595				};
1596
1597				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1598					mux {
1599						groups = "i2c_ao_sda_9";
1600						function = "i2c_ao";
1601						bias-disable;
1602					};
1603				};
1604
1605				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1606					mux {
1607						groups = "i2c_ao_sda_11";
1608						function = "i2c_ao";
1609						bias-disable;
1610					};
1611				};
1612
1613				remote_input_ao_pins: remote_input_ao {
1614					mux {
1615						groups = "remote_input_ao";
1616						function = "remote_input_ao";
1617						bias-disable;
1618					};
1619				};
1620
1621				uart_ao_a_pins: uart_ao_a {
1622					mux {
1623						groups = "uart_ao_tx_a",
1624							 "uart_ao_rx_a";
1625						function = "uart_ao_a";
1626						bias-disable;
1627					};
1628				};
1629
1630				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1631					mux {
1632						groups = "uart_ao_cts_a",
1633							 "uart_ao_rts_a";
1634						function = "uart_ao_a";
1635						bias-disable;
1636					};
1637				};
1638
1639				uart_ao_b_pins: uart_ao_b {
1640					mux {
1641						groups = "uart_ao_tx_b",
1642							 "uart_ao_rx_b";
1643						function = "uart_ao_b";
1644						bias-disable;
1645					};
1646				};
1647
1648				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1649					mux {
1650						groups = "uart_ao_cts_b",
1651							 "uart_ao_rts_b";
1652						function = "uart_ao_b";
1653						bias-disable;
1654					};
1655				};
1656			};
1657
1658			sec_AO: ao-secure@140 {
1659				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1660				reg = <0x0 0x140 0x0 0x140>;
1661				amlogic,has-chip-id;
1662			};
1663
1664			pwm_AO_cd: pwm@2000 {
1665				compatible = "amlogic,meson-axg-ao-pwm";
1666				reg = <0x0 0x02000  0x0 0x20>;
1667				#pwm-cells = <3>;
1668				status = "disabled";
1669			};
1670
1671			uart_AO: serial@3000 {
1672				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1673				reg = <0x0 0x3000 0x0 0x18>;
1674				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1675				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1676				clock-names = "xtal", "pclk", "baud";
1677				status = "disabled";
1678			};
1679
1680			uart_AO_B: serial@4000 {
1681				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1682				reg = <0x0 0x4000 0x0 0x18>;
1683				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1684				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1685				clock-names = "xtal", "pclk", "baud";
1686				status = "disabled";
1687			};
1688
1689			i2c_AO: i2c@5000 {
1690				compatible = "amlogic,meson-axg-i2c";
1691				reg = <0x0 0x05000 0x0 0x20>;
1692				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1693				clocks = <&clkc CLKID_AO_I2C>;
1694				#address-cells = <1>;
1695				#size-cells = <0>;
1696				status = "disabled";
1697			};
1698
1699			pwm_AO_ab: pwm@7000 {
1700				compatible = "amlogic,meson-axg-ao-pwm";
1701				reg = <0x0 0x07000 0x0 0x20>;
1702				#pwm-cells = <3>;
1703				status = "disabled";
1704			};
1705
1706			ir: ir@8000 {
1707				compatible = "amlogic,meson-gxbb-ir";
1708				reg = <0x0 0x8000 0x0 0x20>;
1709				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1710				status = "disabled";
1711			};
1712
1713			saradc: adc@9000 {
1714				compatible = "amlogic,meson-axg-saradc",
1715					"amlogic,meson-saradc";
1716				reg = <0x0 0x9000 0x0 0x38>;
1717				#io-channel-cells = <1>;
1718				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1719				clocks = <&xtal>,
1720					 <&clkc_AO CLKID_AO_SAR_ADC>,
1721					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1722					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1723				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1724				status = "disabled";
1725			};
1726		};
1727
1728		ge2d: ge2d@ff940000 {
1729			compatible = "amlogic,axg-ge2d";
1730			reg = <0x0 0xff940000 0x0 0x10000>;
1731			interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
1732			clocks = <&clkc CLKID_VAPB>;
1733			resets = <&reset RESET_GE2D>;
1734		};
1735
1736		gic: interrupt-controller@ffc01000 {
1737			compatible = "arm,gic-400";
1738			reg = <0x0 0xffc01000 0 0x1000>,
1739			      <0x0 0xffc02000 0 0x2000>,
1740			      <0x0 0xffc04000 0 0x2000>,
1741			      <0x0 0xffc06000 0 0x2000>;
1742			interrupt-controller;
1743			interrupts = <GIC_PPI 9
1744				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1745			#interrupt-cells = <3>;
1746			#address-cells = <0>;
1747		};
1748
1749		cbus: bus@ffd00000 {
1750			compatible = "simple-bus";
1751			reg = <0x0 0xffd00000 0x0 0x25000>;
1752			#address-cells = <2>;
1753			#size-cells = <2>;
1754			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1755
1756			reset: reset-controller@1004 {
1757				compatible = "amlogic,meson-axg-reset";
1758				reg = <0x0 0x01004 0x0 0x9c>;
1759				#reset-cells = <1>;
1760			};
1761
1762			gpio_intc: interrupt-controller@f080 {
1763				compatible = "amlogic,meson-axg-gpio-intc",
1764					     "amlogic,meson-gpio-intc";
1765				reg = <0x0 0xf080 0x0 0x10>;
1766				interrupt-controller;
1767				#interrupt-cells = <2>;
1768				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1769			};
1770
1771			watchdog@f0d0 {
1772				compatible = "amlogic,meson-gxbb-wdt";
1773				reg = <0x0 0xf0d0 0x0 0x10>;
1774				clocks = <&xtal>;
1775			};
1776
1777			pwm_ab: pwm@1b000 {
1778				compatible = "amlogic,meson-axg-ee-pwm";
1779				reg = <0x0 0x1b000 0x0 0x20>;
1780				#pwm-cells = <3>;
1781				status = "disabled";
1782			};
1783
1784			pwm_cd: pwm@1a000 {
1785				compatible = "amlogic,meson-axg-ee-pwm";
1786				reg = <0x0 0x1a000 0x0 0x20>;
1787				#pwm-cells = <3>;
1788				status = "disabled";
1789			};
1790
1791			spicc0: spi@13000 {
1792				compatible = "amlogic,meson-axg-spicc";
1793				reg = <0x0 0x13000 0x0 0x3c>;
1794				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1795				clocks = <&clkc CLKID_SPICC0>;
1796				clock-names = "core";
1797				#address-cells = <1>;
1798				#size-cells = <0>;
1799				status = "disabled";
1800			};
1801
1802			spicc1: spi@15000 {
1803				compatible = "amlogic,meson-axg-spicc";
1804				reg = <0x0 0x15000 0x0 0x3c>;
1805				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1806				clocks = <&clkc CLKID_SPICC1>;
1807				clock-names = "core";
1808				#address-cells = <1>;
1809				#size-cells = <0>;
1810				status = "disabled";
1811			};
1812
1813			clk_msr: clock-measure@18000 {
1814				compatible = "amlogic,meson-axg-clk-measure";
1815				reg = <0x0 0x18000 0x0 0x10>;
1816			};
1817
1818			i2c3: i2c@1c000 {
1819				compatible = "amlogic,meson-axg-i2c";
1820				reg = <0x0 0x1c000 0x0 0x20>;
1821				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1822				clocks = <&clkc CLKID_I2C>;
1823				#address-cells = <1>;
1824				#size-cells = <0>;
1825				status = "disabled";
1826			};
1827
1828			i2c2: i2c@1d000 {
1829				compatible = "amlogic,meson-axg-i2c";
1830				reg = <0x0 0x1d000 0x0 0x20>;
1831				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1832				clocks = <&clkc CLKID_I2C>;
1833				#address-cells = <1>;
1834				#size-cells = <0>;
1835				status = "disabled";
1836			};
1837
1838			i2c1: i2c@1e000 {
1839				compatible = "amlogic,meson-axg-i2c";
1840				reg = <0x0 0x1e000 0x0 0x20>;
1841				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1842				clocks = <&clkc CLKID_I2C>;
1843				#address-cells = <1>;
1844				#size-cells = <0>;
1845				status = "disabled";
1846			};
1847
1848			i2c0: i2c@1f000 {
1849				compatible = "amlogic,meson-axg-i2c";
1850				reg = <0x0 0x1f000 0x0 0x20>;
1851				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1852				clocks = <&clkc CLKID_I2C>;
1853				#address-cells = <1>;
1854				#size-cells = <0>;
1855				status = "disabled";
1856			};
1857
1858			uart_B: serial@23000 {
1859				compatible = "amlogic,meson-gx-uart";
1860				reg = <0x0 0x23000 0x0 0x18>;
1861				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1862				status = "disabled";
1863				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1864				clock-names = "xtal", "pclk", "baud";
1865			};
1866
1867			uart_A: serial@24000 {
1868				compatible = "amlogic,meson-gx-uart";
1869				reg = <0x0 0x24000 0x0 0x18>;
1870				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1871				status = "disabled";
1872				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1873				clock-names = "xtal", "pclk", "baud";
1874				fifo-size = <128>;
1875			};
1876		};
1877
1878		apb: bus@ffe00000 {
1879			compatible = "simple-bus";
1880			reg = <0x0 0xffe00000 0x0 0x200000>;
1881			#address-cells = <2>;
1882			#size-cells = <2>;
1883			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1884
1885			sd_emmc_b: sd@5000 {
1886				compatible = "amlogic,meson-axg-mmc";
1887				reg = <0x0 0x5000 0x0 0x800>;
1888				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1889				status = "disabled";
1890				clocks = <&clkc CLKID_SD_EMMC_B>,
1891					<&clkc CLKID_SD_EMMC_B_CLK0>,
1892					<&clkc CLKID_FCLK_DIV2>;
1893				clock-names = "core", "clkin0", "clkin1";
1894				resets = <&reset RESET_SD_EMMC_B>;
1895			};
1896
1897			sd_emmc_c: mmc@7000 {
1898				compatible = "amlogic,meson-axg-mmc";
1899				reg = <0x0 0x7000 0x0 0x800>;
1900				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1901				status = "disabled";
1902				clocks = <&clkc CLKID_SD_EMMC_C>,
1903					<&clkc CLKID_SD_EMMC_C_CLK0>,
1904					<&clkc CLKID_FCLK_DIV2>;
1905				clock-names = "core", "clkin0", "clkin1";
1906				resets = <&reset RESET_SD_EMMC_C>;
1907			};
1908
1909			usb2_phy1: phy@9020 {
1910				compatible = "amlogic,meson-gxl-usb2-phy";
1911				#phy-cells = <0>;
1912				reg = <0x0 0x9020 0x0 0x20>;
1913				clocks = <&clkc CLKID_USB>;
1914				clock-names = "phy";
1915				resets = <&reset RESET_USB_OTG>;
1916				reset-names = "phy";
1917			};
1918		};
1919
1920		sram: sram@fffc0000 {
1921			compatible = "mmio-sram";
1922			reg = <0x0 0xfffc0000 0x0 0x20000>;
1923			#address-cells = <1>;
1924			#size-cells = <1>;
1925			ranges = <0 0x0 0xfffc0000 0x20000>;
1926
1927			cpu_scp_lpri: scp-sram@13000 {
1928				compatible = "amlogic,meson-axg-scp-shmem";
1929				reg = <0x13000 0x400>;
1930			};
1931
1932			cpu_scp_hpri: scp-sram@13400 {
1933				compatible = "amlogic,meson-axg-scp-shmem";
1934				reg = <0x13400 0x400>;
1935			};
1936		};
1937	};
1938
1939	timer {
1940		compatible = "arm,armv8-timer";
1941		interrupts = <GIC_PPI 13
1942			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1943			     <GIC_PPI 14
1944			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1945			     <GIC_PPI 11
1946			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1947			     <GIC_PPI 10
1948			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1949	};
1950
1951	xtal: xtal-clk {
1952		compatible = "fixed-clock";
1953		clock-frequency = <24000000>;
1954		clock-output-names = "xtal";
1955		#clock-cells = <0>;
1956	};
1957};
1958