1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/axg-aoclkc.h> 7#include <dt-bindings/clock/axg-audio-clkc.h> 8#include <dt-bindings/clock/axg-clkc.h> 9#include <dt-bindings/gpio/gpio.h> 10#include <dt-bindings/gpio/meson-axg-gpio.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 14#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 15 16/ { 17 compatible = "amlogic,meson-axg"; 18 19 interrupt-parent = <&gic>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 tdmif_a: audio-controller-0 { 24 compatible = "amlogic,axg-tdm-iface"; 25 #sound-dai-cells = <0>; 26 sound-name-prefix = "TDM_A"; 27 clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 28 <&clkc_audio AUD_CLKID_MST_A_SCLK>, 29 <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 30 clock-names = "mclk", "sclk", "lrclk"; 31 status = "disabled"; 32 }; 33 34 tdmif_b: audio-controller-1 { 35 compatible = "amlogic,axg-tdm-iface"; 36 #sound-dai-cells = <0>; 37 sound-name-prefix = "TDM_B"; 38 clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 39 <&clkc_audio AUD_CLKID_MST_B_SCLK>, 40 <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 41 clock-names = "mclk", "sclk", "lrclk"; 42 status = "disabled"; 43 }; 44 45 tdmif_c: audio-controller-2 { 46 compatible = "amlogic,axg-tdm-iface"; 47 #sound-dai-cells = <0>; 48 sound-name-prefix = "TDM_C"; 49 clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 50 <&clkc_audio AUD_CLKID_MST_C_SCLK>, 51 <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 52 clock-names = "mclk", "sclk", "lrclk"; 53 status = "disabled"; 54 }; 55 56 arm-pmu { 57 compatible = "arm,cortex-a53-pmu"; 58 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 59 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 60 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 61 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 62 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 63 }; 64 65 cpus { 66 #address-cells = <0x2>; 67 #size-cells = <0x0>; 68 69 cpu0: cpu@0 { 70 device_type = "cpu"; 71 compatible = "arm,cortex-a53"; 72 reg = <0x0 0x0>; 73 enable-method = "psci"; 74 next-level-cache = <&l2>; 75 clocks = <&scpi_dvfs 0>; 76 }; 77 78 cpu1: cpu@1 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a53"; 81 reg = <0x0 0x1>; 82 enable-method = "psci"; 83 next-level-cache = <&l2>; 84 clocks = <&scpi_dvfs 0>; 85 }; 86 87 cpu2: cpu@2 { 88 device_type = "cpu"; 89 compatible = "arm,cortex-a53"; 90 reg = <0x0 0x2>; 91 enable-method = "psci"; 92 next-level-cache = <&l2>; 93 clocks = <&scpi_dvfs 0>; 94 }; 95 96 cpu3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x3>; 100 enable-method = "psci"; 101 next-level-cache = <&l2>; 102 clocks = <&scpi_dvfs 0>; 103 }; 104 105 l2: l2-cache0 { 106 compatible = "cache"; 107 }; 108 }; 109 110 sm: secure-monitor { 111 compatible = "amlogic,meson-gxbb-sm"; 112 }; 113 114 efuse: efuse { 115 compatible = "amlogic,meson-gxbb-efuse"; 116 clocks = <&clkc CLKID_EFUSE>; 117 #address-cells = <1>; 118 #size-cells = <1>; 119 read-only; 120 }; 121 122 psci { 123 compatible = "arm,psci-1.0"; 124 method = "smc"; 125 }; 126 127 reserved-memory { 128 #address-cells = <2>; 129 #size-cells = <2>; 130 ranges; 131 132 /* 16 MiB reserved for Hardware ROM Firmware */ 133 hwrom_reserved: hwrom@0 { 134 reg = <0x0 0x0 0x0 0x1000000>; 135 no-map; 136 }; 137 138 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 139 secmon_reserved: secmon@5000000 { 140 reg = <0x0 0x05000000 0x0 0x300000>; 141 no-map; 142 }; 143 }; 144 145 scpi { 146 compatible = "arm,scpi-pre-1.0"; 147 mboxes = <&mailbox 1 &mailbox 2>; 148 shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 149 150 scpi_clocks: clocks { 151 compatible = "arm,scpi-clocks"; 152 153 scpi_dvfs: clock-controller { 154 compatible = "arm,scpi-dvfs-clocks"; 155 #clock-cells = <1>; 156 clock-indices = <0>; 157 clock-output-names = "vcpu"; 158 }; 159 }; 160 161 scpi_sensors: sensors { 162 compatible = "amlogic,meson-gxbb-scpi-sensors"; 163 #thermal-sensor-cells = <1>; 164 }; 165 }; 166 167 soc { 168 compatible = "simple-bus"; 169 #address-cells = <2>; 170 #size-cells = <2>; 171 ranges; 172 173 ethmac: ethernet@ff3f0000 { 174 compatible = "amlogic,meson-axg-dwmac", 175 "snps,dwmac-3.70a", 176 "snps,dwmac"; 177 reg = <0x0 0xff3f0000 0x0 0x10000 178 0x0 0xff634540 0x0 0x8>; 179 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 180 interrupt-names = "macirq"; 181 clocks = <&clkc CLKID_ETH>, 182 <&clkc CLKID_FCLK_DIV2>, 183 <&clkc CLKID_MPLL2>; 184 clock-names = "stmmaceth", "clkin0", "clkin1"; 185 status = "disabled"; 186 }; 187 188 pdm: audio-controller@ff632000 { 189 compatible = "amlogic,axg-pdm"; 190 reg = <0x0 0xff632000 0x0 0x34>; 191 #sound-dai-cells = <0>; 192 sound-name-prefix = "PDM"; 193 clocks = <&clkc_audio AUD_CLKID_PDM>, 194 <&clkc_audio AUD_CLKID_PDM_DCLK>, 195 <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 196 clock-names = "pclk", "dclk", "sysclk"; 197 status = "disabled"; 198 }; 199 200 periphs: bus@ff634000 { 201 compatible = "simple-bus"; 202 reg = <0x0 0xff634000 0x0 0x2000>; 203 #address-cells = <2>; 204 #size-cells = <2>; 205 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 206 207 hwrng: rng@18 { 208 compatible = "amlogic,meson-rng"; 209 reg = <0x0 0x18 0x0 0x4>; 210 clocks = <&clkc CLKID_RNG0>; 211 clock-names = "core"; 212 }; 213 214 pinctrl_periphs: pinctrl@480 { 215 compatible = "amlogic,meson-axg-periphs-pinctrl"; 216 #address-cells = <2>; 217 #size-cells = <2>; 218 ranges; 219 220 gpio: bank@480 { 221 reg = <0x0 0x00480 0x0 0x40>, 222 <0x0 0x004e8 0x0 0x14>, 223 <0x0 0x00520 0x0 0x14>, 224 <0x0 0x00430 0x0 0x3c>; 225 reg-names = "mux", "pull", "pull-enable", "gpio"; 226 gpio-controller; 227 #gpio-cells = <2>; 228 gpio-ranges = <&pinctrl_periphs 0 0 86>; 229 }; 230 231 i2c0_pins: i2c0 { 232 mux { 233 groups = "i2c0_sck", 234 "i2c0_sda"; 235 function = "i2c0"; 236 bias-disable; 237 }; 238 }; 239 240 i2c1_x_pins: i2c1_x { 241 mux { 242 groups = "i2c1_sck_x", 243 "i2c1_sda_x"; 244 function = "i2c1"; 245 bias-disable; 246 }; 247 }; 248 249 i2c1_z_pins: i2c1_z { 250 mux { 251 groups = "i2c1_sck_z", 252 "i2c1_sda_z"; 253 function = "i2c1"; 254 bias-disable; 255 }; 256 }; 257 258 i2c2_a_pins: i2c2_a { 259 mux { 260 groups = "i2c2_sck_a", 261 "i2c2_sda_a"; 262 function = "i2c2"; 263 bias-disable; 264 }; 265 }; 266 267 i2c2_x_pins: i2c2_x { 268 mux { 269 groups = "i2c2_sck_x", 270 "i2c2_sda_x"; 271 function = "i2c2"; 272 bias-disable; 273 }; 274 }; 275 276 i2c3_a6_pins: i2c3_a6 { 277 mux { 278 groups = "i2c3_sda_a6", 279 "i2c3_sck_a7"; 280 function = "i2c3"; 281 bias-disable; 282 }; 283 }; 284 285 i2c3_a12_pins: i2c3_a12 { 286 mux { 287 groups = "i2c3_sda_a12", 288 "i2c3_sck_a13"; 289 function = "i2c3"; 290 bias-disable; 291 }; 292 }; 293 294 i2c3_a19_pins: i2c3_a19 { 295 mux { 296 groups = "i2c3_sda_a19", 297 "i2c3_sck_a20"; 298 function = "i2c3"; 299 bias-disable; 300 }; 301 }; 302 303 emmc_pins: emmc { 304 mux-0 { 305 groups = "emmc_nand_d0", 306 "emmc_nand_d1", 307 "emmc_nand_d2", 308 "emmc_nand_d3", 309 "emmc_nand_d4", 310 "emmc_nand_d5", 311 "emmc_nand_d6", 312 "emmc_nand_d7", 313 "emmc_cmd"; 314 function = "emmc"; 315 bias-pull-up; 316 }; 317 318 mux-1 { 319 groups = "emmc_clk"; 320 function = "emmc"; 321 bias-disable; 322 }; 323 }; 324 325 emmc_ds_pins: emmc_ds { 326 mux { 327 groups = "emmc_ds"; 328 function = "emmc"; 329 bias-pull-down; 330 }; 331 }; 332 333 emmc_clk_gate_pins: emmc_clk_gate { 334 mux { 335 groups = "BOOT_8"; 336 function = "gpio_periphs"; 337 bias-pull-down; 338 }; 339 }; 340 341 eth_rgmii_x_pins: eth-x-rgmii { 342 mux { 343 groups = "eth_mdio_x", 344 "eth_mdc_x", 345 "eth_rgmii_rx_clk_x", 346 "eth_rx_dv_x", 347 "eth_rxd0_x", 348 "eth_rxd1_x", 349 "eth_rxd2_rgmii", 350 "eth_rxd3_rgmii", 351 "eth_rgmii_tx_clk", 352 "eth_txen_x", 353 "eth_txd0_x", 354 "eth_txd1_x", 355 "eth_txd2_rgmii", 356 "eth_txd3_rgmii"; 357 function = "eth"; 358 bias-disable; 359 }; 360 }; 361 362 eth_rgmii_y_pins: eth-y-rgmii { 363 mux { 364 groups = "eth_mdio_y", 365 "eth_mdc_y", 366 "eth_rgmii_rx_clk_y", 367 "eth_rx_dv_y", 368 "eth_rxd0_y", 369 "eth_rxd1_y", 370 "eth_rxd2_rgmii", 371 "eth_rxd3_rgmii", 372 "eth_rgmii_tx_clk", 373 "eth_txen_y", 374 "eth_txd0_y", 375 "eth_txd1_y", 376 "eth_txd2_rgmii", 377 "eth_txd3_rgmii"; 378 function = "eth"; 379 bias-disable; 380 }; 381 }; 382 383 eth_rmii_x_pins: eth-x-rmii { 384 mux { 385 groups = "eth_mdio_x", 386 "eth_mdc_x", 387 "eth_rgmii_rx_clk_x", 388 "eth_rx_dv_x", 389 "eth_rxd0_x", 390 "eth_rxd1_x", 391 "eth_txen_x", 392 "eth_txd0_x", 393 "eth_txd1_x"; 394 function = "eth"; 395 bias-disable; 396 }; 397 }; 398 399 eth_rmii_y_pins: eth-y-rmii { 400 mux { 401 groups = "eth_mdio_y", 402 "eth_mdc_y", 403 "eth_rgmii_rx_clk_y", 404 "eth_rx_dv_y", 405 "eth_rxd0_y", 406 "eth_rxd1_y", 407 "eth_txen_y", 408 "eth_txd0_y", 409 "eth_txd1_y"; 410 function = "eth"; 411 bias-disable; 412 }; 413 }; 414 415 mclk_b_pins: mclk_b { 416 mux { 417 groups = "mclk_b"; 418 function = "mclk_b"; 419 bias-disable; 420 }; 421 }; 422 423 mclk_c_pins: mclk_c { 424 mux { 425 groups = "mclk_c"; 426 function = "mclk_c"; 427 bias-disable; 428 }; 429 }; 430 431 pdm_dclk_a14_pins: pdm_dclk_a14 { 432 mux { 433 groups = "pdm_dclk_a14"; 434 function = "pdm"; 435 bias-disable; 436 }; 437 }; 438 439 pdm_dclk_a19_pins: pdm_dclk_a19 { 440 mux { 441 groups = "pdm_dclk_a19"; 442 function = "pdm"; 443 bias-disable; 444 }; 445 }; 446 447 pdm_din0_pins: pdm_din0 { 448 mux { 449 groups = "pdm_din0"; 450 function = "pdm"; 451 bias-disable; 452 }; 453 }; 454 455 pdm_din1_pins: pdm_din1 { 456 mux { 457 groups = "pdm_din1"; 458 function = "pdm"; 459 bias-disable; 460 }; 461 }; 462 463 pdm_din2_pins: pdm_din2 { 464 mux { 465 groups = "pdm_din2"; 466 function = "pdm"; 467 bias-disable; 468 }; 469 }; 470 471 pdm_din3_pins: pdm_din3 { 472 mux { 473 groups = "pdm_din3"; 474 function = "pdm"; 475 bias-disable; 476 }; 477 }; 478 479 pwm_a_a_pins: pwm_a_a { 480 mux { 481 groups = "pwm_a_a"; 482 function = "pwm_a"; 483 bias-disable; 484 }; 485 }; 486 487 pwm_a_x18_pins: pwm_a_x18 { 488 mux { 489 groups = "pwm_a_x18"; 490 function = "pwm_a"; 491 bias-disable; 492 }; 493 }; 494 495 pwm_a_x20_pins: pwm_a_x20 { 496 mux { 497 groups = "pwm_a_x20"; 498 function = "pwm_a"; 499 bias-disable; 500 }; 501 }; 502 503 pwm_a_z_pins: pwm_a_z { 504 mux { 505 groups = "pwm_a_z"; 506 function = "pwm_a"; 507 bias-disable; 508 }; 509 }; 510 511 pwm_b_a_pins: pwm_b_a { 512 mux { 513 groups = "pwm_b_a"; 514 function = "pwm_b"; 515 bias-disable; 516 }; 517 }; 518 519 pwm_b_x_pins: pwm_b_x { 520 mux { 521 groups = "pwm_b_x"; 522 function = "pwm_b"; 523 bias-disable; 524 }; 525 }; 526 527 pwm_b_z_pins: pwm_b_z { 528 mux { 529 groups = "pwm_b_z"; 530 function = "pwm_b"; 531 bias-disable; 532 }; 533 }; 534 535 pwm_c_a_pins: pwm_c_a { 536 mux { 537 groups = "pwm_c_a"; 538 function = "pwm_c"; 539 bias-disable; 540 }; 541 }; 542 543 pwm_c_x10_pins: pwm_c_x10 { 544 mux { 545 groups = "pwm_c_x10"; 546 function = "pwm_c"; 547 bias-disable; 548 }; 549 }; 550 551 pwm_c_x17_pins: pwm_c_x17 { 552 mux { 553 groups = "pwm_c_x17"; 554 function = "pwm_c"; 555 bias-disable; 556 }; 557 }; 558 559 pwm_d_x11_pins: pwm_d_x11 { 560 mux { 561 groups = "pwm_d_x11"; 562 function = "pwm_d"; 563 bias-disable; 564 }; 565 }; 566 567 pwm_d_x16_pins: pwm_d_x16 { 568 mux { 569 groups = "pwm_d_x16"; 570 function = "pwm_d"; 571 bias-disable; 572 }; 573 }; 574 575 sdio_pins: sdio { 576 mux-0 { 577 groups = "sdio_d0", 578 "sdio_d1", 579 "sdio_d2", 580 "sdio_d3", 581 "sdio_cmd"; 582 function = "sdio"; 583 bias-pull-up; 584 }; 585 586 mux-1 { 587 groups = "sdio_clk"; 588 function = "sdio"; 589 bias-disable; 590 }; 591 }; 592 593 sdio_clk_gate_pins: sdio_clk_gate { 594 mux { 595 groups = "GPIOX_4"; 596 function = "gpio_periphs"; 597 bias-pull-down; 598 }; 599 }; 600 601 spdif_in_z_pins: spdif_in_z { 602 mux { 603 groups = "spdif_in_z"; 604 function = "spdif_in"; 605 bias-disable; 606 }; 607 }; 608 609 spdif_in_a1_pins: spdif_in_a1 { 610 mux { 611 groups = "spdif_in_a1"; 612 function = "spdif_in"; 613 bias-disable; 614 }; 615 }; 616 617 spdif_in_a7_pins: spdif_in_a7 { 618 mux { 619 groups = "spdif_in_a7"; 620 function = "spdif_in"; 621 bias-disable; 622 }; 623 }; 624 625 spdif_in_a19_pins: spdif_in_a19 { 626 mux { 627 groups = "spdif_in_a19"; 628 function = "spdif_in"; 629 bias-disable; 630 }; 631 }; 632 633 spdif_in_a20_pins: spdif_in_a20 { 634 mux { 635 groups = "spdif_in_a20"; 636 function = "spdif_in"; 637 bias-disable; 638 }; 639 }; 640 641 spdif_out_a1_pins: spdif_out_a1 { 642 mux { 643 groups = "spdif_out_a1"; 644 function = "spdif_out"; 645 bias-disable; 646 }; 647 }; 648 649 spdif_out_a11_pins: spdif_out_a11 { 650 mux { 651 groups = "spdif_out_a11"; 652 function = "spdif_out"; 653 bias-disable; 654 }; 655 }; 656 657 spdif_out_a19_pins: spdif_out_a19 { 658 mux { 659 groups = "spdif_out_a19"; 660 function = "spdif_out"; 661 bias-disable; 662 }; 663 }; 664 665 spdif_out_a20_pins: spdif_out_a20 { 666 mux { 667 groups = "spdif_out_a20"; 668 function = "spdif_out"; 669 bias-disable; 670 }; 671 }; 672 673 spdif_out_z_pins: spdif_out_z { 674 mux { 675 groups = "spdif_out_z"; 676 function = "spdif_out"; 677 bias-disable; 678 }; 679 }; 680 681 spi0_pins: spi0 { 682 mux { 683 groups = "spi0_miso", 684 "spi0_mosi", 685 "spi0_clk"; 686 function = "spi0"; 687 bias-disable; 688 }; 689 }; 690 691 spi0_ss0_pins: spi0_ss0 { 692 mux { 693 groups = "spi0_ss0"; 694 function = "spi0"; 695 bias-disable; 696 }; 697 }; 698 699 spi0_ss1_pins: spi0_ss1 { 700 mux { 701 groups = "spi0_ss1"; 702 function = "spi0"; 703 bias-disable; 704 }; 705 }; 706 707 spi0_ss2_pins: spi0_ss2 { 708 mux { 709 groups = "spi0_ss2"; 710 function = "spi0"; 711 bias-disable; 712 }; 713 }; 714 715 spi1_a_pins: spi1_a { 716 mux { 717 groups = "spi1_miso_a", 718 "spi1_mosi_a", 719 "spi1_clk_a"; 720 function = "spi1"; 721 bias-disable; 722 }; 723 }; 724 725 spi1_ss0_a_pins: spi1_ss0_a { 726 mux { 727 groups = "spi1_ss0_a"; 728 function = "spi1"; 729 bias-disable; 730 }; 731 }; 732 733 spi1_ss1_pins: spi1_ss1 { 734 mux { 735 groups = "spi1_ss1"; 736 function = "spi1"; 737 bias-disable; 738 }; 739 }; 740 741 spi1_x_pins: spi1_x { 742 mux { 743 groups = "spi1_miso_x", 744 "spi1_mosi_x", 745 "spi1_clk_x"; 746 function = "spi1"; 747 bias-disable; 748 }; 749 }; 750 751 spi1_ss0_x_pins: spi1_ss0_x { 752 mux { 753 groups = "spi1_ss0_x"; 754 function = "spi1"; 755 bias-disable; 756 }; 757 }; 758 759 tdma_din0_pins: tdma_din0 { 760 mux { 761 groups = "tdma_din0"; 762 function = "tdma"; 763 bias-disable; 764 }; 765 }; 766 767 tdma_dout0_x14_pins: tdma_dout0_x14 { 768 mux { 769 groups = "tdma_dout0_x14"; 770 function = "tdma"; 771 bias-disable; 772 }; 773 }; 774 775 tdma_dout0_x15_pins: tdma_dout0_x15 { 776 mux { 777 groups = "tdma_dout0_x15"; 778 function = "tdma"; 779 bias-disable; 780 }; 781 }; 782 783 tdma_dout1_pins: tdma_dout1 { 784 mux { 785 groups = "tdma_dout1"; 786 function = "tdma"; 787 bias-disable; 788 }; 789 }; 790 791 tdma_din1_pins: tdma_din1 { 792 mux { 793 groups = "tdma_din1"; 794 function = "tdma"; 795 bias-disable; 796 }; 797 }; 798 799 tdma_fs_pins: tdma_fs { 800 mux { 801 groups = "tdma_fs"; 802 function = "tdma"; 803 bias-disable; 804 }; 805 }; 806 807 tdma_fs_slv_pins: tdma_fs_slv { 808 mux { 809 groups = "tdma_fs_slv"; 810 function = "tdma"; 811 bias-disable; 812 }; 813 }; 814 815 tdma_sclk_pins: tdma_sclk { 816 mux { 817 groups = "tdma_sclk"; 818 function = "tdma"; 819 bias-disable; 820 }; 821 }; 822 823 tdma_sclk_slv_pins: tdma_sclk_slv { 824 mux { 825 groups = "tdma_sclk_slv"; 826 function = "tdma"; 827 bias-disable; 828 }; 829 }; 830 831 tdmb_din0_pins: tdmb_din0 { 832 mux { 833 groups = "tdmb_din0"; 834 function = "tdmb"; 835 bias-disable; 836 }; 837 }; 838 839 tdmb_din1_pins: tdmb_din1 { 840 mux { 841 groups = "tdmb_din1"; 842 function = "tdmb"; 843 bias-disable; 844 }; 845 }; 846 847 tdmb_din2_pins: tdmb_din2 { 848 mux { 849 groups = "tdmb_din2"; 850 function = "tdmb"; 851 bias-disable; 852 }; 853 }; 854 855 tdmb_din3_pins: tdmb_din3 { 856 mux { 857 groups = "tdmb_din3"; 858 function = "tdmb"; 859 bias-disable; 860 }; 861 }; 862 863 tdmb_dout0_pins: tdmb_dout0 { 864 mux { 865 groups = "tdmb_dout0"; 866 function = "tdmb"; 867 bias-disable; 868 }; 869 }; 870 871 tdmb_dout1_pins: tdmb_dout1 { 872 mux { 873 groups = "tdmb_dout1"; 874 function = "tdmb"; 875 bias-disable; 876 }; 877 }; 878 879 tdmb_dout2_pins: tdmb_dout2 { 880 mux { 881 groups = "tdmb_dout2"; 882 function = "tdmb"; 883 bias-disable; 884 }; 885 }; 886 887 tdmb_dout3_pins: tdmb_dout3 { 888 mux { 889 groups = "tdmb_dout3"; 890 function = "tdmb"; 891 bias-disable; 892 }; 893 }; 894 895 tdmb_fs_pins: tdmb_fs { 896 mux { 897 groups = "tdmb_fs"; 898 function = "tdmb"; 899 bias-disable; 900 }; 901 }; 902 903 tdmb_fs_slv_pins: tdmb_fs_slv { 904 mux { 905 groups = "tdmb_fs_slv"; 906 function = "tdmb"; 907 bias-disable; 908 }; 909 }; 910 911 tdmb_sclk_pins: tdmb_sclk { 912 mux { 913 groups = "tdmb_sclk"; 914 function = "tdmb"; 915 bias-disable; 916 }; 917 }; 918 919 tdmb_sclk_slv_pins: tdmb_sclk_slv { 920 mux { 921 groups = "tdmb_sclk_slv"; 922 function = "tdmb"; 923 bias-disable; 924 }; 925 }; 926 927 tdmc_fs_pins: tdmc_fs { 928 mux { 929 groups = "tdmc_fs"; 930 function = "tdmc"; 931 bias-disable; 932 }; 933 }; 934 935 tdmc_fs_slv_pins: tdmc_fs_slv { 936 mux { 937 groups = "tdmc_fs_slv"; 938 function = "tdmc"; 939 bias-disable; 940 }; 941 }; 942 943 tdmc_sclk_pins: tdmc_sclk { 944 mux { 945 groups = "tdmc_sclk"; 946 function = "tdmc"; 947 bias-disable; 948 }; 949 }; 950 951 tdmc_sclk_slv_pins: tdmc_sclk_slv { 952 mux { 953 groups = "tdmc_sclk_slv"; 954 function = "tdmc"; 955 bias-disable; 956 }; 957 }; 958 959 tdmc_din0_pins: tdmc_din0 { 960 mux { 961 groups = "tdmc_din0"; 962 function = "tdmc"; 963 bias-disable; 964 }; 965 }; 966 967 tdmc_din1_pins: tdmc_din1 { 968 mux { 969 groups = "tdmc_din1"; 970 function = "tdmc"; 971 bias-disable; 972 }; 973 }; 974 975 tdmc_din2_pins: tdmc_din2 { 976 mux { 977 groups = "tdmc_din2"; 978 function = "tdmc"; 979 bias-disable; 980 }; 981 }; 982 983 tdmc_din3_pins: tdmc_din3 { 984 mux { 985 groups = "tdmc_din3"; 986 function = "tdmc"; 987 bias-disable; 988 }; 989 }; 990 991 tdmc_dout0_pins: tdmc_dout0 { 992 mux { 993 groups = "tdmc_dout0"; 994 function = "tdmc"; 995 bias-disable; 996 }; 997 }; 998 999 tdmc_dout1_pins: tdmc_dout1 { 1000 mux { 1001 groups = "tdmc_dout1"; 1002 function = "tdmc"; 1003 bias-disable; 1004 }; 1005 }; 1006 1007 tdmc_dout2_pins: tdmc_dout2 { 1008 mux { 1009 groups = "tdmc_dout2"; 1010 function = "tdmc"; 1011 bias-disable; 1012 }; 1013 }; 1014 1015 tdmc_dout3_pins: tdmc_dout3 { 1016 mux { 1017 groups = "tdmc_dout3"; 1018 function = "tdmc"; 1019 bias-disable; 1020 }; 1021 }; 1022 1023 uart_a_pins: uart_a { 1024 mux { 1025 groups = "uart_tx_a", 1026 "uart_rx_a"; 1027 function = "uart_a"; 1028 bias-disable; 1029 }; 1030 }; 1031 1032 uart_a_cts_rts_pins: uart_a_cts_rts { 1033 mux { 1034 groups = "uart_cts_a", 1035 "uart_rts_a"; 1036 function = "uart_a"; 1037 bias-disable; 1038 }; 1039 }; 1040 1041 uart_b_x_pins: uart_b_x { 1042 mux { 1043 groups = "uart_tx_b_x", 1044 "uart_rx_b_x"; 1045 function = "uart_b"; 1046 bias-disable; 1047 }; 1048 }; 1049 1050 uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 1051 mux { 1052 groups = "uart_cts_b_x", 1053 "uart_rts_b_x"; 1054 function = "uart_b"; 1055 bias-disable; 1056 }; 1057 }; 1058 1059 uart_b_z_pins: uart_b_z { 1060 mux { 1061 groups = "uart_tx_b_z", 1062 "uart_rx_b_z"; 1063 function = "uart_b"; 1064 bias-disable; 1065 }; 1066 }; 1067 1068 uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 1069 mux { 1070 groups = "uart_cts_b_z", 1071 "uart_rts_b_z"; 1072 function = "uart_b"; 1073 bias-disable; 1074 }; 1075 }; 1076 1077 uart_ao_b_z_pins: uart_ao_b_z { 1078 mux { 1079 groups = "uart_ao_tx_b_z", 1080 "uart_ao_rx_b_z"; 1081 function = "uart_ao_b_z"; 1082 bias-disable; 1083 }; 1084 }; 1085 1086 uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 1087 mux { 1088 groups = "uart_ao_cts_b_z", 1089 "uart_ao_rts_b_z"; 1090 function = "uart_ao_b_z"; 1091 bias-disable; 1092 }; 1093 }; 1094 }; 1095 }; 1096 1097 hiubus: bus@ff63c000 { 1098 compatible = "simple-bus"; 1099 reg = <0x0 0xff63c000 0x0 0x1c00>; 1100 #address-cells = <2>; 1101 #size-cells = <2>; 1102 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 1103 1104 sysctrl: system-controller@0 { 1105 compatible = "amlogic,meson-axg-hhi-sysctrl", 1106 "simple-mfd", "syscon"; 1107 reg = <0 0 0 0x400>; 1108 1109 clkc: clock-controller { 1110 compatible = "amlogic,axg-clkc"; 1111 #clock-cells = <1>; 1112 clocks = <&xtal>; 1113 clock-names = "xtal"; 1114 }; 1115 }; 1116 }; 1117 1118 mailbox: mailbox@ff63c404 { 1119 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 1120 reg = <0 0xff63c404 0 0x4c>; 1121 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 1122 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 1123 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 1124 #mbox-cells = <1>; 1125 }; 1126 1127 audio: bus@ff642000 { 1128 compatible = "simple-bus"; 1129 reg = <0x0 0xff642000 0x0 0x2000>; 1130 #address-cells = <2>; 1131 #size-cells = <2>; 1132 ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 1133 1134 clkc_audio: clock-controller@0 { 1135 compatible = "amlogic,axg-audio-clkc"; 1136 reg = <0x0 0x0 0x0 0xb4>; 1137 #clock-cells = <1>; 1138 1139 clocks = <&clkc CLKID_AUDIO>, 1140 <&clkc CLKID_MPLL0>, 1141 <&clkc CLKID_MPLL1>, 1142 <&clkc CLKID_MPLL2>, 1143 <&clkc CLKID_MPLL3>, 1144 <&clkc CLKID_HIFI_PLL>, 1145 <&clkc CLKID_FCLK_DIV3>, 1146 <&clkc CLKID_FCLK_DIV4>, 1147 <&clkc CLKID_GP0_PLL>; 1148 clock-names = "pclk", 1149 "mst_in0", 1150 "mst_in1", 1151 "mst_in2", 1152 "mst_in3", 1153 "mst_in4", 1154 "mst_in5", 1155 "mst_in6", 1156 "mst_in7"; 1157 1158 resets = <&reset RESET_AUDIO>; 1159 }; 1160 1161 toddr_a: audio-controller@100 { 1162 compatible = "amlogic,axg-toddr"; 1163 reg = <0x0 0x100 0x0 0x1c>; 1164 #sound-dai-cells = <0>; 1165 sound-name-prefix = "TODDR_A"; 1166 interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1167 clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1168 resets = <&arb AXG_ARB_TODDR_A>; 1169 status = "disabled"; 1170 }; 1171 1172 toddr_b: audio-controller@140 { 1173 compatible = "amlogic,axg-toddr"; 1174 reg = <0x0 0x140 0x0 0x1c>; 1175 #sound-dai-cells = <0>; 1176 sound-name-prefix = "TODDR_B"; 1177 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1178 clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1179 resets = <&arb AXG_ARB_TODDR_B>; 1180 status = "disabled"; 1181 }; 1182 1183 toddr_c: audio-controller@180 { 1184 compatible = "amlogic,axg-toddr"; 1185 reg = <0x0 0x180 0x0 0x1c>; 1186 #sound-dai-cells = <0>; 1187 sound-name-prefix = "TODDR_C"; 1188 interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1189 clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1190 resets = <&arb AXG_ARB_TODDR_C>; 1191 status = "disabled"; 1192 }; 1193 1194 frddr_a: audio-controller@1c0 { 1195 compatible = "amlogic,axg-frddr"; 1196 reg = <0x0 0x1c0 0x0 0x1c>; 1197 #sound-dai-cells = <0>; 1198 sound-name-prefix = "FRDDR_A"; 1199 interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1200 clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1201 resets = <&arb AXG_ARB_FRDDR_A>; 1202 status = "disabled"; 1203 }; 1204 1205 frddr_b: audio-controller@200 { 1206 compatible = "amlogic,axg-frddr"; 1207 reg = <0x0 0x200 0x0 0x1c>; 1208 #sound-dai-cells = <0>; 1209 sound-name-prefix = "FRDDR_B"; 1210 interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1211 clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1212 resets = <&arb AXG_ARB_FRDDR_B>; 1213 status = "disabled"; 1214 }; 1215 1216 frddr_c: audio-controller@240 { 1217 compatible = "amlogic,axg-frddr"; 1218 reg = <0x0 0x240 0x0 0x1c>; 1219 #sound-dai-cells = <0>; 1220 sound-name-prefix = "FRDDR_C"; 1221 interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1222 clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1223 resets = <&arb AXG_ARB_FRDDR_C>; 1224 status = "disabled"; 1225 }; 1226 1227 arb: reset-controller@280 { 1228 compatible = "amlogic,meson-axg-audio-arb"; 1229 reg = <0x0 0x280 0x0 0x4>; 1230 #reset-cells = <1>; 1231 clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 1232 }; 1233 1234 tdmin_a: audio-controller@300 { 1235 compatible = "amlogic,axg-tdmin"; 1236 reg = <0x0 0x300 0x0 0x40>; 1237 sound-name-prefix = "TDMIN_A"; 1238 clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1239 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1240 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1241 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1242 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1243 clock-names = "pclk", "sclk", "sclk_sel", 1244 "lrclk", "lrclk_sel"; 1245 status = "disabled"; 1246 }; 1247 1248 tdmin_b: audio-controller@340 { 1249 compatible = "amlogic,axg-tdmin"; 1250 reg = <0x0 0x340 0x0 0x40>; 1251 sound-name-prefix = "TDMIN_B"; 1252 clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1253 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1254 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1255 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1256 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1257 clock-names = "pclk", "sclk", "sclk_sel", 1258 "lrclk", "lrclk_sel"; 1259 status = "disabled"; 1260 }; 1261 1262 tdmin_c: audio-controller@380 { 1263 compatible = "amlogic,axg-tdmin"; 1264 reg = <0x0 0x380 0x0 0x40>; 1265 sound-name-prefix = "TDMIN_C"; 1266 clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1267 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1268 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1269 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1270 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1271 clock-names = "pclk", "sclk", "sclk_sel", 1272 "lrclk", "lrclk_sel"; 1273 status = "disabled"; 1274 }; 1275 1276 tdmin_lb: audio-controller@3c0 { 1277 compatible = "amlogic,axg-tdmin"; 1278 reg = <0x0 0x3c0 0x0 0x40>; 1279 sound-name-prefix = "TDMIN_LB"; 1280 clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1281 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1282 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1283 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1284 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1285 clock-names = "pclk", "sclk", "sclk_sel", 1286 "lrclk", "lrclk_sel"; 1287 status = "disabled"; 1288 }; 1289 1290 spdifin: audio-controller@400 { 1291 compatible = "amlogic,axg-spdifin"; 1292 reg = <0x0 0x400 0x0 0x30>; 1293 #sound-dai-cells = <0>; 1294 sound-name-prefix = "SPDIFIN"; 1295 interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>; 1296 clocks = <&clkc_audio AUD_CLKID_SPDIFIN>, 1297 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>; 1298 clock-names = "pclk", "refclk"; 1299 status = "disabled"; 1300 }; 1301 1302 spdifout: audio-controller@480 { 1303 compatible = "amlogic,axg-spdifout"; 1304 reg = <0x0 0x480 0x0 0x50>; 1305 #sound-dai-cells = <0>; 1306 sound-name-prefix = "SPDIFOUT"; 1307 clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1308 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1309 clock-names = "pclk", "mclk"; 1310 status = "disabled"; 1311 }; 1312 1313 tdmout_a: audio-controller@500 { 1314 compatible = "amlogic,axg-tdmout"; 1315 reg = <0x0 0x500 0x0 0x40>; 1316 sound-name-prefix = "TDMOUT_A"; 1317 clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1318 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1319 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1320 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1321 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1322 clock-names = "pclk", "sclk", "sclk_sel", 1323 "lrclk", "lrclk_sel"; 1324 status = "disabled"; 1325 }; 1326 1327 tdmout_b: audio-controller@540 { 1328 compatible = "amlogic,axg-tdmout"; 1329 reg = <0x0 0x540 0x0 0x40>; 1330 sound-name-prefix = "TDMOUT_B"; 1331 clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1332 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1333 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1334 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1335 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1336 clock-names = "pclk", "sclk", "sclk_sel", 1337 "lrclk", "lrclk_sel"; 1338 status = "disabled"; 1339 }; 1340 1341 tdmout_c: audio-controller@580 { 1342 compatible = "amlogic,axg-tdmout"; 1343 reg = <0x0 0x580 0x0 0x40>; 1344 sound-name-prefix = "TDMOUT_C"; 1345 clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1346 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1347 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1348 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1349 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1350 clock-names = "pclk", "sclk", "sclk_sel", 1351 "lrclk", "lrclk_sel"; 1352 status = "disabled"; 1353 }; 1354 }; 1355 1356 aobus: bus@ff800000 { 1357 compatible = "simple-bus"; 1358 reg = <0x0 0xff800000 0x0 0x100000>; 1359 #address-cells = <2>; 1360 #size-cells = <2>; 1361 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 1362 1363 sysctrl_AO: sys-ctrl@0 { 1364 compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1365 reg = <0x0 0x0 0x0 0x100>; 1366 1367 clkc_AO: clock-controller { 1368 compatible = "amlogic,meson-axg-aoclkc"; 1369 #clock-cells = <1>; 1370 #reset-cells = <1>; 1371 clocks = <&xtal>, <&clkc CLKID_CLK81>; 1372 clock-names = "xtal", "mpeg-clk"; 1373 }; 1374 }; 1375 1376 pinctrl_aobus: pinctrl@14 { 1377 compatible = "amlogic,meson-axg-aobus-pinctrl"; 1378 #address-cells = <2>; 1379 #size-cells = <2>; 1380 ranges; 1381 1382 gpio_ao: bank@14 { 1383 reg = <0x0 0x00014 0x0 0x8>, 1384 <0x0 0x0002c 0x0 0x4>, 1385 <0x0 0x00024 0x0 0x8>; 1386 reg-names = "mux", "pull", "gpio"; 1387 gpio-controller; 1388 #gpio-cells = <2>; 1389 gpio-ranges = <&pinctrl_aobus 0 0 15>; 1390 }; 1391 1392 i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1393 mux { 1394 groups = "i2c_ao_sck_4"; 1395 function = "i2c_ao"; 1396 bias-disable; 1397 }; 1398 }; 1399 1400 i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1401 mux { 1402 groups = "i2c_ao_sck_8"; 1403 function = "i2c_ao"; 1404 bias-disable; 1405 }; 1406 }; 1407 1408 i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1409 mux { 1410 groups = "i2c_ao_sck_10"; 1411 function = "i2c_ao"; 1412 bias-disable; 1413 }; 1414 }; 1415 1416 i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1417 mux { 1418 groups = "i2c_ao_sda_5"; 1419 function = "i2c_ao"; 1420 bias-disable; 1421 }; 1422 }; 1423 1424 i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1425 mux { 1426 groups = "i2c_ao_sda_9"; 1427 function = "i2c_ao"; 1428 bias-disable; 1429 }; 1430 }; 1431 1432 i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1433 mux { 1434 groups = "i2c_ao_sda_11"; 1435 function = "i2c_ao"; 1436 bias-disable; 1437 }; 1438 }; 1439 1440 remote_input_ao_pins: remote_input_ao { 1441 mux { 1442 groups = "remote_input_ao"; 1443 function = "remote_input_ao"; 1444 bias-disable; 1445 }; 1446 }; 1447 1448 uart_ao_a_pins: uart_ao_a { 1449 mux { 1450 groups = "uart_ao_tx_a", 1451 "uart_ao_rx_a"; 1452 function = "uart_ao_a"; 1453 bias-disable; 1454 }; 1455 }; 1456 1457 uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 1458 mux { 1459 groups = "uart_ao_cts_a", 1460 "uart_ao_rts_a"; 1461 function = "uart_ao_a"; 1462 bias-disable; 1463 }; 1464 }; 1465 1466 uart_ao_b_pins: uart_ao_b { 1467 mux { 1468 groups = "uart_ao_tx_b", 1469 "uart_ao_rx_b"; 1470 function = "uart_ao_b"; 1471 bias-disable; 1472 }; 1473 }; 1474 1475 uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 1476 mux { 1477 groups = "uart_ao_cts_b", 1478 "uart_ao_rts_b"; 1479 function = "uart_ao_b"; 1480 bias-disable; 1481 }; 1482 }; 1483 }; 1484 1485 sec_AO: ao-secure@140 { 1486 compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1487 reg = <0x0 0x140 0x0 0x140>; 1488 amlogic,has-chip-id; 1489 }; 1490 1491 pwm_AO_cd: pwm@2000 { 1492 compatible = "amlogic,meson-axg-ao-pwm"; 1493 reg = <0x0 0x02000 0x0 0x20>; 1494 #pwm-cells = <3>; 1495 status = "disabled"; 1496 }; 1497 1498 uart_AO: serial@3000 { 1499 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1500 reg = <0x0 0x3000 0x0 0x18>; 1501 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 1502 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 1503 clock-names = "xtal", "pclk", "baud"; 1504 status = "disabled"; 1505 }; 1506 1507 uart_AO_B: serial@4000 { 1508 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 1509 reg = <0x0 0x4000 0x0 0x18>; 1510 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 1511 clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 1512 clock-names = "xtal", "pclk", "baud"; 1513 status = "disabled"; 1514 }; 1515 1516 i2c_AO: i2c@5000 { 1517 compatible = "amlogic,meson-axg-i2c"; 1518 reg = <0x0 0x05000 0x0 0x20>; 1519 interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 1520 clocks = <&clkc CLKID_AO_I2C>; 1521 #address-cells = <1>; 1522 #size-cells = <0>; 1523 status = "disabled"; 1524 }; 1525 1526 pwm_AO_ab: pwm@7000 { 1527 compatible = "amlogic,meson-axg-ao-pwm"; 1528 reg = <0x0 0x07000 0x0 0x20>; 1529 #pwm-cells = <3>; 1530 status = "disabled"; 1531 }; 1532 1533 ir: ir@8000 { 1534 compatible = "amlogic,meson-gxbb-ir"; 1535 reg = <0x0 0x8000 0x0 0x20>; 1536 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 1537 status = "disabled"; 1538 }; 1539 1540 saradc: adc@9000 { 1541 compatible = "amlogic,meson-axg-saradc", 1542 "amlogic,meson-saradc"; 1543 reg = <0x0 0x9000 0x0 0x38>; 1544 #io-channel-cells = <1>; 1545 interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1546 clocks = <&xtal>, 1547 <&clkc_AO CLKID_AO_SAR_ADC>, 1548 <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1549 <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1550 clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1551 status = "disabled"; 1552 }; 1553 }; 1554 1555 gic: interrupt-controller@ffc01000 { 1556 compatible = "arm,gic-400"; 1557 reg = <0x0 0xffc01000 0 0x1000>, 1558 <0x0 0xffc02000 0 0x2000>, 1559 <0x0 0xffc04000 0 0x2000>, 1560 <0x0 0xffc06000 0 0x2000>; 1561 interrupt-controller; 1562 interrupts = <GIC_PPI 9 1563 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 1564 #interrupt-cells = <3>; 1565 #address-cells = <0>; 1566 }; 1567 1568 cbus: bus@ffd00000 { 1569 compatible = "simple-bus"; 1570 reg = <0x0 0xffd00000 0x0 0x25000>; 1571 #address-cells = <2>; 1572 #size-cells = <2>; 1573 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 1574 1575 reset: reset-controller@1004 { 1576 compatible = "amlogic,meson-axg-reset"; 1577 reg = <0x0 0x01004 0x0 0x9c>; 1578 #reset-cells = <1>; 1579 }; 1580 1581 gpio_intc: interrupt-controller@f080 { 1582 compatible = "amlogic,meson-axg-gpio-intc", 1583 "amlogic,meson-gpio-intc"; 1584 reg = <0x0 0xf080 0x0 0x10>; 1585 interrupt-controller; 1586 #interrupt-cells = <2>; 1587 amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 1588 }; 1589 1590 watchdog@f0d0 { 1591 compatible = "amlogic,meson-gxbb-wdt"; 1592 reg = <0x0 0xf0d0 0x0 0x10>; 1593 clocks = <&xtal>; 1594 }; 1595 1596 pwm_ab: pwm@1b000 { 1597 compatible = "amlogic,meson-axg-ee-pwm"; 1598 reg = <0x0 0x1b000 0x0 0x20>; 1599 #pwm-cells = <3>; 1600 status = "disabled"; 1601 }; 1602 1603 pwm_cd: pwm@1a000 { 1604 compatible = "amlogic,meson-axg-ee-pwm"; 1605 reg = <0x0 0x1a000 0x0 0x20>; 1606 #pwm-cells = <3>; 1607 status = "disabled"; 1608 }; 1609 1610 spicc0: spi@13000 { 1611 compatible = "amlogic,meson-axg-spicc"; 1612 reg = <0x0 0x13000 0x0 0x3c>; 1613 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1614 clocks = <&clkc CLKID_SPICC0>; 1615 clock-names = "core"; 1616 #address-cells = <1>; 1617 #size-cells = <0>; 1618 status = "disabled"; 1619 }; 1620 1621 spicc1: spi@15000 { 1622 compatible = "amlogic,meson-axg-spicc"; 1623 reg = <0x0 0x15000 0x0 0x3c>; 1624 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1625 clocks = <&clkc CLKID_SPICC1>; 1626 clock-names = "core"; 1627 #address-cells = <1>; 1628 #size-cells = <0>; 1629 status = "disabled"; 1630 }; 1631 1632 clk_msr: clock-measure@18000 { 1633 compatible = "amlogic,meson-axg-clk-measure"; 1634 reg = <0x0 0x18000 0x0 0x10>; 1635 }; 1636 1637 i2c3: i2c@1c000 { 1638 compatible = "amlogic,meson-axg-i2c"; 1639 reg = <0x0 0x1c000 0x0 0x20>; 1640 interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 1641 clocks = <&clkc CLKID_I2C>; 1642 #address-cells = <1>; 1643 #size-cells = <0>; 1644 status = "disabled"; 1645 }; 1646 1647 i2c2: i2c@1d000 { 1648 compatible = "amlogic,meson-axg-i2c"; 1649 reg = <0x0 0x1d000 0x0 0x20>; 1650 interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 1651 clocks = <&clkc CLKID_I2C>; 1652 #address-cells = <1>; 1653 #size-cells = <0>; 1654 status = "disabled"; 1655 }; 1656 1657 i2c1: i2c@1e000 { 1658 compatible = "amlogic,meson-axg-i2c"; 1659 reg = <0x0 0x1e000 0x0 0x20>; 1660 interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 1661 clocks = <&clkc CLKID_I2C>; 1662 #address-cells = <1>; 1663 #size-cells = <0>; 1664 status = "disabled"; 1665 }; 1666 1667 i2c0: i2c@1f000 { 1668 compatible = "amlogic,meson-axg-i2c"; 1669 reg = <0x0 0x1f000 0x0 0x20>; 1670 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 1671 clocks = <&clkc CLKID_I2C>; 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 status = "disabled"; 1675 }; 1676 1677 uart_B: serial@23000 { 1678 compatible = "amlogic,meson-gx-uart"; 1679 reg = <0x0 0x23000 0x0 0x18>; 1680 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 1681 status = "disabled"; 1682 clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 1683 clock-names = "xtal", "pclk", "baud"; 1684 }; 1685 1686 uart_A: serial@24000 { 1687 compatible = "amlogic,meson-gx-uart"; 1688 reg = <0x0 0x24000 0x0 0x18>; 1689 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 1690 status = "disabled"; 1691 clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 1692 clock-names = "xtal", "pclk", "baud"; 1693 }; 1694 }; 1695 1696 apb: bus@ffe00000 { 1697 compatible = "simple-bus"; 1698 reg = <0x0 0xffe00000 0x0 0x200000>; 1699 #address-cells = <2>; 1700 #size-cells = <2>; 1701 ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 1702 1703 sd_emmc_b: sd@5000 { 1704 compatible = "amlogic,meson-axg-mmc"; 1705 reg = <0x0 0x5000 0x0 0x800>; 1706 interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 1707 status = "disabled"; 1708 clocks = <&clkc CLKID_SD_EMMC_B>, 1709 <&clkc CLKID_SD_EMMC_B_CLK0>, 1710 <&clkc CLKID_FCLK_DIV2>; 1711 clock-names = "core", "clkin0", "clkin1"; 1712 resets = <&reset RESET_SD_EMMC_B>; 1713 }; 1714 1715 sd_emmc_c: mmc@7000 { 1716 compatible = "amlogic,meson-axg-mmc"; 1717 reg = <0x0 0x7000 0x0 0x800>; 1718 interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 1719 status = "disabled"; 1720 clocks = <&clkc CLKID_SD_EMMC_C>, 1721 <&clkc CLKID_SD_EMMC_C_CLK0>, 1722 <&clkc CLKID_FCLK_DIV2>; 1723 clock-names = "core", "clkin0", "clkin1"; 1724 resets = <&reset RESET_SD_EMMC_C>; 1725 }; 1726 }; 1727 1728 sram: sram@fffc0000 { 1729 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 1730 reg = <0x0 0xfffc0000 0x0 0x20000>; 1731 #address-cells = <1>; 1732 #size-cells = <1>; 1733 ranges = <0 0x0 0xfffc0000 0x20000>; 1734 1735 cpu_scp_lpri: scp-shmem@13000 { 1736 compatible = "amlogic,meson-axg-scp-shmem"; 1737 reg = <0x13000 0x400>; 1738 }; 1739 1740 cpu_scp_hpri: scp-shmem@13400 { 1741 compatible = "amlogic,meson-axg-scp-shmem"; 1742 reg = <0x13400 0x400>; 1743 }; 1744 }; 1745 }; 1746 1747 timer { 1748 compatible = "arm,armv8-timer"; 1749 interrupts = <GIC_PPI 13 1750 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1751 <GIC_PPI 14 1752 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1753 <GIC_PPI 11 1754 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 1755 <GIC_PPI 10 1756 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 1757 }; 1758 1759 xtal: xtal-clk { 1760 compatible = "fixed-clock"; 1761 clock-frequency = <24000000>; 1762 clock-output-names = "xtal"; 1763 #clock-cells = <0>; 1764 }; 1765}; 1766