1/* 2 * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT) 5 */ 6 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/clock/axg-clkc.h> 11 12/ { 13 compatible = "amlogic,meson-axg"; 14 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 reserved-memory { 20 #address-cells = <2>; 21 #size-cells = <2>; 22 ranges; 23 24 /* 16 MiB reserved for Hardware ROM Firmware */ 25 hwrom_reserved: hwrom@0 { 26 reg = <0x0 0x0 0x0 0x1000000>; 27 no-map; 28 }; 29 30 /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 31 secmon_reserved: secmon@5000000 { 32 reg = <0x0 0x05000000 0x0 0x300000>; 33 no-map; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <0x2>; 39 #size-cells = <0x0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53", "arm,armv8"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 next-level-cache = <&l2>; 47 }; 48 49 cpu1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 reg = <0x0 0x1>; 53 enable-method = "psci"; 54 next-level-cache = <&l2>; 55 }; 56 57 cpu2: cpu@2 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 reg = <0x0 0x2>; 61 enable-method = "psci"; 62 next-level-cache = <&l2>; 63 }; 64 65 cpu3: cpu@3 { 66 device_type = "cpu"; 67 compatible = "arm,cortex-a53", "arm,armv8"; 68 reg = <0x0 0x3>; 69 enable-method = "psci"; 70 next-level-cache = <&l2>; 71 }; 72 73 l2: l2-cache0 { 74 compatible = "cache"; 75 }; 76 }; 77 78 arm-pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 85 }; 86 87 psci { 88 compatible = "arm,psci-1.0"; 89 method = "smc"; 90 }; 91 92 timer { 93 compatible = "arm,armv8-timer"; 94 interrupts = <GIC_PPI 13 95 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 96 <GIC_PPI 14 97 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 98 <GIC_PPI 11 99 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 100 <GIC_PPI 10 101 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 102 }; 103 104 xtal: xtal-clk { 105 compatible = "fixed-clock"; 106 clock-frequency = <24000000>; 107 clock-output-names = "xtal"; 108 #clock-cells = <0>; 109 }; 110 111 soc { 112 compatible = "simple-bus"; 113 #address-cells = <2>; 114 #size-cells = <2>; 115 ranges; 116 117 cbus: bus@ffd00000 { 118 compatible = "simple-bus"; 119 reg = <0x0 0xffd00000 0x0 0x25000>; 120 #address-cells = <2>; 121 #size-cells = <2>; 122 ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 123 124 pwm_ab: pwm@1b000 { 125 compatible = "amlogic,meson-axg-ee-pwm"; 126 reg = <0x0 0x1b000 0x0 0x20>; 127 #pwm-cells = <3>; 128 status = "disabled"; 129 }; 130 131 pwm_cd: pwm@1a000 { 132 compatible = "amlogic,meson-axg-ee-pwm"; 133 reg = <0x0 0x1a000 0x0 0x20>; 134 #pwm-cells = <3>; 135 status = "disabled"; 136 }; 137 138 reset: reset-controller@1004 { 139 compatible = "amlogic,meson-axg-reset"; 140 reg = <0x0 0x01004 0x0 0x9c>; 141 #reset-cells = <1>; 142 }; 143 144 spicc0: spi@13000 { 145 compatible = "amlogic,meson-axg-spicc"; 146 reg = <0x0 0x13000 0x0 0x3c>; 147 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 148 clocks = <&clkc CLKID_SPICC0>; 149 clock-names = "core"; 150 #address-cells = <1>; 151 #size-cells = <0>; 152 status = "disabled"; 153 }; 154 155 spicc1: spi@15000 { 156 compatible = "amlogic,meson-axg-spicc"; 157 reg = <0x0 0x15000 0x0 0x3c>; 158 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&clkc CLKID_SPICC1>; 160 clock-names = "core"; 161 #address-cells = <1>; 162 #size-cells = <0>; 163 status = "disabled"; 164 }; 165 166 uart_A: serial@24000 { 167 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 168 reg = <0x0 0x24000 0x0 0x14>; 169 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 170 status = "disabled"; 171 }; 172 173 uart_B: serial@23000 { 174 compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart"; 175 reg = <0x0 0x23000 0x0 0x14>; 176 interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 177 status = "disabled"; 178 }; 179 }; 180 181 ethmac: ethernet@ff3f0000 { 182 compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac"; 183 reg = <0x0 0xff3f0000 0x0 0x10000 184 0x0 0xff634540 0x0 0x8>; 185 interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 186 interrupt-names = "macirq"; 187 clocks = <&clkc CLKID_ETH>, 188 <&clkc CLKID_FCLK_DIV2>, 189 <&clkc CLKID_MPLL2>; 190 clock-names = "stmmaceth", "clkin0", "clkin1"; 191 status = "disabled"; 192 }; 193 194 gic: interrupt-controller@ffc01000 { 195 compatible = "arm,gic-400"; 196 reg = <0x0 0xffc01000 0 0x1000>, 197 <0x0 0xffc02000 0 0x2000>, 198 <0x0 0xffc04000 0 0x2000>, 199 <0x0 0xffc06000 0 0x2000>; 200 interrupt-controller; 201 interrupts = <GIC_PPI 9 202 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 203 #interrupt-cells = <3>; 204 #address-cells = <0>; 205 }; 206 207 hiubus: bus@ff63c000 { 208 compatible = "simple-bus"; 209 reg = <0x0 0xff63c000 0x0 0x1c00>; 210 #address-cells = <2>; 211 #size-cells = <2>; 212 ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 213 214 clkc: clock-controller@0 { 215 compatible = "amlogic,axg-clkc"; 216 #clock-cells = <1>; 217 reg = <0x0 0x0 0x0 0x320>; 218 }; 219 }; 220 221 mailbox: mailbox@ff63dc00 { 222 compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 223 reg = <0 0xff63dc00 0 0x400>; 224 interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 225 <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 226 <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 227 #mbox-cells = <1>; 228 }; 229 230 periphs: periphs@ff634000 { 231 compatible = "simple-bus"; 232 reg = <0x0 0xff634000 0x0 0x2000>; 233 #address-cells = <2>; 234 #size-cells = <2>; 235 ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 236 237 pinctrl_periphs: pinctrl@480 { 238 compatible = "amlogic,meson-axg-periphs-pinctrl"; 239 #address-cells = <2>; 240 #size-cells = <2>; 241 ranges; 242 243 gpio: bank@480 { 244 reg = <0x0 0x00480 0x0 0x40>, 245 <0x0 0x004e8 0x0 0x14>, 246 <0x0 0x00520 0x0 0x14>, 247 <0x0 0x00430 0x0 0x3c>; 248 reg-names = "mux", "pull", "pull-enable", "gpio"; 249 gpio-controller; 250 #gpio-cells = <2>; 251 gpio-ranges = <&pinctrl_periphs 0 0 86>; 252 }; 253 254 eth_rgmii_x_pins: eth-x-rgmii { 255 mux { 256 groups = "eth_mdio_x", 257 "eth_mdc_x", 258 "eth_rgmii_rx_clk_x", 259 "eth_rx_dv_x", 260 "eth_rxd0_x", 261 "eth_rxd1_x", 262 "eth_rxd2_rgmii", 263 "eth_rxd3_rgmii", 264 "eth_rgmii_tx_clk", 265 "eth_txen_x", 266 "eth_txd0_x", 267 "eth_txd1_x", 268 "eth_txd2_rgmii", 269 "eth_txd3_rgmii"; 270 function = "eth"; 271 }; 272 }; 273 274 eth_rgmii_y_pins: eth-y-rgmii { 275 mux { 276 groups = "eth_mdio_y", 277 "eth_mdc_y", 278 "eth_rgmii_rx_clk_y", 279 "eth_rx_dv_y", 280 "eth_rxd0_y", 281 "eth_rxd1_y", 282 "eth_rxd2_rgmii", 283 "eth_rxd3_rgmii", 284 "eth_rgmii_tx_clk", 285 "eth_txen_y", 286 "eth_txd0_y", 287 "eth_txd1_y", 288 "eth_txd2_rgmii", 289 "eth_txd3_rgmii"; 290 function = "eth"; 291 }; 292 }; 293 294 pwm_a_a_pins: pwm_a_a { 295 mux { 296 groups = "pwm_a_a"; 297 function = "pwm_a"; 298 }; 299 }; 300 301 pwm_a_x18_pins: pwm_a_x18 { 302 mux { 303 groups = "pwm_a_x18"; 304 function = "pwm_a"; 305 }; 306 }; 307 308 pwm_a_x20_pins: pwm_a_x20 { 309 mux { 310 groups = "pwm_a_x20"; 311 function = "pwm_a"; 312 }; 313 }; 314 315 pwm_a_z_pins: pwm_a_z { 316 mux { 317 groups = "pwm_a_z"; 318 function = "pwm_a"; 319 }; 320 }; 321 322 pwm_b_a_pins: pwm_b_a { 323 mux { 324 groups = "pwm_b_a"; 325 function = "pwm_b"; 326 }; 327 }; 328 329 pwm_b_x_pins: pwm_b_x { 330 mux { 331 groups = "pwm_b_x"; 332 function = "pwm_b"; 333 }; 334 }; 335 336 pwm_b_z_pins: pwm_b_z { 337 mux { 338 groups = "pwm_b_z"; 339 function = "pwm_b"; 340 }; 341 }; 342 343 pwm_c_a_pins: pwm_c_a { 344 mux { 345 groups = "pwm_c_a"; 346 function = "pwm_c"; 347 }; 348 }; 349 350 pwm_c_x10_pins: pwm_c_x10 { 351 mux { 352 groups = "pwm_c_x10"; 353 function = "pwm_c"; 354 }; 355 }; 356 357 pwm_c_x17_pins: pwm_c_x17 { 358 mux { 359 groups = "pwm_c_x17"; 360 function = "pwm_c"; 361 }; 362 }; 363 364 pwm_d_x11_pins: pwm_d_x11 { 365 mux { 366 groups = "pwm_d_x11"; 367 function = "pwm_d"; 368 }; 369 }; 370 371 pwm_d_x16_pins: pwm_d_x16 { 372 mux { 373 groups = "pwm_d_x16"; 374 function = "pwm_d"; 375 }; 376 }; 377 378 spi0_pins: spi0 { 379 mux { 380 groups = "spi0_miso", 381 "spi0_mosi", 382 "spi0_clk"; 383 function = "spi0"; 384 }; 385 }; 386 387 spi0_ss0_pins: spi0_ss0 { 388 mux { 389 groups = "spi0_ss0"; 390 function = "spi0"; 391 }; 392 }; 393 394 spi0_ss1_pins: spi0_ss1 { 395 mux { 396 groups = "spi0_ss1"; 397 function = "spi0"; 398 }; 399 }; 400 401 spi0_ss2_pins: spi0_ss2 { 402 mux { 403 groups = "spi0_ss2"; 404 function = "spi0"; 405 }; 406 }; 407 408 409 spi1_a_pins: spi1_a { 410 mux { 411 groups = "spi1_miso_a", 412 "spi1_mosi_a", 413 "spi1_clk_a"; 414 function = "spi1"; 415 }; 416 }; 417 418 spi1_ss0_a_pins: spi1_ss0_a { 419 mux { 420 groups = "spi1_ss0_a"; 421 function = "spi1"; 422 }; 423 }; 424 425 spi1_ss1_pins: spi1_ss1 { 426 mux { 427 groups = "spi1_ss1"; 428 function = "spi1"; 429 }; 430 }; 431 432 spi1_x_pins: spi1_x { 433 mux { 434 groups = "spi1_miso_x", 435 "spi1_mosi_x", 436 "spi1_clk_x"; 437 function = "spi1"; 438 }; 439 }; 440 441 spi1_ss0_x_pins: spi1_ss0_x { 442 mux { 443 groups = "spi1_ss0_x"; 444 function = "spi1"; 445 }; 446 }; 447 }; 448 }; 449 450 sram: sram@fffc0000 { 451 compatible = "amlogic,meson-axg-sram", "mmio-sram"; 452 reg = <0x0 0xfffc0000 0x0 0x20000>; 453 #address-cells = <1>; 454 #size-cells = <1>; 455 ranges = <0 0x0 0xfffc0000 0x20000>; 456 457 cpu_scp_lpri: scp-shmem@0 { 458 compatible = "amlogic,meson-axg-scp-shmem"; 459 reg = <0x13000 0x400>; 460 }; 461 462 cpu_scp_hpri: scp-shmem@200 { 463 compatible = "amlogic,meson-axg-scp-shmem"; 464 reg = <0x13400 0x400>; 465 }; 466 }; 467 468 aobus: bus@ff800000 { 469 compatible = "simple-bus"; 470 reg = <0x0 0xff800000 0x0 0x100000>; 471 #address-cells = <2>; 472 #size-cells = <2>; 473 ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 474 475 pinctrl_aobus: pinctrl@14 { 476 compatible = "amlogic,meson-axg-aobus-pinctrl"; 477 #address-cells = <2>; 478 #size-cells = <2>; 479 ranges; 480 481 gpio_ao: bank@14 { 482 reg = <0x0 0x00014 0x0 0x8>, 483 <0x0 0x0002c 0x0 0x4>, 484 <0x0 0x00024 0x0 0x8>; 485 reg-names = "mux", "pull", "gpio"; 486 gpio-controller; 487 #gpio-cells = <2>; 488 gpio-ranges = <&pinctrl_aobus 0 0 15>; 489 }; 490 491 remote_input_ao_pins: remote_input_ao { 492 mux { 493 groups = "remote_input_ao"; 494 function = "remote_input_ao"; 495 }; 496 }; 497 }; 498 499 pwm_AO_ab: pwm@7000 { 500 compatible = "amlogic,meson-axg-ao-pwm"; 501 reg = <0x0 0x07000 0x0 0x20>; 502 #pwm-cells = <3>; 503 status = "disabled"; 504 }; 505 506 pwm_AO_cd: pwm@2000 { 507 compatible = "amlogic,axg-ao-pwm"; 508 reg = <0x0 0x02000 0x0 0x20>; 509 #pwm-cells = <3>; 510 status = "disabled"; 511 }; 512 513 uart_AO: serial@3000 { 514 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 515 reg = <0x0 0x3000 0x0 0x18>; 516 interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 517 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; 518 clock-names = "xtal", "pclk", "baud"; 519 status = "disabled"; 520 }; 521 522 uart_AO_B: serial@4000 { 523 compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 524 reg = <0x0 0x4000 0x0 0x18>; 525 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 526 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>; 527 clock-names = "xtal", "pclk", "baud"; 528 status = "disabled"; 529 }; 530 531 ir: ir@8000 { 532 compatible = "amlogic,meson-gxbb-ir"; 533 reg = <0x0 0x8000 0x0 0x20>; 534 interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 535 status = "disabled"; 536 }; 537 }; 538 }; 539}; 540