1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
4 */
5
6#include <dt-bindings/clock/axg-aoclkc.h>
7#include <dt-bindings/clock/axg-audio-clkc.h>
8#include <dt-bindings/clock/axg-clkc.h>
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/gpio/meson-axg-gpio.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h>
14#include <dt-bindings/reset/amlogic,meson-axg-reset.h>
15#include <dt-bindings/power/meson-axg-power.h>
16
17/ {
18	compatible = "amlogic,meson-axg";
19
20	interrupt-parent = <&gic>;
21	#address-cells = <2>;
22	#size-cells = <2>;
23
24	tdmif_a: audio-controller-0 {
25		compatible = "amlogic,axg-tdm-iface";
26		#sound-dai-cells = <0>;
27		sound-name-prefix = "TDM_A";
28		clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>,
29			 <&clkc_audio AUD_CLKID_MST_A_SCLK>,
30			 <&clkc_audio AUD_CLKID_MST_A_LRCLK>;
31		clock-names = "mclk", "sclk", "lrclk";
32		status = "disabled";
33	};
34
35	tdmif_b: audio-controller-1 {
36		compatible = "amlogic,axg-tdm-iface";
37		#sound-dai-cells = <0>;
38		sound-name-prefix = "TDM_B";
39		clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>,
40			 <&clkc_audio AUD_CLKID_MST_B_SCLK>,
41			 <&clkc_audio AUD_CLKID_MST_B_LRCLK>;
42		clock-names = "mclk", "sclk", "lrclk";
43		status = "disabled";
44	};
45
46	tdmif_c: audio-controller-2 {
47		compatible = "amlogic,axg-tdm-iface";
48		#sound-dai-cells = <0>;
49		sound-name-prefix = "TDM_C";
50		clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>,
51			 <&clkc_audio AUD_CLKID_MST_C_SCLK>,
52			 <&clkc_audio AUD_CLKID_MST_C_LRCLK>;
53		clock-names = "mclk", "sclk", "lrclk";
54		status = "disabled";
55	};
56
57	arm-pmu {
58		compatible = "arm,cortex-a53-pmu";
59		interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
60			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
61			     <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
62			     <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
63		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
64	};
65
66	cpus {
67		#address-cells = <0x2>;
68		#size-cells = <0x0>;
69
70		cpu0: cpu@0 {
71			device_type = "cpu";
72			compatible = "arm,cortex-a53";
73			reg = <0x0 0x0>;
74			enable-method = "psci";
75			next-level-cache = <&l2>;
76			clocks = <&scpi_dvfs 0>;
77		};
78
79		cpu1: cpu@1 {
80			device_type = "cpu";
81			compatible = "arm,cortex-a53";
82			reg = <0x0 0x1>;
83			enable-method = "psci";
84			next-level-cache = <&l2>;
85			clocks = <&scpi_dvfs 0>;
86		};
87
88		cpu2: cpu@2 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a53";
91			reg = <0x0 0x2>;
92			enable-method = "psci";
93			next-level-cache = <&l2>;
94			clocks = <&scpi_dvfs 0>;
95		};
96
97		cpu3: cpu@3 {
98			device_type = "cpu";
99			compatible = "arm,cortex-a53";
100			reg = <0x0 0x3>;
101			enable-method = "psci";
102			next-level-cache = <&l2>;
103			clocks = <&scpi_dvfs 0>;
104		};
105
106		l2: l2-cache0 {
107			compatible = "cache";
108			cache-level = <2>;
109		};
110	};
111
112	sm: secure-monitor {
113		compatible = "amlogic,meson-gxbb-sm";
114	};
115
116	efuse: efuse {
117		compatible = "amlogic,meson-gxbb-efuse";
118		clocks = <&clkc CLKID_EFUSE>;
119		#address-cells = <1>;
120		#size-cells = <1>;
121		read-only;
122		secure-monitor = <&sm>;
123	};
124
125	psci {
126		compatible = "arm,psci-1.0";
127		method = "smc";
128	};
129
130	reserved-memory {
131		#address-cells = <2>;
132		#size-cells = <2>;
133		ranges;
134
135		/* 16 MiB reserved for Hardware ROM Firmware */
136		hwrom_reserved: hwrom@0 {
137			reg = <0x0 0x0 0x0 0x1000000>;
138			no-map;
139		};
140
141		/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
142		secmon_reserved: secmon@5000000 {
143			reg = <0x0 0x05000000 0x0 0x300000>;
144			no-map;
145		};
146	};
147
148	scpi {
149		compatible = "arm,scpi-pre-1.0";
150		mboxes = <&mailbox 1 &mailbox 2>;
151		shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
152
153		scpi_clocks: clocks {
154			compatible = "arm,scpi-clocks";
155
156			scpi_dvfs: clock-controller {
157				compatible = "arm,scpi-dvfs-clocks";
158				#clock-cells = <1>;
159				clock-indices = <0>;
160				clock-output-names = "vcpu";
161			};
162		};
163
164		scpi_sensors: sensors {
165			compatible = "amlogic,meson-gxbb-scpi-sensors";
166			#thermal-sensor-cells = <1>;
167		};
168	};
169
170	soc {
171		compatible = "simple-bus";
172		#address-cells = <2>;
173		#size-cells = <2>;
174		ranges;
175
176		pcieA: pcie@f9800000 {
177			compatible = "amlogic,axg-pcie", "snps,dw-pcie";
178			reg = <0x0 0xf9800000 0x0 0x400000>,
179			      <0x0 0xff646000 0x0 0x2000>,
180			      <0x0 0xf9f00000 0x0 0x100000>;
181			reg-names = "elbi", "cfg", "config";
182			interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
183			#interrupt-cells = <1>;
184			interrupt-map-mask = <0 0 0 0>;
185			interrupt-map = <0 0 0 0 &gic GIC_SPI 179 IRQ_TYPE_EDGE_RISING>;
186			bus-range = <0x0 0xff>;
187			#address-cells = <3>;
188			#size-cells = <2>;
189			device_type = "pci";
190			ranges = <0x82000000 0 0xf9c00000 0x0 0xf9c00000 0 0x00300000>;
191
192			clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_A>, <&clkc CLKID_PCIE_CML_EN0>;
193			clock-names = "general", "pclk", "port";
194			resets = <&reset RESET_PCIE_A>, <&reset RESET_PCIE_APB>;
195			reset-names = "port", "apb";
196			num-lanes = <1>;
197			phys = <&pcie_phy>;
198			phy-names = "pcie";
199			status = "disabled";
200		};
201
202		pcieB: pcie@fa000000 {
203			compatible = "amlogic,axg-pcie", "snps,dw-pcie";
204			reg = <0x0 0xfa000000 0x0 0x400000>,
205			      <0x0 0xff648000 0x0 0x2000>,
206			      <0x0 0xfa400000 0x0 0x100000>;
207			reg-names = "elbi", "cfg", "config";
208			interrupts = <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
209			#interrupt-cells = <1>;
210			interrupt-map-mask = <0 0 0 0>;
211			interrupt-map = <0 0 0 0 &gic GIC_SPI 169 IRQ_TYPE_EDGE_RISING>;
212			bus-range = <0x0 0xff>;
213			#address-cells = <3>;
214			#size-cells = <2>;
215			device_type = "pci";
216			ranges = <0x82000000 0 0xfa500000 0x0 0xfa500000 0 0x00300000>;
217
218			clocks = <&clkc CLKID_USB>, <&clkc CLKID_PCIE_B>, <&clkc CLKID_PCIE_CML_EN1>;
219			clock-names = "general", "pclk", "port";
220			resets = <&reset RESET_PCIE_B>, <&reset RESET_PCIE_APB>;
221			reset-names = "port", "apb";
222			num-lanes = <1>;
223			phys = <&pcie_phy>;
224			phy-names = "pcie";
225			status = "disabled";
226		};
227
228		usb: usb@ffe09080 {
229			compatible = "amlogic,meson-axg-usb-ctrl";
230			reg = <0x0 0xffe09080 0x0 0x20>;
231			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
232			#address-cells = <2>;
233			#size-cells = <2>;
234			ranges;
235
236			clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1_DDR_BRIDGE>;
237			clock-names = "usb_ctrl", "ddr";
238			resets = <&reset RESET_USB_OTG>;
239
240			dr_mode = "otg";
241
242			phys = <&usb2_phy1>;
243			phy-names = "usb2-phy1";
244
245			dwc2: usb@ff400000 {
246				compatible = "amlogic,meson-g12a-usb", "snps,dwc2";
247				reg = <0x0 0xff400000 0x0 0x40000>;
248				interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
249				clocks = <&clkc CLKID_USB1>;
250				clock-names = "otg";
251				phys = <&usb2_phy1>;
252				dr_mode = "peripheral";
253				g-rx-fifo-size = <192>;
254				g-np-tx-fifo-size = <128>;
255				g-tx-fifo-size = <128 128 16 16 16>;
256			};
257
258			dwc3: usb@ff500000 {
259				compatible = "snps,dwc3";
260				reg = <0x0 0xff500000 0x0 0x100000>;
261				interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
262				dr_mode = "host";
263				maximum-speed = "high-speed";
264				snps,dis_u2_susphy_quirk;
265			};
266		};
267
268		ethmac: ethernet@ff3f0000 {
269			compatible = "amlogic,meson-axg-dwmac",
270				     "snps,dwmac-3.70a",
271				     "snps,dwmac";
272			reg = <0x0 0xff3f0000 0x0 0x10000>,
273			      <0x0 0xff634540 0x0 0x8>;
274			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
275			interrupt-names = "macirq";
276			clocks = <&clkc CLKID_ETH>,
277				 <&clkc CLKID_FCLK_DIV2>,
278				 <&clkc CLKID_MPLL2>,
279				 <&clkc CLKID_FCLK_DIV2>;
280			clock-names = "stmmaceth", "clkin0", "clkin1",
281				      "timing-adjustment";
282			rx-fifo-depth = <4096>;
283			tx-fifo-depth = <2048>;
284			power-domains = <&pwrc PWRC_AXG_ETHERNET_MEM_ID>;
285			status = "disabled";
286		};
287
288		pcie_phy: phy@ff644000 {
289			compatible = "amlogic,axg-pcie-phy";
290			reg = <0x0 0xff644000 0x0 0x1c>;
291			resets = <&reset RESET_PCIE_PHY>;
292			phys = <&mipi_pcie_analog_dphy>;
293			phy-names = "analog";
294			#phy-cells = <0>;
295		};
296
297		pdm: audio-controller@ff632000 {
298			compatible = "amlogic,axg-pdm";
299			reg = <0x0 0xff632000 0x0 0x34>;
300			#sound-dai-cells = <0>;
301			sound-name-prefix = "PDM";
302			clocks = <&clkc_audio AUD_CLKID_PDM>,
303				 <&clkc_audio AUD_CLKID_PDM_DCLK>,
304				 <&clkc_audio AUD_CLKID_PDM_SYSCLK>;
305			clock-names = "pclk", "dclk", "sysclk";
306			status = "disabled";
307		};
308
309		periphs: bus@ff634000 {
310			compatible = "simple-bus";
311			reg = <0x0 0xff634000 0x0 0x2000>;
312			#address-cells = <2>;
313			#size-cells = <2>;
314			ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
315
316			hwrng: rng@18 {
317				compatible = "amlogic,meson-rng";
318				reg = <0x0 0x18 0x0 0x4>;
319				clocks = <&clkc CLKID_RNG0>;
320				clock-names = "core";
321			};
322
323			pinctrl_periphs: pinctrl@480 {
324				compatible = "amlogic,meson-axg-periphs-pinctrl";
325				#address-cells = <2>;
326				#size-cells = <2>;
327				ranges;
328
329				gpio: bank@480 {
330					reg = <0x0 0x00480 0x0 0x40>,
331					      <0x0 0x004e8 0x0 0x14>,
332					      <0x0 0x00520 0x0 0x14>,
333					      <0x0 0x00430 0x0 0x3c>;
334					reg-names = "mux", "pull", "pull-enable", "gpio";
335					gpio-controller;
336					#gpio-cells = <2>;
337					gpio-ranges = <&pinctrl_periphs 0 0 86>;
338				};
339
340				i2c0_pins: i2c0 {
341					mux {
342						groups = "i2c0_sck",
343							 "i2c0_sda";
344						function = "i2c0";
345						bias-disable;
346					};
347				};
348
349				i2c1_x_pins: i2c1_x {
350					mux {
351						groups = "i2c1_sck_x",
352							 "i2c1_sda_x";
353						function = "i2c1";
354						bias-disable;
355					};
356				};
357
358				i2c1_z_pins: i2c1_z {
359					mux {
360						groups = "i2c1_sck_z",
361							 "i2c1_sda_z";
362						function = "i2c1";
363						bias-disable;
364					};
365				};
366
367				i2c2_a_pins: i2c2_a {
368					mux {
369						groups = "i2c2_sck_a",
370							 "i2c2_sda_a";
371						function = "i2c2";
372						bias-disable;
373					};
374				};
375
376				i2c2_x_pins: i2c2_x {
377					mux {
378						groups = "i2c2_sck_x",
379							 "i2c2_sda_x";
380						function = "i2c2";
381						bias-disable;
382					};
383				};
384
385				i2c3_a6_pins: i2c3_a6 {
386					mux {
387						groups = "i2c3_sda_a6",
388							 "i2c3_sck_a7";
389						function = "i2c3";
390						bias-disable;
391					};
392				};
393
394				i2c3_a12_pins: i2c3_a12 {
395					mux {
396						groups = "i2c3_sda_a12",
397							 "i2c3_sck_a13";
398						function = "i2c3";
399						bias-disable;
400					};
401				};
402
403				i2c3_a19_pins: i2c3_a19 {
404					mux {
405						groups = "i2c3_sda_a19",
406							 "i2c3_sck_a20";
407						function = "i2c3";
408						bias-disable;
409					};
410				};
411
412				emmc_pins: emmc {
413					mux-0 {
414						groups = "emmc_nand_d0",
415							 "emmc_nand_d1",
416							 "emmc_nand_d2",
417							 "emmc_nand_d3",
418							 "emmc_nand_d4",
419							 "emmc_nand_d5",
420							 "emmc_nand_d6",
421							 "emmc_nand_d7",
422							 "emmc_cmd";
423						function = "emmc";
424						bias-pull-up;
425					};
426
427					mux-1 {
428						groups = "emmc_clk";
429						function = "emmc";
430						bias-disable;
431					};
432				};
433
434				emmc_ds_pins: emmc_ds {
435					mux {
436						groups = "emmc_ds";
437						function = "emmc";
438						bias-pull-down;
439					};
440				};
441
442				emmc_clk_gate_pins: emmc_clk_gate {
443					mux {
444						groups = "BOOT_8";
445						function = "gpio_periphs";
446						bias-pull-down;
447					};
448				};
449
450				eth_rgmii_x_pins: eth-x-rgmii {
451					mux {
452						groups = "eth_mdio_x",
453							 "eth_mdc_x",
454							 "eth_rgmii_rx_clk_x",
455							 "eth_rx_dv_x",
456							 "eth_rxd0_x",
457							 "eth_rxd1_x",
458							 "eth_rxd2_rgmii",
459							 "eth_rxd3_rgmii",
460							 "eth_rgmii_tx_clk",
461							 "eth_txen_x",
462							 "eth_txd0_x",
463							 "eth_txd1_x",
464							 "eth_txd2_rgmii",
465							 "eth_txd3_rgmii";
466						function = "eth";
467						bias-disable;
468					};
469				};
470
471				eth_rgmii_y_pins: eth-y-rgmii {
472					mux {
473						groups = "eth_mdio_y",
474							 "eth_mdc_y",
475							 "eth_rgmii_rx_clk_y",
476							 "eth_rx_dv_y",
477							 "eth_rxd0_y",
478							 "eth_rxd1_y",
479							 "eth_rxd2_rgmii",
480							 "eth_rxd3_rgmii",
481							 "eth_rgmii_tx_clk",
482							 "eth_txen_y",
483							 "eth_txd0_y",
484							 "eth_txd1_y",
485							 "eth_txd2_rgmii",
486							 "eth_txd3_rgmii";
487						function = "eth";
488						bias-disable;
489					};
490				};
491
492				eth_rmii_x_pins: eth-x-rmii {
493					mux {
494						groups = "eth_mdio_x",
495							 "eth_mdc_x",
496							 "eth_rgmii_rx_clk_x",
497							 "eth_rx_dv_x",
498							 "eth_rxd0_x",
499							 "eth_rxd1_x",
500							 "eth_txen_x",
501							 "eth_txd0_x",
502							 "eth_txd1_x";
503						function = "eth";
504						bias-disable;
505					};
506				};
507
508				eth_rmii_y_pins: eth-y-rmii {
509					mux {
510						groups = "eth_mdio_y",
511							 "eth_mdc_y",
512							 "eth_rgmii_rx_clk_y",
513							 "eth_rx_dv_y",
514							 "eth_rxd0_y",
515							 "eth_rxd1_y",
516							 "eth_txen_y",
517							 "eth_txd0_y",
518							 "eth_txd1_y";
519						function = "eth";
520						bias-disable;
521					};
522				};
523
524				mclk_b_pins: mclk_b {
525					mux {
526						groups = "mclk_b";
527						function = "mclk_b";
528						bias-disable;
529					};
530				};
531
532				mclk_c_pins: mclk_c {
533					mux {
534						groups = "mclk_c";
535						function = "mclk_c";
536						bias-disable;
537					};
538				};
539
540				pdm_dclk_a14_pins: pdm_dclk_a14 {
541					mux {
542						groups = "pdm_dclk_a14";
543						function = "pdm";
544						bias-disable;
545					};
546				};
547
548				pdm_dclk_a19_pins: pdm_dclk_a19 {
549					mux {
550						groups = "pdm_dclk_a19";
551						function = "pdm";
552						bias-disable;
553					};
554				};
555
556				pdm_din0_pins: pdm_din0 {
557					mux {
558						groups = "pdm_din0";
559						function = "pdm";
560						bias-disable;
561					};
562				};
563
564				pdm_din1_pins: pdm_din1 {
565					mux {
566						groups = "pdm_din1";
567						function = "pdm";
568						bias-disable;
569					};
570				};
571
572				pdm_din2_pins: pdm_din2 {
573					mux {
574						groups = "pdm_din2";
575						function = "pdm";
576						bias-disable;
577					};
578				};
579
580				pdm_din3_pins: pdm_din3 {
581					mux {
582						groups = "pdm_din3";
583						function = "pdm";
584						bias-disable;
585					};
586				};
587
588				pwm_a_a_pins: pwm_a_a {
589					mux {
590						groups = "pwm_a_a";
591						function = "pwm_a";
592						bias-disable;
593					};
594				};
595
596				pwm_a_x18_pins: pwm_a_x18 {
597					mux {
598						groups = "pwm_a_x18";
599						function = "pwm_a";
600						bias-disable;
601					};
602				};
603
604				pwm_a_x20_pins: pwm_a_x20 {
605					mux {
606						groups = "pwm_a_x20";
607						function = "pwm_a";
608						bias-disable;
609					};
610				};
611
612				pwm_a_z_pins: pwm_a_z {
613					mux {
614						groups = "pwm_a_z";
615						function = "pwm_a";
616						bias-disable;
617					};
618				};
619
620				pwm_b_a_pins: pwm_b_a {
621					mux {
622						groups = "pwm_b_a";
623						function = "pwm_b";
624						bias-disable;
625					};
626				};
627
628				pwm_b_x_pins: pwm_b_x {
629					mux {
630						groups = "pwm_b_x";
631						function = "pwm_b";
632						bias-disable;
633					};
634				};
635
636				pwm_b_z_pins: pwm_b_z {
637					mux {
638						groups = "pwm_b_z";
639						function = "pwm_b";
640						bias-disable;
641					};
642				};
643
644				pwm_c_a_pins: pwm_c_a {
645					mux {
646						groups = "pwm_c_a";
647						function = "pwm_c";
648						bias-disable;
649					};
650				};
651
652				pwm_c_x10_pins: pwm_c_x10 {
653					mux {
654						groups = "pwm_c_x10";
655						function = "pwm_c";
656						bias-disable;
657					};
658				};
659
660				pwm_c_x17_pins: pwm_c_x17 {
661					mux {
662						groups = "pwm_c_x17";
663						function = "pwm_c";
664						bias-disable;
665					};
666				};
667
668				pwm_d_x11_pins: pwm_d_x11 {
669					mux {
670						groups = "pwm_d_x11";
671						function = "pwm_d";
672						bias-disable;
673					};
674				};
675
676				pwm_d_x16_pins: pwm_d_x16 {
677					mux {
678						groups = "pwm_d_x16";
679						function = "pwm_d";
680						bias-disable;
681					};
682				};
683
684				sdio_pins: sdio {
685					mux-0 {
686						groups = "sdio_d0",
687							 "sdio_d1",
688							 "sdio_d2",
689							 "sdio_d3",
690							 "sdio_cmd";
691						function = "sdio";
692						bias-pull-up;
693					};
694
695					mux-1 {
696						groups = "sdio_clk";
697						function = "sdio";
698						bias-disable;
699					};
700				};
701
702				sdio_clk_gate_pins: sdio_clk_gate {
703					mux {
704						groups = "GPIOX_4";
705						function = "gpio_periphs";
706						bias-pull-down;
707					};
708				};
709
710				spdif_in_z_pins: spdif_in_z {
711					mux {
712						groups = "spdif_in_z";
713						function = "spdif_in";
714						bias-disable;
715					};
716				};
717
718				spdif_in_a1_pins: spdif_in_a1 {
719					mux {
720						groups = "spdif_in_a1";
721						function = "spdif_in";
722						bias-disable;
723					};
724				};
725
726				spdif_in_a7_pins: spdif_in_a7 {
727					mux {
728						groups = "spdif_in_a7";
729						function = "spdif_in";
730						bias-disable;
731					};
732				};
733
734				spdif_in_a19_pins: spdif_in_a19 {
735					mux {
736						groups = "spdif_in_a19";
737						function = "spdif_in";
738						bias-disable;
739					};
740				};
741
742				spdif_in_a20_pins: spdif_in_a20 {
743					mux {
744						groups = "spdif_in_a20";
745						function = "spdif_in";
746						bias-disable;
747					};
748				};
749
750				spdif_out_a1_pins: spdif_out_a1 {
751					mux {
752						groups = "spdif_out_a1";
753						function = "spdif_out";
754						bias-disable;
755					};
756				};
757
758				spdif_out_a11_pins: spdif_out_a11 {
759					mux {
760						groups = "spdif_out_a11";
761						function = "spdif_out";
762						bias-disable;
763					};
764				};
765
766				spdif_out_a19_pins: spdif_out_a19 {
767					mux {
768						groups = "spdif_out_a19";
769						function = "spdif_out";
770						bias-disable;
771					};
772				};
773
774				spdif_out_a20_pins: spdif_out_a20 {
775					mux {
776						groups = "spdif_out_a20";
777						function = "spdif_out";
778						bias-disable;
779					};
780				};
781
782				spdif_out_z_pins: spdif_out_z {
783					mux {
784						groups = "spdif_out_z";
785						function = "spdif_out";
786						bias-disable;
787					};
788				};
789
790				spi0_pins: spi0 {
791					mux {
792						groups = "spi0_miso",
793							 "spi0_mosi",
794							 "spi0_clk";
795						function = "spi0";
796						bias-disable;
797					};
798				};
799
800				spi0_ss0_pins: spi0_ss0 {
801					mux {
802						groups = "spi0_ss0";
803						function = "spi0";
804						bias-disable;
805					};
806				};
807
808				spi0_ss1_pins: spi0_ss1 {
809					mux {
810						groups = "spi0_ss1";
811						function = "spi0";
812						bias-disable;
813					};
814				};
815
816				spi0_ss2_pins: spi0_ss2 {
817					mux {
818						groups = "spi0_ss2";
819						function = "spi0";
820						bias-disable;
821					};
822				};
823
824				spi1_a_pins: spi1_a {
825					mux {
826						groups = "spi1_miso_a",
827							 "spi1_mosi_a",
828							 "spi1_clk_a";
829						function = "spi1";
830						bias-disable;
831					};
832				};
833
834				spi1_ss0_a_pins: spi1_ss0_a {
835					mux {
836						groups = "spi1_ss0_a";
837						function = "spi1";
838						bias-disable;
839					};
840				};
841
842				spi1_ss1_pins: spi1_ss1 {
843					mux {
844						groups = "spi1_ss1";
845						function = "spi1";
846						bias-disable;
847					};
848				};
849
850				spi1_x_pins: spi1_x {
851					mux {
852						groups = "spi1_miso_x",
853							 "spi1_mosi_x",
854							 "spi1_clk_x";
855						function = "spi1";
856						bias-disable;
857					};
858				};
859
860				spi1_ss0_x_pins: spi1_ss0_x {
861					mux {
862						groups = "spi1_ss0_x";
863						function = "spi1";
864						bias-disable;
865					};
866				};
867
868				tdma_din0_pins: tdma_din0 {
869					mux {
870						groups = "tdma_din0";
871						function = "tdma";
872						bias-disable;
873					};
874				};
875
876				tdma_dout0_x14_pins: tdma_dout0_x14 {
877					mux {
878						groups = "tdma_dout0_x14";
879						function = "tdma";
880						bias-disable;
881					};
882				};
883
884				tdma_dout0_x15_pins: tdma_dout0_x15 {
885					mux {
886						groups = "tdma_dout0_x15";
887						function = "tdma";
888						bias-disable;
889					};
890				};
891
892				tdma_dout1_pins: tdma_dout1 {
893					mux {
894						groups = "tdma_dout1";
895						function = "tdma";
896						bias-disable;
897					};
898				};
899
900				tdma_din1_pins: tdma_din1 {
901					mux {
902						groups = "tdma_din1";
903						function = "tdma";
904						bias-disable;
905					};
906				};
907
908				tdma_fs_pins: tdma_fs {
909					mux {
910						groups = "tdma_fs";
911						function = "tdma";
912						bias-disable;
913					};
914				};
915
916				tdma_fs_slv_pins: tdma_fs_slv {
917					mux {
918						groups = "tdma_fs_slv";
919						function = "tdma";
920						bias-disable;
921					};
922				};
923
924				tdma_sclk_pins: tdma_sclk {
925					mux {
926						groups = "tdma_sclk";
927						function = "tdma";
928						bias-disable;
929					};
930				};
931
932				tdma_sclk_slv_pins: tdma_sclk_slv {
933					mux {
934						groups = "tdma_sclk_slv";
935						function = "tdma";
936						bias-disable;
937					};
938				};
939
940				tdmb_din0_pins: tdmb_din0 {
941					mux {
942						groups = "tdmb_din0";
943						function = "tdmb";
944						bias-disable;
945					};
946				};
947
948				tdmb_din1_pins: tdmb_din1 {
949					mux {
950						groups = "tdmb_din1";
951						function = "tdmb";
952						bias-disable;
953					};
954				};
955
956				tdmb_din2_pins: tdmb_din2 {
957					mux {
958						groups = "tdmb_din2";
959						function = "tdmb";
960						bias-disable;
961					};
962				};
963
964				tdmb_din3_pins: tdmb_din3 {
965					mux {
966						groups = "tdmb_din3";
967						function = "tdmb";
968						bias-disable;
969					};
970				};
971
972				tdmb_dout0_pins: tdmb_dout0 {
973					mux {
974						groups = "tdmb_dout0";
975						function = "tdmb";
976						bias-disable;
977					};
978				};
979
980				tdmb_dout1_pins: tdmb_dout1 {
981					mux {
982						groups = "tdmb_dout1";
983						function = "tdmb";
984						bias-disable;
985					};
986				};
987
988				tdmb_dout2_pins: tdmb_dout2 {
989					mux {
990						groups = "tdmb_dout2";
991						function = "tdmb";
992						bias-disable;
993					};
994				};
995
996				tdmb_dout3_pins: tdmb_dout3 {
997					mux {
998						groups = "tdmb_dout3";
999						function = "tdmb";
1000						bias-disable;
1001					};
1002				};
1003
1004				tdmb_fs_pins: tdmb_fs {
1005					mux {
1006						groups = "tdmb_fs";
1007						function = "tdmb";
1008						bias-disable;
1009					};
1010				};
1011
1012				tdmb_fs_slv_pins: tdmb_fs_slv {
1013					mux {
1014						groups = "tdmb_fs_slv";
1015						function = "tdmb";
1016						bias-disable;
1017					};
1018				};
1019
1020				tdmb_sclk_pins: tdmb_sclk {
1021					mux {
1022						groups = "tdmb_sclk";
1023						function = "tdmb";
1024						bias-disable;
1025					};
1026				};
1027
1028				tdmb_sclk_slv_pins: tdmb_sclk_slv {
1029					mux {
1030						groups = "tdmb_sclk_slv";
1031						function = "tdmb";
1032						bias-disable;
1033					};
1034				};
1035
1036				tdmc_fs_pins: tdmc_fs {
1037					mux {
1038						groups = "tdmc_fs";
1039						function = "tdmc";
1040						bias-disable;
1041					};
1042				};
1043
1044				tdmc_fs_slv_pins: tdmc_fs_slv {
1045					mux {
1046						groups = "tdmc_fs_slv";
1047						function = "tdmc";
1048						bias-disable;
1049					};
1050				};
1051
1052				tdmc_sclk_pins: tdmc_sclk {
1053					mux {
1054						groups = "tdmc_sclk";
1055						function = "tdmc";
1056						bias-disable;
1057					};
1058				};
1059
1060				tdmc_sclk_slv_pins: tdmc_sclk_slv {
1061					mux {
1062						groups = "tdmc_sclk_slv";
1063						function = "tdmc";
1064						bias-disable;
1065					};
1066				};
1067
1068				tdmc_din0_pins: tdmc_din0 {
1069					mux {
1070						groups = "tdmc_din0";
1071						function = "tdmc";
1072						bias-disable;
1073					};
1074				};
1075
1076				tdmc_din1_pins: tdmc_din1 {
1077					mux {
1078						groups = "tdmc_din1";
1079						function = "tdmc";
1080						bias-disable;
1081					};
1082				};
1083
1084				tdmc_din2_pins: tdmc_din2 {
1085					mux {
1086						groups = "tdmc_din2";
1087						function = "tdmc";
1088						bias-disable;
1089					};
1090				};
1091
1092				tdmc_din3_pins: tdmc_din3 {
1093					mux {
1094						groups = "tdmc_din3";
1095						function = "tdmc";
1096						bias-disable;
1097					};
1098				};
1099
1100				tdmc_dout0_pins: tdmc_dout0 {
1101					mux {
1102						groups = "tdmc_dout0";
1103						function = "tdmc";
1104						bias-disable;
1105					};
1106				};
1107
1108				tdmc_dout1_pins: tdmc_dout1 {
1109					mux {
1110						groups = "tdmc_dout1";
1111						function = "tdmc";
1112						bias-disable;
1113					};
1114				};
1115
1116				tdmc_dout2_pins: tdmc_dout2 {
1117					mux {
1118						groups = "tdmc_dout2";
1119						function = "tdmc";
1120						bias-disable;
1121					};
1122				};
1123
1124				tdmc_dout3_pins: tdmc_dout3 {
1125					mux {
1126						groups = "tdmc_dout3";
1127						function = "tdmc";
1128						bias-disable;
1129					};
1130				};
1131
1132				uart_a_pins: uart_a {
1133					mux {
1134						groups = "uart_tx_a",
1135							 "uart_rx_a";
1136						function = "uart_a";
1137						bias-disable;
1138					};
1139				};
1140
1141				uart_a_cts_rts_pins: uart_a_cts_rts {
1142					mux {
1143						groups = "uart_cts_a",
1144							 "uart_rts_a";
1145						function = "uart_a";
1146						bias-disable;
1147					};
1148				};
1149
1150				uart_b_x_pins: uart_b_x {
1151					mux {
1152						groups = "uart_tx_b_x",
1153							 "uart_rx_b_x";
1154						function = "uart_b";
1155						bias-disable;
1156					};
1157				};
1158
1159				uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
1160					mux {
1161						groups = "uart_cts_b_x",
1162							 "uart_rts_b_x";
1163						function = "uart_b";
1164						bias-disable;
1165					};
1166				};
1167
1168				uart_b_z_pins: uart_b_z {
1169					mux {
1170						groups = "uart_tx_b_z",
1171							 "uart_rx_b_z";
1172						function = "uart_b";
1173						bias-disable;
1174					};
1175				};
1176
1177				uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
1178					mux {
1179						groups = "uart_cts_b_z",
1180							 "uart_rts_b_z";
1181						function = "uart_b";
1182						bias-disable;
1183					};
1184				};
1185
1186				uart_ao_b_z_pins: uart_ao_b_z {
1187					mux {
1188						groups = "uart_ao_tx_b_z",
1189							 "uart_ao_rx_b_z";
1190						function = "uart_ao_b_z";
1191						bias-disable;
1192					};
1193				};
1194
1195				uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
1196					mux {
1197						groups = "uart_ao_cts_b_z",
1198							 "uart_ao_rts_b_z";
1199						function = "uart_ao_b_z";
1200						bias-disable;
1201					};
1202				};
1203			};
1204		};
1205
1206		hiubus: bus@ff63c000 {
1207			compatible = "simple-bus";
1208			reg = <0x0 0xff63c000 0x0 0x1c00>;
1209			#address-cells = <2>;
1210			#size-cells = <2>;
1211			ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
1212
1213			sysctrl: system-controller@0 {
1214				compatible = "amlogic,meson-axg-hhi-sysctrl",
1215					     "simple-mfd", "syscon";
1216				reg = <0 0 0 0x400>;
1217
1218				clkc: clock-controller {
1219					compatible = "amlogic,axg-clkc";
1220					#clock-cells = <1>;
1221					clocks = <&xtal>;
1222					clock-names = "xtal";
1223				};
1224
1225				pwrc: power-controller {
1226					compatible = "amlogic,meson-axg-pwrc";
1227					#power-domain-cells = <1>;
1228					amlogic,ao-sysctrl = <&sysctrl_AO>;
1229					resets = <&reset RESET_VIU>,
1230						 <&reset RESET_VENC>,
1231						 <&reset RESET_VCBUS>,
1232						 <&reset RESET_VENCL>,
1233						 <&reset RESET_VID_LOCK>;
1234					reset-names = "viu", "venc", "vcbus",
1235						      "vencl", "vid_lock";
1236					clocks = <&clkc CLKID_VPU>,
1237						 <&clkc CLKID_VAPB>;
1238					clock-names = "vpu", "vapb";
1239					/*
1240					 * VPU clocking is provided by two identical clock paths
1241					 * VPU_0 and VPU_1 muxed to a single clock by a glitch
1242					 * free mux to safely change frequency while running.
1243					 * Same for VAPB but with a final gate after the glitch free mux.
1244					 */
1245					assigned-clocks = <&clkc CLKID_VPU_0_SEL>,
1246							  <&clkc CLKID_VPU_0>,
1247							  <&clkc CLKID_VPU>, /* Glitch free mux */
1248							  <&clkc CLKID_VAPB_0_SEL>,
1249							  <&clkc CLKID_VAPB_0>,
1250							  <&clkc CLKID_VAPB_SEL>; /* Glitch free mux */
1251					assigned-clock-parents = <&clkc CLKID_FCLK_DIV4>,
1252								 <0>, /* Do Nothing */
1253								 <&clkc CLKID_VPU_0>,
1254								 <&clkc CLKID_FCLK_DIV4>,
1255								 <0>, /* Do Nothing */
1256								 <&clkc CLKID_VAPB_0>;
1257					assigned-clock-rates = <0>, /* Do Nothing */
1258							       <250000000>,
1259							       <0>, /* Do Nothing */
1260							       <0>, /* Do Nothing */
1261							       <250000000>,
1262							       <0>; /* Do Nothing */
1263				};
1264
1265				mipi_pcie_analog_dphy: phy {
1266					compatible = "amlogic,axg-mipi-pcie-analog-phy";
1267					#phy-cells = <0>;
1268					status = "disabled";
1269				};
1270			};
1271		};
1272
1273		mailbox: mailbox@ff63c404 {
1274			compatible = "amlogic,meson-gxbb-mhu";
1275			reg = <0 0xff63c404 0 0x4c>;
1276			interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
1277				     <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
1278				     <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
1279			#mbox-cells = <1>;
1280		};
1281
1282		mipi_dphy: phy@ff640000 {
1283			compatible = "amlogic,axg-mipi-dphy";
1284			reg = <0x0 0xff640000 0x0 0x100>;
1285			clocks = <&clkc CLKID_MIPI_DSI_PHY>;
1286			clock-names = "pclk";
1287			resets = <&reset RESET_MIPI_PHY>;
1288			reset-names = "phy";
1289			phys = <&mipi_pcie_analog_dphy>;
1290			phy-names = "analog";
1291			#phy-cells = <0>;
1292			status = "disabled";
1293		};
1294
1295		audio: bus@ff642000 {
1296			compatible = "simple-bus";
1297			reg = <0x0 0xff642000 0x0 0x2000>;
1298			#address-cells = <2>;
1299			#size-cells = <2>;
1300			ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>;
1301
1302			clkc_audio: clock-controller@0 {
1303				compatible = "amlogic,axg-audio-clkc";
1304				reg = <0x0 0x0 0x0 0xb4>;
1305				#clock-cells = <1>;
1306
1307				clocks = <&clkc CLKID_AUDIO>,
1308					 <&clkc CLKID_MPLL0>,
1309					 <&clkc CLKID_MPLL1>,
1310					 <&clkc CLKID_MPLL2>,
1311					 <&clkc CLKID_MPLL3>,
1312					 <&clkc CLKID_HIFI_PLL>,
1313					 <&clkc CLKID_FCLK_DIV3>,
1314					 <&clkc CLKID_FCLK_DIV4>,
1315					 <&clkc CLKID_GP0_PLL>;
1316				clock-names = "pclk",
1317					      "mst_in0",
1318					      "mst_in1",
1319					      "mst_in2",
1320					      "mst_in3",
1321					      "mst_in4",
1322					      "mst_in5",
1323					      "mst_in6",
1324					      "mst_in7";
1325
1326				resets = <&reset RESET_AUDIO>;
1327			};
1328
1329			toddr_a: audio-controller@100 {
1330				compatible = "amlogic,axg-toddr";
1331				reg = <0x0 0x100 0x0 0x2c>;
1332				#sound-dai-cells = <0>;
1333				sound-name-prefix = "TODDR_A";
1334				interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
1335				clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
1336				resets = <&arb AXG_ARB_TODDR_A>;
1337				amlogic,fifo-depth = <512>;
1338				status = "disabled";
1339			};
1340
1341			toddr_b: audio-controller@140 {
1342				compatible = "amlogic,axg-toddr";
1343				reg = <0x0 0x140 0x0 0x2c>;
1344				#sound-dai-cells = <0>;
1345				sound-name-prefix = "TODDR_B";
1346				interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
1347				clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
1348				resets = <&arb AXG_ARB_TODDR_B>;
1349				amlogic,fifo-depth = <256>;
1350				status = "disabled";
1351			};
1352
1353			toddr_c: audio-controller@180 {
1354				compatible = "amlogic,axg-toddr";
1355				reg = <0x0 0x180 0x0 0x2c>;
1356				#sound-dai-cells = <0>;
1357				sound-name-prefix = "TODDR_C";
1358				interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
1359				clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
1360				resets = <&arb AXG_ARB_TODDR_C>;
1361				amlogic,fifo-depth = <256>;
1362				status = "disabled";
1363			};
1364
1365			frddr_a: audio-controller@1c0 {
1366				compatible = "amlogic,axg-frddr";
1367				reg = <0x0 0x1c0 0x0 0x2c>;
1368				#sound-dai-cells = <0>;
1369				sound-name-prefix = "FRDDR_A";
1370				interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
1371				clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
1372				resets = <&arb AXG_ARB_FRDDR_A>;
1373				amlogic,fifo-depth = <512>;
1374				status = "disabled";
1375			};
1376
1377			frddr_b: audio-controller@200 {
1378				compatible = "amlogic,axg-frddr";
1379				reg = <0x0 0x200 0x0 0x2c>;
1380				#sound-dai-cells = <0>;
1381				sound-name-prefix = "FRDDR_B";
1382				interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
1383				clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
1384				resets = <&arb AXG_ARB_FRDDR_B>;
1385				amlogic,fifo-depth = <256>;
1386				status = "disabled";
1387			};
1388
1389			frddr_c: audio-controller@240 {
1390				compatible = "amlogic,axg-frddr";
1391				reg = <0x0 0x240 0x0 0x2c>;
1392				#sound-dai-cells = <0>;
1393				sound-name-prefix = "FRDDR_C";
1394				interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
1395				clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
1396				resets = <&arb AXG_ARB_FRDDR_C>;
1397				amlogic,fifo-depth = <256>;
1398				status = "disabled";
1399			};
1400
1401			arb: reset-controller@280 {
1402				compatible = "amlogic,meson-axg-audio-arb";
1403				reg = <0x0 0x280 0x0 0x4>;
1404				#reset-cells = <1>;
1405				clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
1406			};
1407
1408			tdmin_a: audio-controller@300 {
1409				compatible = "amlogic,axg-tdmin";
1410				reg = <0x0 0x300 0x0 0x40>;
1411				sound-name-prefix = "TDMIN_A";
1412				clocks = <&clkc_audio AUD_CLKID_TDMIN_A>,
1413					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>,
1414					 <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>,
1415					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>,
1416					 <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>;
1417				clock-names = "pclk", "sclk", "sclk_sel",
1418					      "lrclk", "lrclk_sel";
1419				status = "disabled";
1420			};
1421
1422			tdmin_b: audio-controller@340 {
1423				compatible = "amlogic,axg-tdmin";
1424				reg = <0x0 0x340 0x0 0x40>;
1425				sound-name-prefix = "TDMIN_B";
1426				clocks = <&clkc_audio AUD_CLKID_TDMIN_B>,
1427					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>,
1428					 <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>,
1429					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>,
1430					 <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>;
1431				clock-names = "pclk", "sclk", "sclk_sel",
1432					      "lrclk", "lrclk_sel";
1433				status = "disabled";
1434			};
1435
1436			tdmin_c: audio-controller@380 {
1437				compatible = "amlogic,axg-tdmin";
1438				reg = <0x0 0x380 0x0 0x40>;
1439				sound-name-prefix = "TDMIN_C";
1440				clocks = <&clkc_audio AUD_CLKID_TDMIN_C>,
1441					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>,
1442					 <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>,
1443					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>,
1444					 <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>;
1445				clock-names = "pclk", "sclk", "sclk_sel",
1446					      "lrclk", "lrclk_sel";
1447				status = "disabled";
1448			};
1449
1450			tdmin_lb: audio-controller@3c0 {
1451				compatible = "amlogic,axg-tdmin";
1452				reg = <0x0 0x3c0 0x0 0x40>;
1453				sound-name-prefix = "TDMIN_LB";
1454				clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>,
1455					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>,
1456					 <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>,
1457					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>,
1458					 <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>;
1459				clock-names = "pclk", "sclk", "sclk_sel",
1460					      "lrclk", "lrclk_sel";
1461				status = "disabled";
1462			};
1463
1464			spdifin: audio-controller@400 {
1465				compatible = "amlogic,axg-spdifin";
1466				reg = <0x0 0x400 0x0 0x30>;
1467				#sound-dai-cells = <0>;
1468				sound-name-prefix = "SPDIFIN";
1469				interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
1470				clocks = <&clkc_audio AUD_CLKID_SPDIFIN>,
1471					 <&clkc_audio AUD_CLKID_SPDIFIN_CLK>;
1472				clock-names = "pclk", "refclk";
1473				status = "disabled";
1474			};
1475
1476			spdifout: audio-controller@480 {
1477				compatible = "amlogic,axg-spdifout";
1478				reg = <0x0 0x480 0x0 0x50>;
1479				#sound-dai-cells = <0>;
1480				sound-name-prefix = "SPDIFOUT";
1481				clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
1482					 <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
1483				clock-names = "pclk", "mclk";
1484				status = "disabled";
1485			};
1486
1487			tdmout_a: audio-controller@500 {
1488				compatible = "amlogic,axg-tdmout";
1489				reg = <0x0 0x500 0x0 0x40>;
1490				sound-name-prefix = "TDMOUT_A";
1491				clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>,
1492					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>,
1493					 <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>,
1494					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>,
1495					 <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>;
1496				clock-names = "pclk", "sclk", "sclk_sel",
1497					      "lrclk", "lrclk_sel";
1498				status = "disabled";
1499			};
1500
1501			tdmout_b: audio-controller@540 {
1502				compatible = "amlogic,axg-tdmout";
1503				reg = <0x0 0x540 0x0 0x40>;
1504				sound-name-prefix = "TDMOUT_B";
1505				clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>,
1506					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>,
1507					 <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>,
1508					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>,
1509					 <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>;
1510				clock-names = "pclk", "sclk", "sclk_sel",
1511					      "lrclk", "lrclk_sel";
1512				status = "disabled";
1513			};
1514
1515			tdmout_c: audio-controller@580 {
1516				compatible = "amlogic,axg-tdmout";
1517				reg = <0x0 0x580 0x0 0x40>;
1518				sound-name-prefix = "TDMOUT_C";
1519				clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>,
1520					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>,
1521					 <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>,
1522					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>,
1523					 <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>;
1524				clock-names = "pclk", "sclk", "sclk_sel",
1525					      "lrclk", "lrclk_sel";
1526				status = "disabled";
1527			};
1528		};
1529
1530		aobus: bus@ff800000 {
1531			compatible = "simple-bus";
1532			reg = <0x0 0xff800000 0x0 0x100000>;
1533			#address-cells = <2>;
1534			#size-cells = <2>;
1535			ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
1536
1537			sysctrl_AO: sys-ctrl@0 {
1538				compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon";
1539				reg = <0x0 0x0 0x0 0x100>;
1540
1541				clkc_AO: clock-controller {
1542					compatible = "amlogic,meson-axg-aoclkc";
1543					#clock-cells = <1>;
1544					#reset-cells = <1>;
1545					clocks = <&xtal>, <&clkc CLKID_CLK81>;
1546					clock-names = "xtal", "mpeg-clk";
1547				};
1548			};
1549
1550			pinctrl_aobus: pinctrl@14 {
1551				compatible = "amlogic,meson-axg-aobus-pinctrl";
1552				#address-cells = <2>;
1553				#size-cells = <2>;
1554				ranges;
1555
1556				gpio_ao: bank@14 {
1557					reg = <0x0 0x00014 0x0 0x8>,
1558					      <0x0 0x0002c 0x0 0x4>,
1559					      <0x0 0x00024 0x0 0x8>;
1560					reg-names = "mux", "pull", "gpio";
1561					gpio-controller;
1562					#gpio-cells = <2>;
1563					gpio-ranges = <&pinctrl_aobus 0 0 15>;
1564				};
1565
1566				i2c_ao_sck_4_pins: i2c_ao_sck_4 {
1567					mux {
1568						groups = "i2c_ao_sck_4";
1569						function = "i2c_ao";
1570						bias-disable;
1571					};
1572				};
1573
1574				i2c_ao_sck_8_pins: i2c_ao_sck_8 {
1575					mux {
1576						groups = "i2c_ao_sck_8";
1577						function = "i2c_ao";
1578						bias-disable;
1579					};
1580				};
1581
1582				i2c_ao_sck_10_pins: i2c_ao_sck_10 {
1583					mux {
1584						groups = "i2c_ao_sck_10";
1585						function = "i2c_ao";
1586						bias-disable;
1587					};
1588				};
1589
1590				i2c_ao_sda_5_pins: i2c_ao_sda_5 {
1591					mux {
1592						groups = "i2c_ao_sda_5";
1593						function = "i2c_ao";
1594						bias-disable;
1595					};
1596				};
1597
1598				i2c_ao_sda_9_pins: i2c_ao_sda_9 {
1599					mux {
1600						groups = "i2c_ao_sda_9";
1601						function = "i2c_ao";
1602						bias-disable;
1603					};
1604				};
1605
1606				i2c_ao_sda_11_pins: i2c_ao_sda_11 {
1607					mux {
1608						groups = "i2c_ao_sda_11";
1609						function = "i2c_ao";
1610						bias-disable;
1611					};
1612				};
1613
1614				remote_input_ao_pins: remote_input_ao {
1615					mux {
1616						groups = "remote_input_ao";
1617						function = "remote_input_ao";
1618						bias-disable;
1619					};
1620				};
1621
1622				uart_ao_a_pins: uart_ao_a {
1623					mux {
1624						groups = "uart_ao_tx_a",
1625							 "uart_ao_rx_a";
1626						function = "uart_ao_a";
1627						bias-disable;
1628					};
1629				};
1630
1631				uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
1632					mux {
1633						groups = "uart_ao_cts_a",
1634							 "uart_ao_rts_a";
1635						function = "uart_ao_a";
1636						bias-disable;
1637					};
1638				};
1639
1640				uart_ao_b_pins: uart_ao_b {
1641					mux {
1642						groups = "uart_ao_tx_b",
1643							 "uart_ao_rx_b";
1644						function = "uart_ao_b";
1645						bias-disable;
1646					};
1647				};
1648
1649				uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
1650					mux {
1651						groups = "uart_ao_cts_b",
1652							 "uart_ao_rts_b";
1653						function = "uart_ao_b";
1654						bias-disable;
1655					};
1656				};
1657			};
1658
1659			sec_AO: ao-secure@140 {
1660				compatible = "amlogic,meson-gx-ao-secure", "syscon";
1661				reg = <0x0 0x140 0x0 0x140>;
1662				amlogic,has-chip-id;
1663			};
1664
1665			pwm_AO_cd: pwm@2000 {
1666				compatible = "amlogic,meson-axg-ao-pwm";
1667				reg = <0x0 0x02000  0x0 0x20>;
1668				#pwm-cells = <3>;
1669				status = "disabled";
1670			};
1671
1672			uart_AO: serial@3000 {
1673				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1674				reg = <0x0 0x3000 0x0 0x18>;
1675				interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
1676				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>;
1677				clock-names = "xtal", "pclk", "baud";
1678				status = "disabled";
1679			};
1680
1681			uart_AO_B: serial@4000 {
1682				compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
1683				reg = <0x0 0x4000 0x0 0x18>;
1684				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
1685				clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>;
1686				clock-names = "xtal", "pclk", "baud";
1687				status = "disabled";
1688			};
1689
1690			i2c_AO: i2c@5000 {
1691				compatible = "amlogic,meson-axg-i2c";
1692				reg = <0x0 0x05000 0x0 0x20>;
1693				interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>;
1694				clocks = <&clkc CLKID_AO_I2C>;
1695				#address-cells = <1>;
1696				#size-cells = <0>;
1697				status = "disabled";
1698			};
1699
1700			pwm_AO_ab: pwm@7000 {
1701				compatible = "amlogic,meson-axg-ao-pwm";
1702				reg = <0x0 0x07000 0x0 0x20>;
1703				#pwm-cells = <3>;
1704				status = "disabled";
1705			};
1706
1707			ir: ir@8000 {
1708				compatible = "amlogic,meson-gxbb-ir";
1709				reg = <0x0 0x8000 0x0 0x20>;
1710				interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
1711				status = "disabled";
1712			};
1713
1714			saradc: adc@9000 {
1715				compatible = "amlogic,meson-axg-saradc",
1716					"amlogic,meson-saradc";
1717				reg = <0x0 0x9000 0x0 0x38>;
1718				#io-channel-cells = <1>;
1719				interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>;
1720				clocks = <&xtal>,
1721					 <&clkc_AO CLKID_AO_SAR_ADC>,
1722					 <&clkc_AO CLKID_AO_SAR_ADC_CLK>,
1723					 <&clkc_AO CLKID_AO_SAR_ADC_SEL>;
1724				clock-names = "clkin", "core", "adc_clk", "adc_sel";
1725				status = "disabled";
1726			};
1727		};
1728
1729		ge2d: ge2d@ff940000 {
1730			compatible = "amlogic,axg-ge2d";
1731			reg = <0x0 0xff940000 0x0 0x10000>;
1732			interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>;
1733			clocks = <&clkc CLKID_VAPB>;
1734			resets = <&reset RESET_GE2D>;
1735		};
1736
1737		gic: interrupt-controller@ffc01000 {
1738			compatible = "arm,gic-400";
1739			reg = <0x0 0xffc01000 0 0x1000>,
1740			      <0x0 0xffc02000 0 0x2000>,
1741			      <0x0 0xffc04000 0 0x2000>,
1742			      <0x0 0xffc06000 0 0x2000>;
1743			interrupt-controller;
1744			interrupts = <GIC_PPI 9
1745				(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1746			#interrupt-cells = <3>;
1747			#address-cells = <0>;
1748		};
1749
1750		cbus: bus@ffd00000 {
1751			compatible = "simple-bus";
1752			reg = <0x0 0xffd00000 0x0 0x25000>;
1753			#address-cells = <2>;
1754			#size-cells = <2>;
1755			ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
1756
1757			reset: reset-controller@1004 {
1758				compatible = "amlogic,meson-axg-reset";
1759				reg = <0x0 0x01004 0x0 0x9c>;
1760				#reset-cells = <1>;
1761			};
1762
1763			gpio_intc: interrupt-controller@f080 {
1764				compatible = "amlogic,meson-axg-gpio-intc",
1765					     "amlogic,meson-gpio-intc";
1766				reg = <0x0 0xf080 0x0 0x10>;
1767				interrupt-controller;
1768				#interrupt-cells = <2>;
1769				amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
1770			};
1771
1772			watchdog@f0d0 {
1773				compatible = "amlogic,meson-gxbb-wdt";
1774				reg = <0x0 0xf0d0 0x0 0x10>;
1775				clocks = <&xtal>;
1776			};
1777
1778			pwm_ab: pwm@1b000 {
1779				compatible = "amlogic,meson-axg-ee-pwm";
1780				reg = <0x0 0x1b000 0x0 0x20>;
1781				#pwm-cells = <3>;
1782				status = "disabled";
1783			};
1784
1785			pwm_cd: pwm@1a000 {
1786				compatible = "amlogic,meson-axg-ee-pwm";
1787				reg = <0x0 0x1a000 0x0 0x20>;
1788				#pwm-cells = <3>;
1789				status = "disabled";
1790			};
1791
1792			spicc0: spi@13000 {
1793				compatible = "amlogic,meson-axg-spicc";
1794				reg = <0x0 0x13000 0x0 0x3c>;
1795				interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
1796				clocks = <&clkc CLKID_SPICC0>;
1797				clock-names = "core";
1798				#address-cells = <1>;
1799				#size-cells = <0>;
1800				status = "disabled";
1801			};
1802
1803			spicc1: spi@15000 {
1804				compatible = "amlogic,meson-axg-spicc";
1805				reg = <0x0 0x15000 0x0 0x3c>;
1806				interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1807				clocks = <&clkc CLKID_SPICC1>;
1808				clock-names = "core";
1809				#address-cells = <1>;
1810				#size-cells = <0>;
1811				status = "disabled";
1812			};
1813
1814			clk_msr: clock-measure@18000 {
1815				compatible = "amlogic,meson-axg-clk-measure";
1816				reg = <0x0 0x18000 0x0 0x10>;
1817			};
1818
1819			i2c3: i2c@1c000 {
1820				compatible = "amlogic,meson-axg-i2c";
1821				reg = <0x0 0x1c000 0x0 0x20>;
1822				interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
1823				clocks = <&clkc CLKID_I2C>;
1824				#address-cells = <1>;
1825				#size-cells = <0>;
1826				status = "disabled";
1827			};
1828
1829			i2c2: i2c@1d000 {
1830				compatible = "amlogic,meson-axg-i2c";
1831				reg = <0x0 0x1d000 0x0 0x20>;
1832				interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>;
1833				clocks = <&clkc CLKID_I2C>;
1834				#address-cells = <1>;
1835				#size-cells = <0>;
1836				status = "disabled";
1837			};
1838
1839			i2c1: i2c@1e000 {
1840				compatible = "amlogic,meson-axg-i2c";
1841				reg = <0x0 0x1e000 0x0 0x20>;
1842				interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>;
1843				clocks = <&clkc CLKID_I2C>;
1844				#address-cells = <1>;
1845				#size-cells = <0>;
1846				status = "disabled";
1847			};
1848
1849			i2c0: i2c@1f000 {
1850				compatible = "amlogic,meson-axg-i2c";
1851				reg = <0x0 0x1f000 0x0 0x20>;
1852				interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>;
1853				clocks = <&clkc CLKID_I2C>;
1854				#address-cells = <1>;
1855				#size-cells = <0>;
1856				status = "disabled";
1857			};
1858
1859			uart_B: serial@23000 {
1860				compatible = "amlogic,meson-gx-uart";
1861				reg = <0x0 0x23000 0x0 0x18>;
1862				interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
1863				status = "disabled";
1864				clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
1865				clock-names = "xtal", "pclk", "baud";
1866			};
1867
1868			uart_A: serial@24000 {
1869				compatible = "amlogic,meson-gx-uart";
1870				reg = <0x0 0x24000 0x0 0x18>;
1871				interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
1872				status = "disabled";
1873				clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
1874				clock-names = "xtal", "pclk", "baud";
1875				fifo-size = <128>;
1876			};
1877		};
1878
1879		apb: bus@ffe00000 {
1880			compatible = "simple-bus";
1881			reg = <0x0 0xffe00000 0x0 0x200000>;
1882			#address-cells = <2>;
1883			#size-cells = <2>;
1884			ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>;
1885
1886			sd_emmc_b: sd@5000 {
1887				compatible = "amlogic,meson-axg-mmc";
1888				reg = <0x0 0x5000 0x0 0x800>;
1889				interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>;
1890				status = "disabled";
1891				clocks = <&clkc CLKID_SD_EMMC_B>,
1892					<&clkc CLKID_SD_EMMC_B_CLK0>,
1893					<&clkc CLKID_FCLK_DIV2>;
1894				clock-names = "core", "clkin0", "clkin1";
1895				resets = <&reset RESET_SD_EMMC_B>;
1896			};
1897
1898			sd_emmc_c: mmc@7000 {
1899				compatible = "amlogic,meson-axg-mmc";
1900				reg = <0x0 0x7000 0x0 0x800>;
1901				interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>;
1902				status = "disabled";
1903				clocks = <&clkc CLKID_SD_EMMC_C>,
1904					<&clkc CLKID_SD_EMMC_C_CLK0>,
1905					<&clkc CLKID_FCLK_DIV2>;
1906				clock-names = "core", "clkin0", "clkin1";
1907				resets = <&reset RESET_SD_EMMC_C>;
1908			};
1909
1910			usb2_phy1: phy@9020 {
1911				compatible = "amlogic,meson-gxl-usb2-phy";
1912				#phy-cells = <0>;
1913				reg = <0x0 0x9020 0x0 0x20>;
1914				clocks = <&clkc CLKID_USB>;
1915				clock-names = "phy";
1916				resets = <&reset RESET_USB_OTG>;
1917				reset-names = "phy";
1918			};
1919		};
1920
1921		sram: sram@fffc0000 {
1922			compatible = "mmio-sram";
1923			reg = <0x0 0xfffc0000 0x0 0x20000>;
1924			#address-cells = <1>;
1925			#size-cells = <1>;
1926			ranges = <0 0x0 0xfffc0000 0x20000>;
1927
1928			cpu_scp_lpri: scp-sram@13000 {
1929				compatible = "amlogic,meson-axg-scp-shmem";
1930				reg = <0x13000 0x400>;
1931			};
1932
1933			cpu_scp_hpri: scp-sram@13400 {
1934				compatible = "amlogic,meson-axg-scp-shmem";
1935				reg = <0x13400 0x400>;
1936			};
1937		};
1938	};
1939
1940	timer {
1941		compatible = "arm,armv8-timer";
1942		interrupts = <GIC_PPI 13
1943			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1944			     <GIC_PPI 14
1945			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1946			     <GIC_PPI 11
1947			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
1948			     <GIC_PPI 10
1949			(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
1950	};
1951
1952	xtal: xtal-clk {
1953		compatible = "fixed-clock";
1954		clock-frequency = <24000000>;
1955		clock-output-names = "xtal";
1956		#clock-cells = <0>;
1957	};
1958};
1959