1114abfe1SNeil Armstrong// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 29d59b708SYixun Lan/* 39d59b708SYixun Lan * Copyright (c) 2017 Amlogic, Inc. All rights reserved. 49d59b708SYixun Lan */ 59d59b708SYixun Lan 68c0cf40fSJerome Brunet#include <dt-bindings/clock/axg-aoclkc.h> 78909e722SJerome Brunet#include <dt-bindings/clock/axg-audio-clkc.h> 806b7a631SYixun Lan#include <dt-bindings/clock/axg-clkc.h> 98c0cf40fSJerome Brunet#include <dt-bindings/gpio/gpio.h> 10221cf34bSNan Li#include <dt-bindings/gpio/meson-axg-gpio.h> 118c0cf40fSJerome Brunet#include <dt-bindings/interrupt-controller/irq.h> 128c0cf40fSJerome Brunet#include <dt-bindings/interrupt-controller/arm-gic.h> 13f2b8f6a9SJerome Brunet#include <dt-bindings/reset/amlogic,meson-axg-audio-arb.h> 148c0cf40fSJerome Brunet#include <dt-bindings/reset/amlogic,meson-axg-reset.h> 159d59b708SYixun Lan 169d59b708SYixun Lan/ { 179d59b708SYixun Lan compatible = "amlogic,meson-axg"; 189d59b708SYixun Lan 199d59b708SYixun Lan interrupt-parent = <&gic>; 209d59b708SYixun Lan #address-cells = <2>; 219d59b708SYixun Lan #size-cells = <2>; 229d59b708SYixun Lan 23fbd5cbc5SJerome Brunet tdmif_a: audio-controller-0 { 248c0cf40fSJerome Brunet compatible = "amlogic,axg-tdm-iface"; 258c0cf40fSJerome Brunet #sound-dai-cells = <0>; 268c0cf40fSJerome Brunet sound-name-prefix = "TDM_A"; 278c0cf40fSJerome Brunet clocks = <&clkc_audio AUD_CLKID_MST_A_MCLK>, 288c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_A_SCLK>, 298c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_A_LRCLK>; 308c0cf40fSJerome Brunet clock-names = "mclk", "sclk", "lrclk"; 318c0cf40fSJerome Brunet status = "disabled"; 329d59b708SYixun Lan }; 339d59b708SYixun Lan 34fbd5cbc5SJerome Brunet tdmif_b: audio-controller-1 { 358c0cf40fSJerome Brunet compatible = "amlogic,axg-tdm-iface"; 368c0cf40fSJerome Brunet #sound-dai-cells = <0>; 378c0cf40fSJerome Brunet sound-name-prefix = "TDM_B"; 388c0cf40fSJerome Brunet clocks = <&clkc_audio AUD_CLKID_MST_B_MCLK>, 398c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_B_SCLK>, 408c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_B_LRCLK>; 418c0cf40fSJerome Brunet clock-names = "mclk", "sclk", "lrclk"; 428c0cf40fSJerome Brunet status = "disabled"; 439d59b708SYixun Lan }; 448c0cf40fSJerome Brunet 45fbd5cbc5SJerome Brunet tdmif_c: audio-controller-2 { 468c0cf40fSJerome Brunet compatible = "amlogic,axg-tdm-iface"; 478c0cf40fSJerome Brunet #sound-dai-cells = <0>; 488c0cf40fSJerome Brunet sound-name-prefix = "TDM_C"; 498c0cf40fSJerome Brunet clocks = <&clkc_audio AUD_CLKID_MST_C_MCLK>, 508c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_C_SCLK>, 518c0cf40fSJerome Brunet <&clkc_audio AUD_CLKID_MST_C_LRCLK>; 528c0cf40fSJerome Brunet clock-names = "mclk", "sclk", "lrclk"; 538c0cf40fSJerome Brunet status = "disabled"; 548c0cf40fSJerome Brunet }; 558c0cf40fSJerome Brunet 568c0cf40fSJerome Brunet ao_alt_xtal: ao_alt_xtal-clk { 578c0cf40fSJerome Brunet compatible = "fixed-clock"; 588c0cf40fSJerome Brunet clock-frequency = <32000000>; 598c0cf40fSJerome Brunet clock-output-names = "ao_alt_xtal"; 608c0cf40fSJerome Brunet #clock-cells = <0>; 618c0cf40fSJerome Brunet }; 628c0cf40fSJerome Brunet 638c0cf40fSJerome Brunet arm-pmu { 648c0cf40fSJerome Brunet compatible = "arm,cortex-a53-pmu"; 658c0cf40fSJerome Brunet interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 668c0cf40fSJerome Brunet <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 678c0cf40fSJerome Brunet <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 688c0cf40fSJerome Brunet <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 698c0cf40fSJerome Brunet interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 709d59b708SYixun Lan }; 719d59b708SYixun Lan 729d59b708SYixun Lan cpus { 739d59b708SYixun Lan #address-cells = <0x2>; 749d59b708SYixun Lan #size-cells = <0x0>; 759d59b708SYixun Lan 769d59b708SYixun Lan cpu0: cpu@0 { 779d59b708SYixun Lan device_type = "cpu"; 789d59b708SYixun Lan compatible = "arm,cortex-a53", "arm,armv8"; 799d59b708SYixun Lan reg = <0x0 0x0>; 809d59b708SYixun Lan enable-method = "psci"; 819d59b708SYixun Lan next-level-cache = <&l2>; 822c130695SJerome Brunet clocks = <&scpi_dvfs 0>; 839d59b708SYixun Lan }; 849d59b708SYixun Lan 859d59b708SYixun Lan cpu1: cpu@1 { 869d59b708SYixun Lan device_type = "cpu"; 879d59b708SYixun Lan compatible = "arm,cortex-a53", "arm,armv8"; 889d59b708SYixun Lan reg = <0x0 0x1>; 899d59b708SYixun Lan enable-method = "psci"; 909d59b708SYixun Lan next-level-cache = <&l2>; 912c130695SJerome Brunet clocks = <&scpi_dvfs 0>; 929d59b708SYixun Lan }; 939d59b708SYixun Lan 949d59b708SYixun Lan cpu2: cpu@2 { 959d59b708SYixun Lan device_type = "cpu"; 969d59b708SYixun Lan compatible = "arm,cortex-a53", "arm,armv8"; 979d59b708SYixun Lan reg = <0x0 0x2>; 989d59b708SYixun Lan enable-method = "psci"; 999d59b708SYixun Lan next-level-cache = <&l2>; 1002c130695SJerome Brunet clocks = <&scpi_dvfs 0>; 1019d59b708SYixun Lan }; 1029d59b708SYixun Lan 1039d59b708SYixun Lan cpu3: cpu@3 { 1049d59b708SYixun Lan device_type = "cpu"; 1059d59b708SYixun Lan compatible = "arm,cortex-a53", "arm,armv8"; 1069d59b708SYixun Lan reg = <0x0 0x3>; 1079d59b708SYixun Lan enable-method = "psci"; 1089d59b708SYixun Lan next-level-cache = <&l2>; 1092c130695SJerome Brunet clocks = <&scpi_dvfs 0>; 1109d59b708SYixun Lan }; 1119d59b708SYixun Lan 1129d59b708SYixun Lan l2: l2-cache0 { 1139d59b708SYixun Lan compatible = "cache"; 1149d59b708SYixun Lan }; 1159d59b708SYixun Lan }; 1169d59b708SYixun Lan 11796dc5702SJerome Brunet sm: secure-monitor { 11896dc5702SJerome Brunet compatible = "amlogic,meson-gxbb-sm"; 11996dc5702SJerome Brunet }; 12096dc5702SJerome Brunet 1219d59b708SYixun Lan psci { 1229d59b708SYixun Lan compatible = "arm,psci-1.0"; 1239d59b708SYixun Lan method = "smc"; 1249d59b708SYixun Lan }; 1259d59b708SYixun Lan 1268c0cf40fSJerome Brunet reserved-memory { 1278c0cf40fSJerome Brunet #address-cells = <2>; 1288c0cf40fSJerome Brunet #size-cells = <2>; 1298c0cf40fSJerome Brunet ranges; 1308c0cf40fSJerome Brunet 1318c0cf40fSJerome Brunet /* 16 MiB reserved for Hardware ROM Firmware */ 1328c0cf40fSJerome Brunet hwrom_reserved: hwrom@0 { 1338c0cf40fSJerome Brunet reg = <0x0 0x0 0x0 0x1000000>; 1348c0cf40fSJerome Brunet no-map; 13508307aabSJerome Brunet }; 13608307aabSJerome Brunet 1378c0cf40fSJerome Brunet /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */ 1388c0cf40fSJerome Brunet secmon_reserved: secmon@5000000 { 1398c0cf40fSJerome Brunet reg = <0x0 0x05000000 0x0 0x300000>; 1408c0cf40fSJerome Brunet no-map; 14108307aabSJerome Brunet }; 1425e395e14SYixun Lan }; 1435e395e14SYixun Lan 1442c130695SJerome Brunet scpi { 1452c130695SJerome Brunet compatible = "arm,scpi-pre-1.0"; 1462c130695SJerome Brunet mboxes = <&mailbox 1 &mailbox 2>; 1472c130695SJerome Brunet shmem = <&cpu_scp_lpri &cpu_scp_hpri>; 1482c130695SJerome Brunet 1492c130695SJerome Brunet scpi_clocks: clocks { 1502c130695SJerome Brunet compatible = "arm,scpi-clocks"; 1512c130695SJerome Brunet 1522c130695SJerome Brunet scpi_dvfs: clock-controller { 1532c130695SJerome Brunet compatible = "arm,scpi-dvfs-clocks"; 1542c130695SJerome Brunet #clock-cells = <1>; 1552c130695SJerome Brunet clock-indices = <0>; 1562c130695SJerome Brunet clock-output-names = "vcpu"; 1572c130695SJerome Brunet }; 1582c130695SJerome Brunet }; 1592c130695SJerome Brunet 1602c130695SJerome Brunet scpi_sensors: sensors { 1612c130695SJerome Brunet compatible = "amlogic,meson-gxbb-scpi-sensors"; 1622c130695SJerome Brunet #thermal-sensor-cells = <1>; 1632c130695SJerome Brunet }; 1642c130695SJerome Brunet }; 1652c130695SJerome Brunet 1669d59b708SYixun Lan soc { 1679d59b708SYixun Lan compatible = "simple-bus"; 1689d59b708SYixun Lan #address-cells = <2>; 1699d59b708SYixun Lan #size-cells = <2>; 1709d59b708SYixun Lan ranges; 1719d59b708SYixun Lan 1728c0cf40fSJerome Brunet ethmac: ethernet@ff3f0000 { 173eaf8f57cSNeil Armstrong compatible = "amlogic,meson-axg-dwmac", "snps,dwmac"; 1748c0cf40fSJerome Brunet reg = <0x0 0xff3f0000 0x0 0x10000 1758c0cf40fSJerome Brunet 0x0 0xff634540 0x0 0x8>; 1768c0cf40fSJerome Brunet interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; 1778c0cf40fSJerome Brunet interrupt-names = "macirq"; 1788c0cf40fSJerome Brunet clocks = <&clkc CLKID_ETH>, 1798c0cf40fSJerome Brunet <&clkc CLKID_FCLK_DIV2>, 1808c0cf40fSJerome Brunet <&clkc CLKID_MPLL2>; 1818c0cf40fSJerome Brunet clock-names = "stmmaceth", "clkin0", "clkin1"; 1828c0cf40fSJerome Brunet status = "disabled"; 1838c0cf40fSJerome Brunet }; 1848c0cf40fSJerome Brunet 185c362e4e0SJerome Brunet pdm: audio-controller@ff632000 { 186c362e4e0SJerome Brunet compatible = "amlogic,axg-pdm"; 187c362e4e0SJerome Brunet reg = <0x0 0xff632000 0x0 0x34>; 188c362e4e0SJerome Brunet #sound-dai-cells = <0>; 189c362e4e0SJerome Brunet sound-name-prefix = "PDM"; 190c362e4e0SJerome Brunet clocks = <&clkc_audio AUD_CLKID_PDM>, 191c362e4e0SJerome Brunet <&clkc_audio AUD_CLKID_PDM_DCLK>, 192c362e4e0SJerome Brunet <&clkc_audio AUD_CLKID_PDM_SYSCLK>; 193c362e4e0SJerome Brunet clock-names = "pclk", "dclk", "sysclk"; 194c362e4e0SJerome Brunet status = "disabled"; 195c362e4e0SJerome Brunet }; 196c362e4e0SJerome Brunet 1978c0cf40fSJerome Brunet periphs: bus@ff634000 { 198221cf34bSNan Li compatible = "simple-bus"; 1998c0cf40fSJerome Brunet reg = <0x0 0xff634000 0x0 0x2000>; 200221cf34bSNan Li #address-cells = <2>; 201221cf34bSNan Li #size-cells = <2>; 2028c0cf40fSJerome Brunet ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>; 203221cf34bSNan Li 2048c0cf40fSJerome Brunet hwrng: rng@18 { 2058c0cf40fSJerome Brunet compatible = "amlogic,meson-rng"; 2068c0cf40fSJerome Brunet reg = <0x0 0x18 0x0 0x4>; 2078c0cf40fSJerome Brunet clocks = <&clkc CLKID_RNG0>; 2088c0cf40fSJerome Brunet clock-names = "core"; 209221cf34bSNan Li }; 210221cf34bSNan Li 2118c0cf40fSJerome Brunet pinctrl_periphs: pinctrl@480 { 2128c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-periphs-pinctrl"; 2138c0cf40fSJerome Brunet #address-cells = <2>; 2148c0cf40fSJerome Brunet #size-cells = <2>; 2158c0cf40fSJerome Brunet ranges; 2168c0cf40fSJerome Brunet 2178c0cf40fSJerome Brunet gpio: bank@480 { 2188c0cf40fSJerome Brunet reg = <0x0 0x00480 0x0 0x40>, 2198c0cf40fSJerome Brunet <0x0 0x004e8 0x0 0x14>, 2208c0cf40fSJerome Brunet <0x0 0x00520 0x0 0x14>, 2218c0cf40fSJerome Brunet <0x0 0x00430 0x0 0x3c>; 2228c0cf40fSJerome Brunet reg-names = "mux", "pull", "pull-enable", "gpio"; 2238c0cf40fSJerome Brunet gpio-controller; 2248c0cf40fSJerome Brunet #gpio-cells = <2>; 2258c0cf40fSJerome Brunet gpio-ranges = <&pinctrl_periphs 0 0 86>; 226221cf34bSNan Li }; 2278c0cf40fSJerome Brunet 2288c0cf40fSJerome Brunet i2c0_pins: i2c0 { 2298c0cf40fSJerome Brunet mux { 2308c0cf40fSJerome Brunet groups = "i2c0_sck", 2318c0cf40fSJerome Brunet "i2c0_sda"; 2328c0cf40fSJerome Brunet function = "i2c0"; 2338c0cf40fSJerome Brunet }; 2348c0cf40fSJerome Brunet }; 2358c0cf40fSJerome Brunet 2368c0cf40fSJerome Brunet i2c1_x_pins: i2c1_x { 2378c0cf40fSJerome Brunet mux { 2388c0cf40fSJerome Brunet groups = "i2c1_sck_x", 2398c0cf40fSJerome Brunet "i2c1_sda_x"; 2408c0cf40fSJerome Brunet function = "i2c1"; 2418c0cf40fSJerome Brunet }; 2428c0cf40fSJerome Brunet }; 2438c0cf40fSJerome Brunet 2448c0cf40fSJerome Brunet i2c1_z_pins: i2c1_z { 2458c0cf40fSJerome Brunet mux { 2468c0cf40fSJerome Brunet groups = "i2c1_sck_z", 2478c0cf40fSJerome Brunet "i2c1_sda_z"; 2488c0cf40fSJerome Brunet function = "i2c1"; 2498c0cf40fSJerome Brunet }; 2508c0cf40fSJerome Brunet }; 2518c0cf40fSJerome Brunet 2528c0cf40fSJerome Brunet i2c2_a_pins: i2c2_a { 2538c0cf40fSJerome Brunet mux { 2548c0cf40fSJerome Brunet groups = "i2c2_sck_a", 2558c0cf40fSJerome Brunet "i2c2_sda_a"; 2568c0cf40fSJerome Brunet function = "i2c2"; 2578c0cf40fSJerome Brunet }; 2588c0cf40fSJerome Brunet }; 2598c0cf40fSJerome Brunet 2608c0cf40fSJerome Brunet i2c2_x_pins: i2c2_x { 2618c0cf40fSJerome Brunet mux { 2628c0cf40fSJerome Brunet groups = "i2c2_sck_x", 2638c0cf40fSJerome Brunet "i2c2_sda_x"; 2648c0cf40fSJerome Brunet function = "i2c2"; 2658c0cf40fSJerome Brunet }; 2668c0cf40fSJerome Brunet }; 2678c0cf40fSJerome Brunet 2688c0cf40fSJerome Brunet i2c3_a6_pins: i2c3_a6 { 2698c0cf40fSJerome Brunet mux { 2708c0cf40fSJerome Brunet groups = "i2c3_sda_a6", 2718c0cf40fSJerome Brunet "i2c3_sck_a7"; 2728c0cf40fSJerome Brunet function = "i2c3"; 2738c0cf40fSJerome Brunet }; 2748c0cf40fSJerome Brunet }; 2758c0cf40fSJerome Brunet 2768c0cf40fSJerome Brunet i2c3_a12_pins: i2c3_a12 { 2778c0cf40fSJerome Brunet mux { 2788c0cf40fSJerome Brunet groups = "i2c3_sda_a12", 2798c0cf40fSJerome Brunet "i2c3_sck_a13"; 2808c0cf40fSJerome Brunet function = "i2c3"; 2818c0cf40fSJerome Brunet }; 2828c0cf40fSJerome Brunet }; 2838c0cf40fSJerome Brunet 2848c0cf40fSJerome Brunet i2c3_a19_pins: i2c3_a19 { 2858c0cf40fSJerome Brunet mux { 2868c0cf40fSJerome Brunet groups = "i2c3_sda_a19", 2878c0cf40fSJerome Brunet "i2c3_sck_a20"; 2888c0cf40fSJerome Brunet function = "i2c3"; 2898c0cf40fSJerome Brunet }; 2908c0cf40fSJerome Brunet }; 2918c0cf40fSJerome Brunet 2928c0cf40fSJerome Brunet emmc_pins: emmc { 2938c0cf40fSJerome Brunet mux { 2948c0cf40fSJerome Brunet groups = "emmc_nand_d0", 2958c0cf40fSJerome Brunet "emmc_nand_d1", 2968c0cf40fSJerome Brunet "emmc_nand_d2", 2978c0cf40fSJerome Brunet "emmc_nand_d3", 2988c0cf40fSJerome Brunet "emmc_nand_d4", 2998c0cf40fSJerome Brunet "emmc_nand_d5", 3008c0cf40fSJerome Brunet "emmc_nand_d6", 3018c0cf40fSJerome Brunet "emmc_nand_d7", 3028c0cf40fSJerome Brunet "emmc_clk", 3038c0cf40fSJerome Brunet "emmc_cmd", 3048c0cf40fSJerome Brunet "emmc_ds"; 3058c0cf40fSJerome Brunet function = "emmc"; 3068c0cf40fSJerome Brunet }; 3078c0cf40fSJerome Brunet }; 3088c0cf40fSJerome Brunet 3098c0cf40fSJerome Brunet emmc_clk_gate_pins: emmc_clk_gate { 3108c0cf40fSJerome Brunet mux { 3118c0cf40fSJerome Brunet groups = "BOOT_8"; 3128c0cf40fSJerome Brunet function = "gpio_periphs"; 3138c0cf40fSJerome Brunet }; 3148c0cf40fSJerome Brunet cfg-pull-down { 3158c0cf40fSJerome Brunet pins = "BOOT_8"; 3168c0cf40fSJerome Brunet bias-pull-down; 3178c0cf40fSJerome Brunet }; 3188c0cf40fSJerome Brunet }; 3198c0cf40fSJerome Brunet 3208c0cf40fSJerome Brunet eth_rgmii_x_pins: eth-x-rgmii { 3218c0cf40fSJerome Brunet mux { 3228c0cf40fSJerome Brunet groups = "eth_mdio_x", 3238c0cf40fSJerome Brunet "eth_mdc_x", 3248c0cf40fSJerome Brunet "eth_rgmii_rx_clk_x", 3258c0cf40fSJerome Brunet "eth_rx_dv_x", 3268c0cf40fSJerome Brunet "eth_rxd0_x", 3278c0cf40fSJerome Brunet "eth_rxd1_x", 3288c0cf40fSJerome Brunet "eth_rxd2_rgmii", 3298c0cf40fSJerome Brunet "eth_rxd3_rgmii", 3308c0cf40fSJerome Brunet "eth_rgmii_tx_clk", 3318c0cf40fSJerome Brunet "eth_txen_x", 3328c0cf40fSJerome Brunet "eth_txd0_x", 3338c0cf40fSJerome Brunet "eth_txd1_x", 3348c0cf40fSJerome Brunet "eth_txd2_rgmii", 3358c0cf40fSJerome Brunet "eth_txd3_rgmii"; 3368c0cf40fSJerome Brunet function = "eth"; 3378c0cf40fSJerome Brunet }; 3388c0cf40fSJerome Brunet }; 3398c0cf40fSJerome Brunet 3408c0cf40fSJerome Brunet eth_rgmii_y_pins: eth-y-rgmii { 3418c0cf40fSJerome Brunet mux { 3428c0cf40fSJerome Brunet groups = "eth_mdio_y", 3438c0cf40fSJerome Brunet "eth_mdc_y", 3448c0cf40fSJerome Brunet "eth_rgmii_rx_clk_y", 3458c0cf40fSJerome Brunet "eth_rx_dv_y", 3468c0cf40fSJerome Brunet "eth_rxd0_y", 3478c0cf40fSJerome Brunet "eth_rxd1_y", 3488c0cf40fSJerome Brunet "eth_rxd2_rgmii", 3498c0cf40fSJerome Brunet "eth_rxd3_rgmii", 3508c0cf40fSJerome Brunet "eth_rgmii_tx_clk", 3518c0cf40fSJerome Brunet "eth_txen_y", 3528c0cf40fSJerome Brunet "eth_txd0_y", 3538c0cf40fSJerome Brunet "eth_txd1_y", 3548c0cf40fSJerome Brunet "eth_txd2_rgmii", 3558c0cf40fSJerome Brunet "eth_txd3_rgmii"; 3568c0cf40fSJerome Brunet function = "eth"; 3578c0cf40fSJerome Brunet }; 3588c0cf40fSJerome Brunet }; 3598c0cf40fSJerome Brunet 3608c0cf40fSJerome Brunet eth_rmii_x_pins: eth-x-rmii { 3618c0cf40fSJerome Brunet mux { 3628c0cf40fSJerome Brunet groups = "eth_mdio_x", 3638c0cf40fSJerome Brunet "eth_mdc_x", 3648c0cf40fSJerome Brunet "eth_rgmii_rx_clk_x", 3658c0cf40fSJerome Brunet "eth_rx_dv_x", 3668c0cf40fSJerome Brunet "eth_rxd0_x", 3678c0cf40fSJerome Brunet "eth_rxd1_x", 3688c0cf40fSJerome Brunet "eth_txen_x", 3698c0cf40fSJerome Brunet "eth_txd0_x", 3708c0cf40fSJerome Brunet "eth_txd1_x"; 3718c0cf40fSJerome Brunet function = "eth"; 3728c0cf40fSJerome Brunet }; 3738c0cf40fSJerome Brunet }; 3748c0cf40fSJerome Brunet 3758c0cf40fSJerome Brunet eth_rmii_y_pins: eth-y-rmii { 3768c0cf40fSJerome Brunet mux { 3778c0cf40fSJerome Brunet groups = "eth_mdio_y", 3788c0cf40fSJerome Brunet "eth_mdc_y", 3798c0cf40fSJerome Brunet "eth_rgmii_rx_clk_y", 3808c0cf40fSJerome Brunet "eth_rx_dv_y", 3818c0cf40fSJerome Brunet "eth_rxd0_y", 3828c0cf40fSJerome Brunet "eth_rxd1_y", 3838c0cf40fSJerome Brunet "eth_txen_y", 3848c0cf40fSJerome Brunet "eth_txd0_y", 3858c0cf40fSJerome Brunet "eth_txd1_y"; 3868c0cf40fSJerome Brunet function = "eth"; 3878c0cf40fSJerome Brunet }; 3888c0cf40fSJerome Brunet }; 3898c0cf40fSJerome Brunet 3908c0cf40fSJerome Brunet mclk_b_pins: mclk_b { 3918c0cf40fSJerome Brunet mux { 3928c0cf40fSJerome Brunet groups = "mclk_b"; 3938c0cf40fSJerome Brunet function = "mclk_b"; 3948c0cf40fSJerome Brunet }; 3958c0cf40fSJerome Brunet }; 3968c0cf40fSJerome Brunet 3978c0cf40fSJerome Brunet mclk_c_pins: mclk_c { 3988c0cf40fSJerome Brunet mux { 3998c0cf40fSJerome Brunet groups = "mclk_c"; 4008c0cf40fSJerome Brunet function = "mclk_c"; 4018c0cf40fSJerome Brunet }; 4028c0cf40fSJerome Brunet }; 4038c0cf40fSJerome Brunet 4048c0cf40fSJerome Brunet pdm_dclk_a14_pins: pdm_dclk_a14 { 4058c0cf40fSJerome Brunet mux { 4068c0cf40fSJerome Brunet groups = "pdm_dclk_a14"; 4078c0cf40fSJerome Brunet function = "pdm"; 4088c0cf40fSJerome Brunet }; 4098c0cf40fSJerome Brunet }; 4108c0cf40fSJerome Brunet 4118c0cf40fSJerome Brunet pdm_dclk_a19_pins: pdm_dclk_a19 { 4128c0cf40fSJerome Brunet mux { 4138c0cf40fSJerome Brunet groups = "pdm_dclk_a19"; 4148c0cf40fSJerome Brunet function = "pdm"; 4158c0cf40fSJerome Brunet }; 4168c0cf40fSJerome Brunet }; 4178c0cf40fSJerome Brunet 4188c0cf40fSJerome Brunet pdm_din0_pins: pdm_din0 { 4198c0cf40fSJerome Brunet mux { 4208c0cf40fSJerome Brunet groups = "pdm_din0"; 4218c0cf40fSJerome Brunet function = "pdm"; 4228c0cf40fSJerome Brunet }; 4238c0cf40fSJerome Brunet }; 4248c0cf40fSJerome Brunet 4258c0cf40fSJerome Brunet pdm_din1_pins: pdm_din1 { 4268c0cf40fSJerome Brunet mux { 4278c0cf40fSJerome Brunet groups = "pdm_din1"; 4288c0cf40fSJerome Brunet function = "pdm"; 4298c0cf40fSJerome Brunet }; 4308c0cf40fSJerome Brunet }; 4318c0cf40fSJerome Brunet 4328c0cf40fSJerome Brunet pdm_din2_pins: pdm_din2 { 4338c0cf40fSJerome Brunet mux { 4348c0cf40fSJerome Brunet groups = "pdm_din2"; 4358c0cf40fSJerome Brunet function = "pdm"; 4368c0cf40fSJerome Brunet }; 4378c0cf40fSJerome Brunet }; 4388c0cf40fSJerome Brunet 4398c0cf40fSJerome Brunet pdm_din3_pins: pdm_din3 { 4408c0cf40fSJerome Brunet mux { 4418c0cf40fSJerome Brunet groups = "pdm_din3"; 4428c0cf40fSJerome Brunet function = "pdm"; 4438c0cf40fSJerome Brunet }; 4448c0cf40fSJerome Brunet }; 4458c0cf40fSJerome Brunet 4468c0cf40fSJerome Brunet pwm_a_a_pins: pwm_a_a { 4478c0cf40fSJerome Brunet mux { 4488c0cf40fSJerome Brunet groups = "pwm_a_a"; 4498c0cf40fSJerome Brunet function = "pwm_a"; 4508c0cf40fSJerome Brunet }; 4518c0cf40fSJerome Brunet }; 4528c0cf40fSJerome Brunet 4538c0cf40fSJerome Brunet pwm_a_x18_pins: pwm_a_x18 { 4548c0cf40fSJerome Brunet mux { 4558c0cf40fSJerome Brunet groups = "pwm_a_x18"; 4568c0cf40fSJerome Brunet function = "pwm_a"; 4578c0cf40fSJerome Brunet }; 4588c0cf40fSJerome Brunet }; 4598c0cf40fSJerome Brunet 4608c0cf40fSJerome Brunet pwm_a_x20_pins: pwm_a_x20 { 4618c0cf40fSJerome Brunet mux { 4628c0cf40fSJerome Brunet groups = "pwm_a_x20"; 4638c0cf40fSJerome Brunet function = "pwm_a"; 4648c0cf40fSJerome Brunet }; 4658c0cf40fSJerome Brunet }; 4668c0cf40fSJerome Brunet 4678c0cf40fSJerome Brunet pwm_a_z_pins: pwm_a_z { 4688c0cf40fSJerome Brunet mux { 4698c0cf40fSJerome Brunet groups = "pwm_a_z"; 4708c0cf40fSJerome Brunet function = "pwm_a"; 4718c0cf40fSJerome Brunet }; 4728c0cf40fSJerome Brunet }; 4738c0cf40fSJerome Brunet 4748c0cf40fSJerome Brunet pwm_b_a_pins: pwm_b_a { 4758c0cf40fSJerome Brunet mux { 4768c0cf40fSJerome Brunet groups = "pwm_b_a"; 4778c0cf40fSJerome Brunet function = "pwm_b"; 4788c0cf40fSJerome Brunet }; 4798c0cf40fSJerome Brunet }; 4808c0cf40fSJerome Brunet 4818c0cf40fSJerome Brunet pwm_b_x_pins: pwm_b_x { 4828c0cf40fSJerome Brunet mux { 4838c0cf40fSJerome Brunet groups = "pwm_b_x"; 4848c0cf40fSJerome Brunet function = "pwm_b"; 4858c0cf40fSJerome Brunet }; 4868c0cf40fSJerome Brunet }; 4878c0cf40fSJerome Brunet 4888c0cf40fSJerome Brunet pwm_b_z_pins: pwm_b_z { 4898c0cf40fSJerome Brunet mux { 4908c0cf40fSJerome Brunet groups = "pwm_b_z"; 4918c0cf40fSJerome Brunet function = "pwm_b"; 4928c0cf40fSJerome Brunet }; 4938c0cf40fSJerome Brunet }; 4948c0cf40fSJerome Brunet 4958c0cf40fSJerome Brunet pwm_c_a_pins: pwm_c_a { 4968c0cf40fSJerome Brunet mux { 4978c0cf40fSJerome Brunet groups = "pwm_c_a"; 4988c0cf40fSJerome Brunet function = "pwm_c"; 4998c0cf40fSJerome Brunet }; 5008c0cf40fSJerome Brunet }; 5018c0cf40fSJerome Brunet 5028c0cf40fSJerome Brunet pwm_c_x10_pins: pwm_c_x10 { 5038c0cf40fSJerome Brunet mux { 5048c0cf40fSJerome Brunet groups = "pwm_c_x10"; 5058c0cf40fSJerome Brunet function = "pwm_c"; 5068c0cf40fSJerome Brunet }; 5078c0cf40fSJerome Brunet }; 5088c0cf40fSJerome Brunet 5098c0cf40fSJerome Brunet pwm_c_x17_pins: pwm_c_x17 { 5108c0cf40fSJerome Brunet mux { 5118c0cf40fSJerome Brunet groups = "pwm_c_x17"; 5128c0cf40fSJerome Brunet function = "pwm_c"; 5138c0cf40fSJerome Brunet }; 5148c0cf40fSJerome Brunet }; 5158c0cf40fSJerome Brunet 5168c0cf40fSJerome Brunet pwm_d_x11_pins: pwm_d_x11 { 5178c0cf40fSJerome Brunet mux { 5188c0cf40fSJerome Brunet groups = "pwm_d_x11"; 5198c0cf40fSJerome Brunet function = "pwm_d"; 5208c0cf40fSJerome Brunet }; 5218c0cf40fSJerome Brunet }; 5228c0cf40fSJerome Brunet 5238c0cf40fSJerome Brunet pwm_d_x16_pins: pwm_d_x16 { 5248c0cf40fSJerome Brunet mux { 5258c0cf40fSJerome Brunet groups = "pwm_d_x16"; 5268c0cf40fSJerome Brunet function = "pwm_d"; 5278c0cf40fSJerome Brunet }; 5288c0cf40fSJerome Brunet }; 5298c0cf40fSJerome Brunet 5308c0cf40fSJerome Brunet sdio_pins: sdio { 5318c0cf40fSJerome Brunet mux { 5328c0cf40fSJerome Brunet groups = "sdio_d0", 5338c0cf40fSJerome Brunet "sdio_d1", 5348c0cf40fSJerome Brunet "sdio_d2", 5358c0cf40fSJerome Brunet "sdio_d3", 5368c0cf40fSJerome Brunet "sdio_cmd", 5378c0cf40fSJerome Brunet "sdio_clk"; 5388c0cf40fSJerome Brunet function = "sdio"; 5398c0cf40fSJerome Brunet }; 5408c0cf40fSJerome Brunet }; 5418c0cf40fSJerome Brunet 5428c0cf40fSJerome Brunet sdio_clk_gate_pins: sdio_clk_gate { 5438c0cf40fSJerome Brunet mux { 5448c0cf40fSJerome Brunet groups = "GPIOX_4"; 5458c0cf40fSJerome Brunet function = "gpio_periphs"; 5468c0cf40fSJerome Brunet }; 5478c0cf40fSJerome Brunet cfg-pull-down { 5488c0cf40fSJerome Brunet pins = "GPIOX_4"; 5498c0cf40fSJerome Brunet bias-pull-down; 5508c0cf40fSJerome Brunet }; 5518c0cf40fSJerome Brunet }; 5528c0cf40fSJerome Brunet 5538c0cf40fSJerome Brunet spdif_in_z_pins: spdif_in_z { 5548c0cf40fSJerome Brunet mux { 5558c0cf40fSJerome Brunet groups = "spdif_in_z"; 5568c0cf40fSJerome Brunet function = "spdif_in"; 5578c0cf40fSJerome Brunet }; 5588c0cf40fSJerome Brunet }; 5598c0cf40fSJerome Brunet 5608c0cf40fSJerome Brunet spdif_in_a1_pins: spdif_in_a1 { 5618c0cf40fSJerome Brunet mux { 5628c0cf40fSJerome Brunet groups = "spdif_in_a1"; 5638c0cf40fSJerome Brunet function = "spdif_in"; 5648c0cf40fSJerome Brunet }; 5658c0cf40fSJerome Brunet }; 5668c0cf40fSJerome Brunet 5678c0cf40fSJerome Brunet spdif_in_a7_pins: spdif_in_a7 { 5688c0cf40fSJerome Brunet mux { 5698c0cf40fSJerome Brunet groups = "spdif_in_a7"; 5708c0cf40fSJerome Brunet function = "spdif_in"; 5718c0cf40fSJerome Brunet }; 5728c0cf40fSJerome Brunet }; 5738c0cf40fSJerome Brunet 5748c0cf40fSJerome Brunet spdif_in_a19_pins: spdif_in_a19 { 5758c0cf40fSJerome Brunet mux { 5768c0cf40fSJerome Brunet groups = "spdif_in_a19"; 5778c0cf40fSJerome Brunet function = "spdif_in"; 5788c0cf40fSJerome Brunet }; 5798c0cf40fSJerome Brunet }; 5808c0cf40fSJerome Brunet 5818c0cf40fSJerome Brunet spdif_in_a20_pins: spdif_in_a20 { 5828c0cf40fSJerome Brunet mux { 5838c0cf40fSJerome Brunet groups = "spdif_in_a20"; 5848c0cf40fSJerome Brunet function = "spdif_in"; 5858c0cf40fSJerome Brunet }; 5868c0cf40fSJerome Brunet }; 5878c0cf40fSJerome Brunet 5888c0cf40fSJerome Brunet spdif_out_a1_pins: spdif_out_a1 { 5898c0cf40fSJerome Brunet mux { 5908c0cf40fSJerome Brunet groups = "spdif_out_a1"; 5918c0cf40fSJerome Brunet function = "spdif_out"; 5928c0cf40fSJerome Brunet }; 5938c0cf40fSJerome Brunet }; 5948c0cf40fSJerome Brunet 5958c0cf40fSJerome Brunet spdif_out_a11_pins: spdif_out_a11 { 5968c0cf40fSJerome Brunet mux { 5978c0cf40fSJerome Brunet groups = "spdif_out_a11"; 5988c0cf40fSJerome Brunet function = "spdif_out"; 5998c0cf40fSJerome Brunet }; 6008c0cf40fSJerome Brunet }; 6018c0cf40fSJerome Brunet 6028c0cf40fSJerome Brunet spdif_out_a19_pins: spdif_out_a19 { 6038c0cf40fSJerome Brunet mux { 6048c0cf40fSJerome Brunet groups = "spdif_out_a19"; 6058c0cf40fSJerome Brunet function = "spdif_out"; 6068c0cf40fSJerome Brunet }; 6078c0cf40fSJerome Brunet }; 6088c0cf40fSJerome Brunet 6098c0cf40fSJerome Brunet spdif_out_a20_pins: spdif_out_a20 { 6108c0cf40fSJerome Brunet mux { 6118c0cf40fSJerome Brunet groups = "spdif_out_a20"; 6128c0cf40fSJerome Brunet function = "spdif_out"; 6138c0cf40fSJerome Brunet }; 6148c0cf40fSJerome Brunet }; 6158c0cf40fSJerome Brunet 6168c0cf40fSJerome Brunet spdif_out_z_pins: spdif_out_z { 6178c0cf40fSJerome Brunet mux { 6188c0cf40fSJerome Brunet groups = "spdif_out_z"; 6198c0cf40fSJerome Brunet function = "spdif_out"; 6208c0cf40fSJerome Brunet }; 6218c0cf40fSJerome Brunet }; 6228c0cf40fSJerome Brunet 6238c0cf40fSJerome Brunet spi0_pins: spi0 { 6248c0cf40fSJerome Brunet mux { 6258c0cf40fSJerome Brunet groups = "spi0_miso", 6268c0cf40fSJerome Brunet "spi0_mosi", 6278c0cf40fSJerome Brunet "spi0_clk"; 6288c0cf40fSJerome Brunet function = "spi0"; 6298c0cf40fSJerome Brunet }; 6308c0cf40fSJerome Brunet }; 6318c0cf40fSJerome Brunet 6328c0cf40fSJerome Brunet spi0_ss0_pins: spi0_ss0 { 6338c0cf40fSJerome Brunet mux { 6348c0cf40fSJerome Brunet groups = "spi0_ss0"; 6358c0cf40fSJerome Brunet function = "spi0"; 6368c0cf40fSJerome Brunet }; 6378c0cf40fSJerome Brunet }; 6388c0cf40fSJerome Brunet 6398c0cf40fSJerome Brunet spi0_ss1_pins: spi0_ss1 { 6408c0cf40fSJerome Brunet mux { 6418c0cf40fSJerome Brunet groups = "spi0_ss1"; 6428c0cf40fSJerome Brunet function = "spi0"; 6438c0cf40fSJerome Brunet }; 6448c0cf40fSJerome Brunet }; 6458c0cf40fSJerome Brunet 6468c0cf40fSJerome Brunet spi0_ss2_pins: spi0_ss2 { 6478c0cf40fSJerome Brunet mux { 6488c0cf40fSJerome Brunet groups = "spi0_ss2"; 6498c0cf40fSJerome Brunet function = "spi0"; 6508c0cf40fSJerome Brunet }; 6518c0cf40fSJerome Brunet }; 6528c0cf40fSJerome Brunet 6538c0cf40fSJerome Brunet spi1_a_pins: spi1_a { 6548c0cf40fSJerome Brunet mux { 6558c0cf40fSJerome Brunet groups = "spi1_miso_a", 6568c0cf40fSJerome Brunet "spi1_mosi_a", 6578c0cf40fSJerome Brunet "spi1_clk_a"; 6588c0cf40fSJerome Brunet function = "spi1"; 6598c0cf40fSJerome Brunet }; 6608c0cf40fSJerome Brunet }; 6618c0cf40fSJerome Brunet 6628c0cf40fSJerome Brunet spi1_ss0_a_pins: spi1_ss0_a { 6638c0cf40fSJerome Brunet mux { 6648c0cf40fSJerome Brunet groups = "spi1_ss0_a"; 6658c0cf40fSJerome Brunet function = "spi1"; 6668c0cf40fSJerome Brunet }; 6678c0cf40fSJerome Brunet }; 6688c0cf40fSJerome Brunet 6698c0cf40fSJerome Brunet spi1_ss1_pins: spi1_ss1 { 6708c0cf40fSJerome Brunet mux { 6718c0cf40fSJerome Brunet groups = "spi1_ss1"; 6728c0cf40fSJerome Brunet function = "spi1"; 6738c0cf40fSJerome Brunet }; 6748c0cf40fSJerome Brunet }; 6758c0cf40fSJerome Brunet 6768c0cf40fSJerome Brunet spi1_x_pins: spi1_x { 6778c0cf40fSJerome Brunet mux { 6788c0cf40fSJerome Brunet groups = "spi1_miso_x", 6798c0cf40fSJerome Brunet "spi1_mosi_x", 6808c0cf40fSJerome Brunet "spi1_clk_x"; 6818c0cf40fSJerome Brunet function = "spi1"; 6828c0cf40fSJerome Brunet }; 6838c0cf40fSJerome Brunet }; 6848c0cf40fSJerome Brunet 6858c0cf40fSJerome Brunet spi1_ss0_x_pins: spi1_ss0_x { 6868c0cf40fSJerome Brunet mux { 6878c0cf40fSJerome Brunet groups = "spi1_ss0_x"; 6888c0cf40fSJerome Brunet function = "spi1"; 6898c0cf40fSJerome Brunet }; 6908c0cf40fSJerome Brunet }; 6918c0cf40fSJerome Brunet 6928c0cf40fSJerome Brunet tdma_din0_pins: tdma_din0 { 6938c0cf40fSJerome Brunet mux { 6948c0cf40fSJerome Brunet groups = "tdma_din0"; 6958c0cf40fSJerome Brunet function = "tdma"; 6968c0cf40fSJerome Brunet }; 6978c0cf40fSJerome Brunet }; 6988c0cf40fSJerome Brunet 6998c0cf40fSJerome Brunet tdma_dout0_x14_pins: tdma_dout0_x14 { 7008c0cf40fSJerome Brunet mux { 7018c0cf40fSJerome Brunet groups = "tdma_dout0_x14"; 7028c0cf40fSJerome Brunet function = "tdma"; 7038c0cf40fSJerome Brunet }; 7048c0cf40fSJerome Brunet }; 7058c0cf40fSJerome Brunet 7068c0cf40fSJerome Brunet tdma_dout0_x15_pins: tdma_dout0_x15 { 7078c0cf40fSJerome Brunet mux { 7088c0cf40fSJerome Brunet groups = "tdma_dout0_x15"; 7098c0cf40fSJerome Brunet function = "tdma"; 7108c0cf40fSJerome Brunet }; 7118c0cf40fSJerome Brunet }; 7128c0cf40fSJerome Brunet 7138c0cf40fSJerome Brunet tdma_dout1_pins: tdma_dout1 { 7148c0cf40fSJerome Brunet mux { 7158c0cf40fSJerome Brunet groups = "tdma_dout1"; 7168c0cf40fSJerome Brunet function = "tdma"; 7178c0cf40fSJerome Brunet }; 7188c0cf40fSJerome Brunet }; 7198c0cf40fSJerome Brunet 7208c0cf40fSJerome Brunet tdma_din1_pins: tdma_din1 { 7218c0cf40fSJerome Brunet mux { 7228c0cf40fSJerome Brunet groups = "tdma_din1"; 7238c0cf40fSJerome Brunet function = "tdma"; 7248c0cf40fSJerome Brunet }; 7258c0cf40fSJerome Brunet }; 7268c0cf40fSJerome Brunet 7278c0cf40fSJerome Brunet tdma_fs_pins: tdma_fs { 7288c0cf40fSJerome Brunet mux { 7298c0cf40fSJerome Brunet groups = "tdma_fs"; 7308c0cf40fSJerome Brunet function = "tdma"; 7318c0cf40fSJerome Brunet }; 7328c0cf40fSJerome Brunet }; 7338c0cf40fSJerome Brunet 7348c0cf40fSJerome Brunet tdma_fs_slv_pins: tdma_fs_slv { 7358c0cf40fSJerome Brunet mux { 7368c0cf40fSJerome Brunet groups = "tdma_fs_slv"; 7378c0cf40fSJerome Brunet function = "tdma"; 7388c0cf40fSJerome Brunet }; 7398c0cf40fSJerome Brunet }; 7408c0cf40fSJerome Brunet 7418c0cf40fSJerome Brunet tdma_sclk_pins: tdma_sclk { 7428c0cf40fSJerome Brunet mux { 7438c0cf40fSJerome Brunet groups = "tdma_sclk"; 7448c0cf40fSJerome Brunet function = "tdma"; 7458c0cf40fSJerome Brunet }; 7468c0cf40fSJerome Brunet }; 7478c0cf40fSJerome Brunet 7488c0cf40fSJerome Brunet tdma_sclk_slv_pins: tdma_sclk_slv { 7498c0cf40fSJerome Brunet mux { 7508c0cf40fSJerome Brunet groups = "tdma_sclk_slv"; 7518c0cf40fSJerome Brunet function = "tdma"; 7528c0cf40fSJerome Brunet }; 7538c0cf40fSJerome Brunet }; 7548c0cf40fSJerome Brunet 7558c0cf40fSJerome Brunet tdmb_din0_pins: tdmb_din0 { 7568c0cf40fSJerome Brunet mux { 7578c0cf40fSJerome Brunet groups = "tdmb_din0"; 7588c0cf40fSJerome Brunet function = "tdmb"; 7598c0cf40fSJerome Brunet }; 7608c0cf40fSJerome Brunet }; 7618c0cf40fSJerome Brunet 7628c0cf40fSJerome Brunet tdmb_din1_pins: tdmb_din1 { 7638c0cf40fSJerome Brunet mux { 7648c0cf40fSJerome Brunet groups = "tdmb_din1"; 7658c0cf40fSJerome Brunet function = "tdmb"; 7668c0cf40fSJerome Brunet }; 7678c0cf40fSJerome Brunet }; 7688c0cf40fSJerome Brunet 7698c0cf40fSJerome Brunet tdmb_din2_pins: tdmb_din2 { 7708c0cf40fSJerome Brunet mux { 7718c0cf40fSJerome Brunet groups = "tdmb_din2"; 7728c0cf40fSJerome Brunet function = "tdmb"; 7738c0cf40fSJerome Brunet }; 7748c0cf40fSJerome Brunet }; 7758c0cf40fSJerome Brunet 7768c0cf40fSJerome Brunet tdmb_din3_pins: tdmb_din3 { 7778c0cf40fSJerome Brunet mux { 7788c0cf40fSJerome Brunet groups = "tdmb_din3"; 7798c0cf40fSJerome Brunet function = "tdmb"; 7808c0cf40fSJerome Brunet }; 7818c0cf40fSJerome Brunet }; 7828c0cf40fSJerome Brunet 7838c0cf40fSJerome Brunet tdmb_dout0_pins: tdmb_dout0 { 7848c0cf40fSJerome Brunet mux { 7858c0cf40fSJerome Brunet groups = "tdmb_dout0"; 7868c0cf40fSJerome Brunet function = "tdmb"; 7878c0cf40fSJerome Brunet }; 7888c0cf40fSJerome Brunet }; 7898c0cf40fSJerome Brunet 7908c0cf40fSJerome Brunet tdmb_dout1_pins: tdmb_dout1 { 7918c0cf40fSJerome Brunet mux { 7928c0cf40fSJerome Brunet groups = "tdmb_dout1"; 7938c0cf40fSJerome Brunet function = "tdmb"; 7948c0cf40fSJerome Brunet }; 7958c0cf40fSJerome Brunet }; 7968c0cf40fSJerome Brunet 7978c0cf40fSJerome Brunet tdmb_dout2_pins: tdmb_dout2 { 7988c0cf40fSJerome Brunet mux { 7998c0cf40fSJerome Brunet groups = "tdmb_dout2"; 8008c0cf40fSJerome Brunet function = "tdmb"; 8018c0cf40fSJerome Brunet }; 8028c0cf40fSJerome Brunet }; 8038c0cf40fSJerome Brunet 8048c0cf40fSJerome Brunet tdmb_dout3_pins: tdmb_dout3 { 8058c0cf40fSJerome Brunet mux { 8068c0cf40fSJerome Brunet groups = "tdmb_dout3"; 8078c0cf40fSJerome Brunet function = "tdmb"; 8088c0cf40fSJerome Brunet }; 8098c0cf40fSJerome Brunet }; 8108c0cf40fSJerome Brunet 8118c0cf40fSJerome Brunet tdmb_fs_pins: tdmb_fs { 8128c0cf40fSJerome Brunet mux { 8138c0cf40fSJerome Brunet groups = "tdmb_fs"; 8148c0cf40fSJerome Brunet function = "tdmb"; 8158c0cf40fSJerome Brunet }; 8168c0cf40fSJerome Brunet }; 8178c0cf40fSJerome Brunet 8188c0cf40fSJerome Brunet tdmb_fs_slv_pins: tdmb_fs_slv { 8198c0cf40fSJerome Brunet mux { 8208c0cf40fSJerome Brunet groups = "tdmb_fs_slv"; 8218c0cf40fSJerome Brunet function = "tdmb"; 8228c0cf40fSJerome Brunet }; 8238c0cf40fSJerome Brunet }; 8248c0cf40fSJerome Brunet 8258c0cf40fSJerome Brunet tdmb_sclk_pins: tdmb_sclk { 8268c0cf40fSJerome Brunet mux { 8278c0cf40fSJerome Brunet groups = "tdmb_sclk"; 8288c0cf40fSJerome Brunet function = "tdmb"; 8298c0cf40fSJerome Brunet }; 8308c0cf40fSJerome Brunet }; 8318c0cf40fSJerome Brunet 8328c0cf40fSJerome Brunet tdmb_sclk_slv_pins: tdmb_sclk_slv { 8338c0cf40fSJerome Brunet mux { 8348c0cf40fSJerome Brunet groups = "tdmb_sclk_slv"; 8358c0cf40fSJerome Brunet function = "tdmb"; 8368c0cf40fSJerome Brunet }; 8378c0cf40fSJerome Brunet }; 8388c0cf40fSJerome Brunet 8398c0cf40fSJerome Brunet tdmc_fs_pins: tdmc_fs { 8408c0cf40fSJerome Brunet mux { 8418c0cf40fSJerome Brunet groups = "tdmc_fs"; 8428c0cf40fSJerome Brunet function = "tdmc"; 8438c0cf40fSJerome Brunet }; 8448c0cf40fSJerome Brunet }; 8458c0cf40fSJerome Brunet 8468c0cf40fSJerome Brunet tdmc_fs_slv_pins: tdmc_fs_slv { 8478c0cf40fSJerome Brunet mux { 8488c0cf40fSJerome Brunet groups = "tdmc_fs_slv"; 8498c0cf40fSJerome Brunet function = "tdmc"; 8508c0cf40fSJerome Brunet }; 8518c0cf40fSJerome Brunet }; 8528c0cf40fSJerome Brunet 8538c0cf40fSJerome Brunet tdmc_sclk_pins: tdmc_sclk { 8548c0cf40fSJerome Brunet mux { 8558c0cf40fSJerome Brunet groups = "tdmc_sclk"; 8568c0cf40fSJerome Brunet function = "tdmc"; 8578c0cf40fSJerome Brunet }; 8588c0cf40fSJerome Brunet }; 8598c0cf40fSJerome Brunet 8608c0cf40fSJerome Brunet tdmc_sclk_slv_pins: tdmc_sclk_slv { 8618c0cf40fSJerome Brunet mux { 8628c0cf40fSJerome Brunet groups = "tdmc_sclk_slv"; 8638c0cf40fSJerome Brunet function = "tdmc"; 8648c0cf40fSJerome Brunet }; 8658c0cf40fSJerome Brunet }; 8668c0cf40fSJerome Brunet 8678c0cf40fSJerome Brunet tdmc_din0_pins: tdmc_din0 { 8688c0cf40fSJerome Brunet mux { 8698c0cf40fSJerome Brunet groups = "tdmc_din0"; 8708c0cf40fSJerome Brunet function = "tdmc"; 8718c0cf40fSJerome Brunet }; 8728c0cf40fSJerome Brunet }; 8738c0cf40fSJerome Brunet 8748c0cf40fSJerome Brunet tdmc_din1_pins: tdmc_din1 { 8758c0cf40fSJerome Brunet mux { 8768c0cf40fSJerome Brunet groups = "tdmc_din1"; 8778c0cf40fSJerome Brunet function = "tdmc"; 8788c0cf40fSJerome Brunet }; 8798c0cf40fSJerome Brunet }; 8808c0cf40fSJerome Brunet 8818c0cf40fSJerome Brunet tdmc_din2_pins: tdmc_din2 { 8828c0cf40fSJerome Brunet mux { 8838c0cf40fSJerome Brunet groups = "tdmc_din2"; 8848c0cf40fSJerome Brunet function = "tdmc"; 8858c0cf40fSJerome Brunet }; 8868c0cf40fSJerome Brunet }; 8878c0cf40fSJerome Brunet 8888c0cf40fSJerome Brunet tdmc_din3_pins: tdmc_din3 { 8898c0cf40fSJerome Brunet mux { 8908c0cf40fSJerome Brunet groups = "tdmc_din3"; 8918c0cf40fSJerome Brunet function = "tdmc"; 8928c0cf40fSJerome Brunet }; 8938c0cf40fSJerome Brunet }; 8948c0cf40fSJerome Brunet 8958c0cf40fSJerome Brunet tdmc_dout0_pins: tdmc_dout0 { 8968c0cf40fSJerome Brunet mux { 8978c0cf40fSJerome Brunet groups = "tdmc_dout0"; 8988c0cf40fSJerome Brunet function = "tdmc"; 8998c0cf40fSJerome Brunet }; 9008c0cf40fSJerome Brunet }; 9018c0cf40fSJerome Brunet 9028c0cf40fSJerome Brunet tdmc_dout1_pins: tdmc_dout1 { 9038c0cf40fSJerome Brunet mux { 9048c0cf40fSJerome Brunet groups = "tdmc_dout1"; 9058c0cf40fSJerome Brunet function = "tdmc"; 9068c0cf40fSJerome Brunet }; 9078c0cf40fSJerome Brunet }; 9088c0cf40fSJerome Brunet 9098c0cf40fSJerome Brunet tdmc_dout2_pins: tdmc_dout2 { 9108c0cf40fSJerome Brunet mux { 9118c0cf40fSJerome Brunet groups = "tdmc_dout2"; 9128c0cf40fSJerome Brunet function = "tdmc"; 9138c0cf40fSJerome Brunet }; 9148c0cf40fSJerome Brunet }; 9158c0cf40fSJerome Brunet 9168c0cf40fSJerome Brunet tdmc_dout3_pins: tdmc_dout3 { 9178c0cf40fSJerome Brunet mux { 9188c0cf40fSJerome Brunet groups = "tdmc_dout3"; 9198c0cf40fSJerome Brunet function = "tdmc"; 9208c0cf40fSJerome Brunet }; 9218c0cf40fSJerome Brunet }; 9228c0cf40fSJerome Brunet 9238c0cf40fSJerome Brunet uart_a_pins: uart_a { 9248c0cf40fSJerome Brunet mux { 9258c0cf40fSJerome Brunet groups = "uart_tx_a", 9268c0cf40fSJerome Brunet "uart_rx_a"; 9278c0cf40fSJerome Brunet function = "uart_a"; 9288c0cf40fSJerome Brunet }; 9298c0cf40fSJerome Brunet }; 9308c0cf40fSJerome Brunet 9318c0cf40fSJerome Brunet uart_a_cts_rts_pins: uart_a_cts_rts { 9328c0cf40fSJerome Brunet mux { 9338c0cf40fSJerome Brunet groups = "uart_cts_a", 9348c0cf40fSJerome Brunet "uart_rts_a"; 9358c0cf40fSJerome Brunet function = "uart_a"; 9368c0cf40fSJerome Brunet }; 9378c0cf40fSJerome Brunet }; 9388c0cf40fSJerome Brunet 9398c0cf40fSJerome Brunet uart_b_x_pins: uart_b_x { 9408c0cf40fSJerome Brunet mux { 9418c0cf40fSJerome Brunet groups = "uart_tx_b_x", 9428c0cf40fSJerome Brunet "uart_rx_b_x"; 9438c0cf40fSJerome Brunet function = "uart_b"; 9448c0cf40fSJerome Brunet }; 9458c0cf40fSJerome Brunet }; 9468c0cf40fSJerome Brunet 9478c0cf40fSJerome Brunet uart_b_x_cts_rts_pins: uart_b_x_cts_rts { 9488c0cf40fSJerome Brunet mux { 9498c0cf40fSJerome Brunet groups = "uart_cts_b_x", 9508c0cf40fSJerome Brunet "uart_rts_b_x"; 9518c0cf40fSJerome Brunet function = "uart_b"; 9528c0cf40fSJerome Brunet }; 9538c0cf40fSJerome Brunet }; 9548c0cf40fSJerome Brunet 9558c0cf40fSJerome Brunet uart_b_z_pins: uart_b_z { 9568c0cf40fSJerome Brunet mux { 9578c0cf40fSJerome Brunet groups = "uart_tx_b_z", 9588c0cf40fSJerome Brunet "uart_rx_b_z"; 9598c0cf40fSJerome Brunet function = "uart_b"; 9608c0cf40fSJerome Brunet }; 9618c0cf40fSJerome Brunet }; 9628c0cf40fSJerome Brunet 9638c0cf40fSJerome Brunet uart_b_z_cts_rts_pins: uart_b_z_cts_rts { 9648c0cf40fSJerome Brunet mux { 9658c0cf40fSJerome Brunet groups = "uart_cts_b_z", 9668c0cf40fSJerome Brunet "uart_rts_b_z"; 9678c0cf40fSJerome Brunet function = "uart_b"; 9688c0cf40fSJerome Brunet }; 9698c0cf40fSJerome Brunet }; 9708c0cf40fSJerome Brunet 9718c0cf40fSJerome Brunet uart_ao_b_z_pins: uart_ao_b_z { 9728c0cf40fSJerome Brunet mux { 9738c0cf40fSJerome Brunet groups = "uart_ao_tx_b_z", 9748c0cf40fSJerome Brunet "uart_ao_rx_b_z"; 9758c0cf40fSJerome Brunet function = "uart_ao_b_z"; 9768c0cf40fSJerome Brunet }; 9778c0cf40fSJerome Brunet }; 9788c0cf40fSJerome Brunet 9798c0cf40fSJerome Brunet uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts { 9808c0cf40fSJerome Brunet mux { 9818c0cf40fSJerome Brunet groups = "uart_ao_cts_b_z", 9828c0cf40fSJerome Brunet "uart_ao_rts_b_z"; 9838c0cf40fSJerome Brunet function = "uart_ao_b_z"; 9848c0cf40fSJerome Brunet }; 9858c0cf40fSJerome Brunet }; 9868c0cf40fSJerome Brunet }; 9878c0cf40fSJerome Brunet }; 9888c0cf40fSJerome Brunet 9898c0cf40fSJerome Brunet hiubus: bus@ff63c000 { 9908c0cf40fSJerome Brunet compatible = "simple-bus"; 9918c0cf40fSJerome Brunet reg = <0x0 0xff63c000 0x0 0x1c00>; 9928c0cf40fSJerome Brunet #address-cells = <2>; 9938c0cf40fSJerome Brunet #size-cells = <2>; 9948c0cf40fSJerome Brunet ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>; 9958c0cf40fSJerome Brunet 9968c0cf40fSJerome Brunet sysctrl: system-controller@0 { 9978c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-hhi-sysctrl", 998445f2bdaSNeil Armstrong "simple-mfd", "syscon"; 9998c0cf40fSJerome Brunet reg = <0 0 0 0x400>; 10008c0cf40fSJerome Brunet 10018c0cf40fSJerome Brunet clkc: clock-controller { 10028c0cf40fSJerome Brunet compatible = "amlogic,axg-clkc"; 10038c0cf40fSJerome Brunet #clock-cells = <1>; 10048c0cf40fSJerome Brunet }; 10058c0cf40fSJerome Brunet }; 10068c0cf40fSJerome Brunet }; 10078c0cf40fSJerome Brunet 10089fdff382SJerome Brunet mailbox: mailbox@ff63c404 { 10098c0cf40fSJerome Brunet compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu"; 10109fdff382SJerome Brunet reg = <0 0xff63c404 0 0x4c>; 10118c0cf40fSJerome Brunet interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>, 10128c0cf40fSJerome Brunet <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>, 10138c0cf40fSJerome Brunet <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>; 10148c0cf40fSJerome Brunet #mbox-cells = <1>; 1015221cf34bSNan Li }; 1016221cf34bSNan Li 10178909e722SJerome Brunet audio: bus@ff642000 { 10188909e722SJerome Brunet compatible = "simple-bus"; 10198909e722SJerome Brunet reg = <0x0 0xff642000 0x0 0x2000>; 10208909e722SJerome Brunet #address-cells = <2>; 10218909e722SJerome Brunet #size-cells = <2>; 10228909e722SJerome Brunet ranges = <0x0 0x0 0x0 0xff642000 0x0 0x2000>; 10238909e722SJerome Brunet 10248909e722SJerome Brunet clkc_audio: clock-controller@0 { 10258909e722SJerome Brunet compatible = "amlogic,axg-audio-clkc"; 10268909e722SJerome Brunet reg = <0x0 0x0 0x0 0xb4>; 10278909e722SJerome Brunet #clock-cells = <1>; 10288909e722SJerome Brunet 10298909e722SJerome Brunet clocks = <&clkc CLKID_AUDIO>, 10308909e722SJerome Brunet <&clkc CLKID_MPLL0>, 10318909e722SJerome Brunet <&clkc CLKID_MPLL1>, 10328909e722SJerome Brunet <&clkc CLKID_MPLL2>, 10338909e722SJerome Brunet <&clkc CLKID_MPLL3>, 10348909e722SJerome Brunet <&clkc CLKID_HIFI_PLL>, 10358909e722SJerome Brunet <&clkc CLKID_FCLK_DIV3>, 10368909e722SJerome Brunet <&clkc CLKID_FCLK_DIV4>, 10378909e722SJerome Brunet <&clkc CLKID_GP0_PLL>; 10388909e722SJerome Brunet clock-names = "pclk", 10398909e722SJerome Brunet "mst_in0", 10408909e722SJerome Brunet "mst_in1", 10418909e722SJerome Brunet "mst_in2", 10428909e722SJerome Brunet "mst_in3", 10438909e722SJerome Brunet "mst_in4", 10448909e722SJerome Brunet "mst_in5", 10458909e722SJerome Brunet "mst_in6", 10468909e722SJerome Brunet "mst_in7"; 10478909e722SJerome Brunet 10488909e722SJerome Brunet resets = <&reset RESET_AUDIO>; 10498909e722SJerome Brunet }; 105066d58a8fSJerome Brunet 1051f2b8f6a9SJerome Brunet toddr_a: audio-controller@100 { 1052f2b8f6a9SJerome Brunet compatible = "amlogic,axg-toddr"; 1053f2b8f6a9SJerome Brunet reg = <0x0 0x100 0x0 0x1c>; 1054f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1055f2b8f6a9SJerome Brunet sound-name-prefix = "TODDR_A"; 1056f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>; 1057f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TODDR_A>; 1058f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_TODDR_A>; 1059f2b8f6a9SJerome Brunet status = "disabled"; 1060f2b8f6a9SJerome Brunet }; 1061f2b8f6a9SJerome Brunet 1062f2b8f6a9SJerome Brunet toddr_b: audio-controller@140 { 1063f2b8f6a9SJerome Brunet compatible = "amlogic,axg-toddr"; 1064f2b8f6a9SJerome Brunet reg = <0x0 0x140 0x0 0x1c>; 1065f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1066f2b8f6a9SJerome Brunet sound-name-prefix = "TODDR_B"; 1067f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>; 1068f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TODDR_B>; 1069f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_TODDR_B>; 1070f2b8f6a9SJerome Brunet status = "disabled"; 1071f2b8f6a9SJerome Brunet }; 1072f2b8f6a9SJerome Brunet 1073f2b8f6a9SJerome Brunet toddr_c: audio-controller@180 { 1074f2b8f6a9SJerome Brunet compatible = "amlogic,axg-toddr"; 1075f2b8f6a9SJerome Brunet reg = <0x0 0x180 0x0 0x1c>; 1076f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1077f2b8f6a9SJerome Brunet sound-name-prefix = "TODDR_C"; 1078f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>; 1079f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TODDR_C>; 1080f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_TODDR_C>; 1081f2b8f6a9SJerome Brunet status = "disabled"; 1082f2b8f6a9SJerome Brunet }; 1083f2b8f6a9SJerome Brunet 1084f2b8f6a9SJerome Brunet frddr_a: audio-controller@1c0 { 1085f2b8f6a9SJerome Brunet compatible = "amlogic,axg-frddr"; 1086f2b8f6a9SJerome Brunet reg = <0x0 0x1c0 0x0 0x1c>; 1087f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1088f2b8f6a9SJerome Brunet sound-name-prefix = "FRDDR_A"; 1089f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 1090f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_FRDDR_A>; 1091f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_FRDDR_A>; 1092f2b8f6a9SJerome Brunet status = "disabled"; 1093f2b8f6a9SJerome Brunet }; 1094f2b8f6a9SJerome Brunet 1095f2b8f6a9SJerome Brunet frddr_b: audio-controller@200 { 1096f2b8f6a9SJerome Brunet compatible = "amlogic,axg-frddr"; 1097f2b8f6a9SJerome Brunet reg = <0x0 0x200 0x0 0x1c>; 1098f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1099f2b8f6a9SJerome Brunet sound-name-prefix = "FRDDR_B"; 1100f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>; 1101f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_FRDDR_B>; 1102f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_FRDDR_B>; 1103f2b8f6a9SJerome Brunet status = "disabled"; 1104f2b8f6a9SJerome Brunet }; 1105f2b8f6a9SJerome Brunet 1106f2b8f6a9SJerome Brunet frddr_c: audio-controller@240 { 1107f2b8f6a9SJerome Brunet compatible = "amlogic,axg-frddr"; 1108f2b8f6a9SJerome Brunet reg = <0x0 0x240 0x0 0x1c>; 1109f2b8f6a9SJerome Brunet #sound-dai-cells = <0>; 1110f2b8f6a9SJerome Brunet sound-name-prefix = "FRDDR_C"; 1111f2b8f6a9SJerome Brunet interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; 1112f2b8f6a9SJerome Brunet clocks = <&clkc_audio AUD_CLKID_FRDDR_C>; 1113f2b8f6a9SJerome Brunet resets = <&arb AXG_ARB_FRDDR_C>; 1114f2b8f6a9SJerome Brunet status = "disabled"; 1115f2b8f6a9SJerome Brunet }; 1116f2b8f6a9SJerome Brunet 111766d58a8fSJerome Brunet arb: reset-controller@280 { 111866d58a8fSJerome Brunet compatible = "amlogic,meson-axg-audio-arb"; 111966d58a8fSJerome Brunet reg = <0x0 0x280 0x0 0x4>; 112066d58a8fSJerome Brunet #reset-cells = <1>; 112166d58a8fSJerome Brunet clocks = <&clkc_audio AUD_CLKID_DDR_ARB>; 112266d58a8fSJerome Brunet }; 1123f08c52deSJerome Brunet 1124bf8e4790SJerome Brunet tdmin_a: audio-controller@300 { 1125bf8e4790SJerome Brunet compatible = "amlogic,axg-tdmin"; 1126bf8e4790SJerome Brunet reg = <0x0 0x300 0x0 0x40>; 1127bf8e4790SJerome Brunet sound-name-prefix = "TDMIN_A"; 1128bf8e4790SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMIN_A>, 1129bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_A_SCLK>, 1130bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_A_SCLK_SEL>, 1131bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>, 1132bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_A_LRCLK>; 1133bf8e4790SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1134bf8e4790SJerome Brunet "lrclk", "lrclk_sel"; 1135bf8e4790SJerome Brunet status = "disabled"; 1136bf8e4790SJerome Brunet }; 1137bf8e4790SJerome Brunet 1138bf8e4790SJerome Brunet tdmin_b: audio-controller@340 { 1139bf8e4790SJerome Brunet compatible = "amlogic,axg-tdmin"; 1140bf8e4790SJerome Brunet reg = <0x0 0x340 0x0 0x40>; 1141bf8e4790SJerome Brunet sound-name-prefix = "TDMIN_B"; 1142bf8e4790SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMIN_B>, 1143bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_B_SCLK>, 1144bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_B_SCLK_SEL>, 1145bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>, 1146bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_B_LRCLK>; 1147bf8e4790SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1148bf8e4790SJerome Brunet "lrclk", "lrclk_sel"; 1149bf8e4790SJerome Brunet status = "disabled"; 1150bf8e4790SJerome Brunet }; 1151bf8e4790SJerome Brunet 1152bf8e4790SJerome Brunet tdmin_c: audio-controller@380 { 1153bf8e4790SJerome Brunet compatible = "amlogic,axg-tdmin"; 1154bf8e4790SJerome Brunet reg = <0x0 0x380 0x0 0x40>; 1155bf8e4790SJerome Brunet sound-name-prefix = "TDMIN_C"; 1156bf8e4790SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMIN_C>, 1157bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_C_SCLK>, 1158bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_C_SCLK_SEL>, 1159bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>, 1160bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_C_LRCLK>; 1161bf8e4790SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1162bf8e4790SJerome Brunet "lrclk", "lrclk_sel"; 1163bf8e4790SJerome Brunet status = "disabled"; 1164bf8e4790SJerome Brunet }; 1165bf8e4790SJerome Brunet 1166bf8e4790SJerome Brunet tdmin_lb: audio-controller@3c0 { 1167bf8e4790SJerome Brunet compatible = "amlogic,axg-tdmin"; 1168bf8e4790SJerome Brunet reg = <0x0 0x3c0 0x0 0x40>; 1169bf8e4790SJerome Brunet sound-name-prefix = "TDMIN_LB"; 1170bf8e4790SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMIN_LB>, 1171bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK>, 1172bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_LB_SCLK_SEL>, 1173bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>, 1174bf8e4790SJerome Brunet <&clkc_audio AUD_CLKID_TDMIN_LB_LRCLK>; 1175bf8e4790SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1176bf8e4790SJerome Brunet "lrclk", "lrclk_sel"; 1177bf8e4790SJerome Brunet status = "disabled"; 1178bf8e4790SJerome Brunet }; 1179bf8e4790SJerome Brunet 1180f08c52deSJerome Brunet spdifout: audio-controller@480 { 1181f08c52deSJerome Brunet compatible = "amlogic,axg-spdifout"; 1182f08c52deSJerome Brunet reg = <0x0 0x480 0x0 0x50>; 1183f08c52deSJerome Brunet #sound-dai-cells = <0>; 1184f08c52deSJerome Brunet sound-name-prefix = "SPDIFOUT"; 1185f08c52deSJerome Brunet clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>, 1186f08c52deSJerome Brunet <&clkc_audio AUD_CLKID_SPDIFOUT_CLK>; 1187f08c52deSJerome Brunet clock-names = "pclk", "mclk"; 1188f08c52deSJerome Brunet status = "disabled"; 1189f08c52deSJerome Brunet }; 1190fd916739SJerome Brunet 1191fd916739SJerome Brunet tdmout_a: audio-controller@500 { 1192fd916739SJerome Brunet compatible = "amlogic,axg-tdmout"; 1193fd916739SJerome Brunet reg = <0x0 0x500 0x0 0x40>; 1194fd916739SJerome Brunet sound-name-prefix = "TDMOUT_A"; 1195fd916739SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMOUT_A>, 1196fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK>, 1197fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_A_SCLK_SEL>, 1198fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>, 1199fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_A_LRCLK>; 1200fd916739SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1201fd916739SJerome Brunet "lrclk", "lrclk_sel"; 1202fd916739SJerome Brunet status = "disabled"; 1203fd916739SJerome Brunet }; 1204fd916739SJerome Brunet 1205fd916739SJerome Brunet tdmout_b: audio-controller@540 { 1206fd916739SJerome Brunet compatible = "amlogic,axg-tdmout"; 1207fd916739SJerome Brunet reg = <0x0 0x540 0x0 0x40>; 1208fd916739SJerome Brunet sound-name-prefix = "TDMOUT_B"; 1209fd916739SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMOUT_B>, 1210fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK>, 1211fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_B_SCLK_SEL>, 1212fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>, 1213fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_B_LRCLK>; 1214fd916739SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1215fd916739SJerome Brunet "lrclk", "lrclk_sel"; 1216fd916739SJerome Brunet status = "disabled"; 1217fd916739SJerome Brunet }; 1218fd916739SJerome Brunet 1219fd916739SJerome Brunet tdmout_c: audio-controller@580 { 1220fd916739SJerome Brunet compatible = "amlogic,axg-tdmout"; 1221fd916739SJerome Brunet reg = <0x0 0x580 0x0 0x40>; 1222fd916739SJerome Brunet sound-name-prefix = "TDMOUT_C"; 1223fd916739SJerome Brunet clocks = <&clkc_audio AUD_CLKID_TDMOUT_C>, 1224fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK>, 1225fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_C_SCLK_SEL>, 1226fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>, 1227fd916739SJerome Brunet <&clkc_audio AUD_CLKID_TDMOUT_C_LRCLK>; 1228fd916739SJerome Brunet clock-names = "pclk", "sclk", "sclk_sel", 1229fd916739SJerome Brunet "lrclk", "lrclk_sel"; 1230fd916739SJerome Brunet status = "disabled"; 1231fd916739SJerome Brunet }; 12328909e722SJerome Brunet }; 12338909e722SJerome Brunet 12340cb6c604SKevin Hilman aobus: bus@ff800000 { 12359d59b708SYixun Lan compatible = "simple-bus"; 12369d59b708SYixun Lan reg = <0x0 0xff800000 0x0 0x100000>; 12379d59b708SYixun Lan #address-cells = <2>; 12389d59b708SYixun Lan #size-cells = <2>; 12399d59b708SYixun Lan ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>; 12409d59b708SYixun Lan 1241e03421ecSQiufang Dai sysctrl_AO: sys-ctrl@0 { 1242445f2bdaSNeil Armstrong compatible = "amlogic,meson-axg-ao-sysctrl", "simple-mfd", "syscon"; 1243e03421ecSQiufang Dai reg = <0x0 0x0 0x0 0x100>; 1244e03421ecSQiufang Dai 1245e03421ecSQiufang Dai clkc_AO: clock-controller { 1246e03421ecSQiufang Dai compatible = "amlogic,meson-axg-aoclkc"; 1247e03421ecSQiufang Dai #clock-cells = <1>; 1248e03421ecSQiufang Dai #reset-cells = <1>; 1249e03421ecSQiufang Dai }; 1250e03421ecSQiufang Dai }; 1251e03421ecSQiufang Dai 1252de05ded6SXingyu Chen pinctrl_aobus: pinctrl@14 { 1253de05ded6SXingyu Chen compatible = "amlogic,meson-axg-aobus-pinctrl"; 1254de05ded6SXingyu Chen #address-cells = <2>; 1255de05ded6SXingyu Chen #size-cells = <2>; 1256de05ded6SXingyu Chen ranges; 1257de05ded6SXingyu Chen 1258de05ded6SXingyu Chen gpio_ao: bank@14 { 1259de05ded6SXingyu Chen reg = <0x0 0x00014 0x0 0x8>, 1260de05ded6SXingyu Chen <0x0 0x0002c 0x0 0x4>, 1261de05ded6SXingyu Chen <0x0 0x00024 0x0 0x8>; 1262de05ded6SXingyu Chen reg-names = "mux", "pull", "gpio"; 1263de05ded6SXingyu Chen gpio-controller; 1264de05ded6SXingyu Chen #gpio-cells = <2>; 1265de05ded6SXingyu Chen gpio-ranges = <&pinctrl_aobus 0 0 15>; 1266de05ded6SXingyu Chen }; 12677bd46a79SYixun Lan 1268c054b6c2SJerome Brunet i2c_ao_sck_4_pins: i2c_ao_sck_4 { 1269c054b6c2SJerome Brunet mux { 1270c054b6c2SJerome Brunet groups = "i2c_ao_sck_4"; 1271c054b6c2SJerome Brunet function = "i2c_ao"; 1272c054b6c2SJerome Brunet }; 1273c054b6c2SJerome Brunet }; 1274c054b6c2SJerome Brunet 1275c054b6c2SJerome Brunet i2c_ao_sck_8_pins: i2c_ao_sck_8 { 1276c054b6c2SJerome Brunet mux { 1277c054b6c2SJerome Brunet groups = "i2c_ao_sck_8"; 1278c054b6c2SJerome Brunet function = "i2c_ao"; 1279c054b6c2SJerome Brunet }; 1280c054b6c2SJerome Brunet }; 1281c054b6c2SJerome Brunet 1282c054b6c2SJerome Brunet i2c_ao_sck_10_pins: i2c_ao_sck_10 { 1283c054b6c2SJerome Brunet mux { 1284c054b6c2SJerome Brunet groups = "i2c_ao_sck_10"; 1285c054b6c2SJerome Brunet function = "i2c_ao"; 1286c054b6c2SJerome Brunet }; 1287c054b6c2SJerome Brunet }; 1288c054b6c2SJerome Brunet 1289c054b6c2SJerome Brunet i2c_ao_sda_5_pins: i2c_ao_sda_5 { 1290c054b6c2SJerome Brunet mux { 1291c054b6c2SJerome Brunet groups = "i2c_ao_sda_5"; 1292c054b6c2SJerome Brunet function = "i2c_ao"; 1293c054b6c2SJerome Brunet }; 1294c054b6c2SJerome Brunet }; 1295c054b6c2SJerome Brunet 1296c054b6c2SJerome Brunet i2c_ao_sda_9_pins: i2c_ao_sda_9 { 1297c054b6c2SJerome Brunet mux { 1298c054b6c2SJerome Brunet groups = "i2c_ao_sda_9"; 1299c054b6c2SJerome Brunet function = "i2c_ao"; 1300c054b6c2SJerome Brunet }; 1301c054b6c2SJerome Brunet }; 1302c054b6c2SJerome Brunet 1303c054b6c2SJerome Brunet i2c_ao_sda_11_pins: i2c_ao_sda_11 { 1304c054b6c2SJerome Brunet mux { 1305c054b6c2SJerome Brunet groups = "i2c_ao_sda_11"; 1306c054b6c2SJerome Brunet function = "i2c_ao"; 1307c054b6c2SJerome Brunet }; 1308c054b6c2SJerome Brunet }; 1309c054b6c2SJerome Brunet 13107bd46a79SYixun Lan remote_input_ao_pins: remote_input_ao { 13117bd46a79SYixun Lan mux { 13127bd46a79SYixun Lan groups = "remote_input_ao"; 13137bd46a79SYixun Lan function = "remote_input_ao"; 13147bd46a79SYixun Lan }; 13157bd46a79SYixun Lan }; 13164eae66a6SYixun Lan 13174eae66a6SYixun Lan uart_ao_a_pins: uart_ao_a { 13184eae66a6SYixun Lan mux { 13194eae66a6SYixun Lan groups = "uart_ao_tx_a", 13204eae66a6SYixun Lan "uart_ao_rx_a"; 13214eae66a6SYixun Lan function = "uart_ao_a"; 13224eae66a6SYixun Lan }; 13234eae66a6SYixun Lan }; 13244eae66a6SYixun Lan 13254eae66a6SYixun Lan uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts { 13264eae66a6SYixun Lan mux { 13274eae66a6SYixun Lan groups = "uart_ao_cts_a", 13284eae66a6SYixun Lan "uart_ao_rts_a"; 13294eae66a6SYixun Lan function = "uart_ao_a"; 13304eae66a6SYixun Lan }; 13314eae66a6SYixun Lan }; 13324eae66a6SYixun Lan 13334eae66a6SYixun Lan uart_ao_b_pins: uart_ao_b { 13344eae66a6SYixun Lan mux { 13354eae66a6SYixun Lan groups = "uart_ao_tx_b", 13364eae66a6SYixun Lan "uart_ao_rx_b"; 13374eae66a6SYixun Lan function = "uart_ao_b"; 13384eae66a6SYixun Lan }; 13394eae66a6SYixun Lan }; 13404eae66a6SYixun Lan 13414eae66a6SYixun Lan uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts { 13424eae66a6SYixun Lan mux { 13434eae66a6SYixun Lan groups = "uart_ao_cts_b", 13444eae66a6SYixun Lan "uart_ao_rts_b"; 13454eae66a6SYixun Lan function = "uart_ao_b"; 13464eae66a6SYixun Lan }; 13474eae66a6SYixun Lan }; 1348de05ded6SXingyu Chen }; 1349de05ded6SXingyu Chen 1350a04c18cbSJerome Brunet sec_AO: ao-secure@140 { 1351a04c18cbSJerome Brunet compatible = "amlogic,meson-gx-ao-secure", "syscon"; 1352a04c18cbSJerome Brunet reg = <0x0 0x140 0x0 0x140>; 1353a04c18cbSJerome Brunet amlogic,has-chip-id; 1354a04c18cbSJerome Brunet }; 1355a04c18cbSJerome Brunet 13564a81e5ddSJian Hu pwm_AO_cd: pwm@2000 { 1357b4ff05caSJerome Brunet compatible = "amlogic,meson-axg-ao-pwm"; 13584a81e5ddSJian Hu reg = <0x0 0x02000 0x0 0x20>; 13594a81e5ddSJian Hu #pwm-cells = <3>; 13604a81e5ddSJian Hu status = "disabled"; 13614a81e5ddSJian Hu }; 13624a81e5ddSJian Hu 13639d59b708SYixun Lan uart_AO: serial@3000 { 13649d59b708SYixun Lan compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 13659d59b708SYixun Lan reg = <0x0 0x3000 0x0 0x18>; 13669d59b708SYixun Lan interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>; 13679adda353SYixun Lan clocks = <&xtal>, <&clkc_AO CLKID_AO_UART1>, <&xtal>; 13689d59b708SYixun Lan clock-names = "xtal", "pclk", "baud"; 13699d59b708SYixun Lan status = "disabled"; 13709d59b708SYixun Lan }; 13719d59b708SYixun Lan 13729d59b708SYixun Lan uart_AO_B: serial@4000 { 13739d59b708SYixun Lan compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart"; 13749d59b708SYixun Lan reg = <0x0 0x4000 0x0 0x18>; 13759d59b708SYixun Lan interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 13769adda353SYixun Lan clocks = <&xtal>, <&clkc_AO CLKID_AO_UART2>, <&xtal>; 13779d59b708SYixun Lan clock-names = "xtal", "pclk", "baud"; 13789d59b708SYixun Lan status = "disabled"; 13799d59b708SYixun Lan }; 13807bd46a79SYixun Lan 13818c0cf40fSJerome Brunet i2c_AO: i2c@5000 { 13828c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-i2c"; 13838c0cf40fSJerome Brunet reg = <0x0 0x05000 0x0 0x20>; 13848c0cf40fSJerome Brunet interrupts = <GIC_SPI 195 IRQ_TYPE_EDGE_RISING>; 13858c0cf40fSJerome Brunet clocks = <&clkc CLKID_AO_I2C>; 13868c0cf40fSJerome Brunet #address-cells = <1>; 13878c0cf40fSJerome Brunet #size-cells = <0>; 13888c0cf40fSJerome Brunet status = "disabled"; 13898c0cf40fSJerome Brunet }; 13908c0cf40fSJerome Brunet 13918c0cf40fSJerome Brunet pwm_AO_ab: pwm@7000 { 13928c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-ao-pwm"; 13938c0cf40fSJerome Brunet reg = <0x0 0x07000 0x0 0x20>; 13948c0cf40fSJerome Brunet #pwm-cells = <3>; 13958c0cf40fSJerome Brunet status = "disabled"; 13968c0cf40fSJerome Brunet }; 13978c0cf40fSJerome Brunet 13987bd46a79SYixun Lan ir: ir@8000 { 13997bd46a79SYixun Lan compatible = "amlogic,meson-gxbb-ir"; 14007bd46a79SYixun Lan reg = <0x0 0x8000 0x0 0x20>; 14017bd46a79SYixun Lan interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>; 14027bd46a79SYixun Lan status = "disabled"; 14037bd46a79SYixun Lan }; 1404a51b74eaSXingyu Chen 1405a51b74eaSXingyu Chen saradc: adc@9000 { 1406a51b74eaSXingyu Chen compatible = "amlogic,meson-axg-saradc", 1407a51b74eaSXingyu Chen "amlogic,meson-saradc"; 1408a51b74eaSXingyu Chen reg = <0x0 0x9000 0x0 0x38>; 1409a51b74eaSXingyu Chen #io-channel-cells = <1>; 1410a51b74eaSXingyu Chen interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; 1411a51b74eaSXingyu Chen clocks = <&xtal>, 1412a51b74eaSXingyu Chen <&clkc_AO CLKID_AO_SAR_ADC>, 1413a51b74eaSXingyu Chen <&clkc_AO CLKID_AO_SAR_ADC_CLK>, 1414a51b74eaSXingyu Chen <&clkc_AO CLKID_AO_SAR_ADC_SEL>; 1415a51b74eaSXingyu Chen clock-names = "clkin", "core", "adc_clk", "adc_sel"; 1416a51b74eaSXingyu Chen status = "disabled"; 1417a51b74eaSXingyu Chen }; 14189d59b708SYixun Lan }; 14198c0cf40fSJerome Brunet 14208c0cf40fSJerome Brunet gic: interrupt-controller@ffc01000 { 14218c0cf40fSJerome Brunet compatible = "arm,gic-400"; 14228c0cf40fSJerome Brunet reg = <0x0 0xffc01000 0 0x1000>, 14238c0cf40fSJerome Brunet <0x0 0xffc02000 0 0x2000>, 14248c0cf40fSJerome Brunet <0x0 0xffc04000 0 0x2000>, 14258c0cf40fSJerome Brunet <0x0 0xffc06000 0 0x2000>; 14268c0cf40fSJerome Brunet interrupt-controller; 14278c0cf40fSJerome Brunet interrupts = <GIC_PPI 9 14288c0cf40fSJerome Brunet (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 14298c0cf40fSJerome Brunet #interrupt-cells = <3>; 14308c0cf40fSJerome Brunet #address-cells = <0>; 14318c0cf40fSJerome Brunet }; 14328c0cf40fSJerome Brunet 14338c0cf40fSJerome Brunet cbus: bus@ffd00000 { 14348c0cf40fSJerome Brunet compatible = "simple-bus"; 14358c0cf40fSJerome Brunet reg = <0x0 0xffd00000 0x0 0x25000>; 14368c0cf40fSJerome Brunet #address-cells = <2>; 14378c0cf40fSJerome Brunet #size-cells = <2>; 14388c0cf40fSJerome Brunet ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>; 14398c0cf40fSJerome Brunet 14408c0cf40fSJerome Brunet reset: reset-controller@1004 { 14418c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-reset"; 14428c0cf40fSJerome Brunet reg = <0x0 0x01004 0x0 0x9c>; 14438c0cf40fSJerome Brunet #reset-cells = <1>; 14448c0cf40fSJerome Brunet }; 14458c0cf40fSJerome Brunet 14468c0cf40fSJerome Brunet gpio_intc: interrupt-controller@f080 { 14478c0cf40fSJerome Brunet compatible = "amlogic,meson-gpio-intc"; 14488c0cf40fSJerome Brunet reg = <0x0 0xf080 0x0 0x10>; 14498c0cf40fSJerome Brunet interrupt-controller; 14508c0cf40fSJerome Brunet #interrupt-cells = <2>; 14518c0cf40fSJerome Brunet amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>; 14528c0cf40fSJerome Brunet status = "disabled"; 14538c0cf40fSJerome Brunet }; 14548c0cf40fSJerome Brunet 14558c0cf40fSJerome Brunet pwm_ab: pwm@1b000 { 14568c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-ee-pwm"; 14578c0cf40fSJerome Brunet reg = <0x0 0x1b000 0x0 0x20>; 14588c0cf40fSJerome Brunet #pwm-cells = <3>; 14598c0cf40fSJerome Brunet status = "disabled"; 14608c0cf40fSJerome Brunet }; 14618c0cf40fSJerome Brunet 14628c0cf40fSJerome Brunet pwm_cd: pwm@1a000 { 14638c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-ee-pwm"; 14648c0cf40fSJerome Brunet reg = <0x0 0x1a000 0x0 0x20>; 14658c0cf40fSJerome Brunet #pwm-cells = <3>; 14668c0cf40fSJerome Brunet status = "disabled"; 14678c0cf40fSJerome Brunet }; 14688c0cf40fSJerome Brunet 14698c0cf40fSJerome Brunet spicc0: spi@13000 { 14708c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-spicc"; 14718c0cf40fSJerome Brunet reg = <0x0 0x13000 0x0 0x3c>; 14728c0cf40fSJerome Brunet interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 14738c0cf40fSJerome Brunet clocks = <&clkc CLKID_SPICC0>; 14748c0cf40fSJerome Brunet clock-names = "core"; 14758c0cf40fSJerome Brunet #address-cells = <1>; 14768c0cf40fSJerome Brunet #size-cells = <0>; 14778c0cf40fSJerome Brunet status = "disabled"; 14788c0cf40fSJerome Brunet }; 14798c0cf40fSJerome Brunet 14808c0cf40fSJerome Brunet spicc1: spi@15000 { 14818c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-spicc"; 14828c0cf40fSJerome Brunet reg = <0x0 0x15000 0x0 0x3c>; 14838c0cf40fSJerome Brunet interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 14848c0cf40fSJerome Brunet clocks = <&clkc CLKID_SPICC1>; 14858c0cf40fSJerome Brunet clock-names = "core"; 14868c0cf40fSJerome Brunet #address-cells = <1>; 14878c0cf40fSJerome Brunet #size-cells = <0>; 14888c0cf40fSJerome Brunet status = "disabled"; 14898c0cf40fSJerome Brunet }; 14908c0cf40fSJerome Brunet 14918c0cf40fSJerome Brunet i2c3: i2c@1c000 { 14928c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-i2c"; 14938c0cf40fSJerome Brunet reg = <0x0 0x1c000 0x0 0x20>; 14948c0cf40fSJerome Brunet interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>; 14958c0cf40fSJerome Brunet clocks = <&clkc CLKID_I2C>; 14968c0cf40fSJerome Brunet #address-cells = <1>; 14978c0cf40fSJerome Brunet #size-cells = <0>; 14988c0cf40fSJerome Brunet status = "disabled"; 14998c0cf40fSJerome Brunet }; 15008c0cf40fSJerome Brunet 15018c0cf40fSJerome Brunet i2c2: i2c@1d000 { 15028c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-i2c"; 15038c0cf40fSJerome Brunet reg = <0x0 0x1d000 0x0 0x20>; 15048c0cf40fSJerome Brunet interrupts = <GIC_SPI 215 IRQ_TYPE_EDGE_RISING>; 15058c0cf40fSJerome Brunet clocks = <&clkc CLKID_I2C>; 15068c0cf40fSJerome Brunet #address-cells = <1>; 15078c0cf40fSJerome Brunet #size-cells = <0>; 15088c0cf40fSJerome Brunet status = "disabled"; 15098c0cf40fSJerome Brunet }; 15108c0cf40fSJerome Brunet 15118c0cf40fSJerome Brunet i2c1: i2c@1e000 { 15128c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-i2c"; 15138c0cf40fSJerome Brunet reg = <0x0 0x1e000 0x0 0x20>; 15148c0cf40fSJerome Brunet interrupts = <GIC_SPI 214 IRQ_TYPE_EDGE_RISING>; 15158c0cf40fSJerome Brunet clocks = <&clkc CLKID_I2C>; 15168c0cf40fSJerome Brunet #address-cells = <1>; 15178c0cf40fSJerome Brunet #size-cells = <0>; 15188c0cf40fSJerome Brunet status = "disabled"; 15198c0cf40fSJerome Brunet }; 15208c0cf40fSJerome Brunet 15218c0cf40fSJerome Brunet i2c0: i2c@1f000 { 15228c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-i2c"; 15238c0cf40fSJerome Brunet reg = <0x0 0x1f000 0x0 0x20>; 15248c0cf40fSJerome Brunet interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 15258c0cf40fSJerome Brunet clocks = <&clkc CLKID_I2C>; 15268c0cf40fSJerome Brunet #address-cells = <1>; 15278c0cf40fSJerome Brunet #size-cells = <0>; 15288c0cf40fSJerome Brunet status = "disabled"; 15298c0cf40fSJerome Brunet }; 15308c0cf40fSJerome Brunet 15318c0cf40fSJerome Brunet uart_B: serial@23000 { 15328c0cf40fSJerome Brunet compatible = "amlogic,meson-gx-uart"; 15338c0cf40fSJerome Brunet reg = <0x0 0x23000 0x0 0x18>; 15348c0cf40fSJerome Brunet interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; 15358c0cf40fSJerome Brunet status = "disabled"; 15368c0cf40fSJerome Brunet clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>; 15378c0cf40fSJerome Brunet clock-names = "xtal", "pclk", "baud"; 15388c0cf40fSJerome Brunet }; 15398c0cf40fSJerome Brunet 15408c0cf40fSJerome Brunet uart_A: serial@24000 { 15418c0cf40fSJerome Brunet compatible = "amlogic,meson-gx-uart"; 15428c0cf40fSJerome Brunet reg = <0x0 0x24000 0x0 0x18>; 15438c0cf40fSJerome Brunet interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 15448c0cf40fSJerome Brunet status = "disabled"; 15458c0cf40fSJerome Brunet clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>; 15468c0cf40fSJerome Brunet clock-names = "xtal", "pclk", "baud"; 15478c0cf40fSJerome Brunet }; 15488c0cf40fSJerome Brunet }; 15498c0cf40fSJerome Brunet 15508c0cf40fSJerome Brunet apb: bus@ffe00000 { 15518c0cf40fSJerome Brunet compatible = "simple-bus"; 15528c0cf40fSJerome Brunet reg = <0x0 0xffe00000 0x0 0x200000>; 15538c0cf40fSJerome Brunet #address-cells = <2>; 15548c0cf40fSJerome Brunet #size-cells = <2>; 15558c0cf40fSJerome Brunet ranges = <0x0 0x0 0x0 0xffe00000 0x0 0x200000>; 15568c0cf40fSJerome Brunet 15578c0cf40fSJerome Brunet sd_emmc_b: sd@5000 { 15588c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-mmc"; 15598c0cf40fSJerome Brunet reg = <0x0 0x5000 0x0 0x800>; 15608c0cf40fSJerome Brunet interrupts = <GIC_SPI 217 IRQ_TYPE_EDGE_RISING>; 15618c0cf40fSJerome Brunet status = "disabled"; 15628c0cf40fSJerome Brunet clocks = <&clkc CLKID_SD_EMMC_B>, 15638c0cf40fSJerome Brunet <&clkc CLKID_SD_EMMC_B_CLK0>, 15648c0cf40fSJerome Brunet <&clkc CLKID_FCLK_DIV2>; 15658c0cf40fSJerome Brunet clock-names = "core", "clkin0", "clkin1"; 15668c0cf40fSJerome Brunet resets = <&reset RESET_SD_EMMC_B>; 15678c0cf40fSJerome Brunet }; 15688c0cf40fSJerome Brunet 15698c0cf40fSJerome Brunet sd_emmc_c: mmc@7000 { 15708c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-mmc"; 15718c0cf40fSJerome Brunet reg = <0x0 0x7000 0x0 0x800>; 15728c0cf40fSJerome Brunet interrupts = <GIC_SPI 218 IRQ_TYPE_EDGE_RISING>; 15738c0cf40fSJerome Brunet status = "disabled"; 15748c0cf40fSJerome Brunet clocks = <&clkc CLKID_SD_EMMC_C>, 15758c0cf40fSJerome Brunet <&clkc CLKID_SD_EMMC_C_CLK0>, 15768c0cf40fSJerome Brunet <&clkc CLKID_FCLK_DIV2>; 15778c0cf40fSJerome Brunet clock-names = "core", "clkin0", "clkin1"; 15788c0cf40fSJerome Brunet resets = <&reset RESET_SD_EMMC_C>; 15798c0cf40fSJerome Brunet }; 15808c0cf40fSJerome Brunet }; 15818c0cf40fSJerome Brunet 15828c0cf40fSJerome Brunet sram: sram@fffc0000 { 15838c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-sram", "mmio-sram"; 15848c0cf40fSJerome Brunet reg = <0x0 0xfffc0000 0x0 0x20000>; 15858c0cf40fSJerome Brunet #address-cells = <1>; 15868c0cf40fSJerome Brunet #size-cells = <1>; 15878c0cf40fSJerome Brunet ranges = <0 0x0 0xfffc0000 0x20000>; 15888c0cf40fSJerome Brunet 15899c2d16bbSJerome Brunet cpu_scp_lpri: scp-shmem@13000 { 15908c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-scp-shmem"; 15918c0cf40fSJerome Brunet reg = <0x13000 0x400>; 15928c0cf40fSJerome Brunet }; 15938c0cf40fSJerome Brunet 15949c2d16bbSJerome Brunet cpu_scp_hpri: scp-shmem@13400 { 15958c0cf40fSJerome Brunet compatible = "amlogic,meson-axg-scp-shmem"; 15968c0cf40fSJerome Brunet reg = <0x13400 0x400>; 15978c0cf40fSJerome Brunet }; 15988c0cf40fSJerome Brunet }; 15998c0cf40fSJerome Brunet }; 16008c0cf40fSJerome Brunet 16018c0cf40fSJerome Brunet timer { 16028c0cf40fSJerome Brunet compatible = "arm,armv8-timer"; 16038c0cf40fSJerome Brunet interrupts = <GIC_PPI 13 16048c0cf40fSJerome Brunet (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 16058c0cf40fSJerome Brunet <GIC_PPI 14 16068c0cf40fSJerome Brunet (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 16078c0cf40fSJerome Brunet <GIC_PPI 11 16088c0cf40fSJerome Brunet (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 16098c0cf40fSJerome Brunet <GIC_PPI 10 16108c0cf40fSJerome Brunet (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 16118c0cf40fSJerome Brunet }; 16128c0cf40fSJerome Brunet 16138c0cf40fSJerome Brunet xtal: xtal-clk { 16148c0cf40fSJerome Brunet compatible = "fixed-clock"; 16158c0cf40fSJerome Brunet clock-frequency = <24000000>; 16168c0cf40fSJerome Brunet clock-output-names = "xtal"; 16178c0cf40fSJerome Brunet #clock-cells = <0>; 16189d59b708SYixun Lan }; 16199d59b708SYixun Lan}; 1620