1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2019 Amlogic, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/irq.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 compatible = "amlogic,a1"; 11 12 interrupt-parent = <&gic>; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 cpus { 17 #address-cells = <2>; 18 #size-cells = <0>; 19 20 cpu0: cpu@0 { 21 device_type = "cpu"; 22 compatible = "arm,cortex-a35"; 23 reg = <0x0 0x0>; 24 enable-method = "psci"; 25 next-level-cache = <&l2>; 26 }; 27 28 cpu1: cpu@1 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a35"; 31 reg = <0x0 0x1>; 32 enable-method = "psci"; 33 next-level-cache = <&l2>; 34 }; 35 36 l2: l2-cache0 { 37 compatible = "cache"; 38 }; 39 }; 40 41 psci { 42 compatible = "arm,psci-1.0"; 43 method = "smc"; 44 }; 45 46 reserved-memory { 47 #address-cells = <2>; 48 #size-cells = <2>; 49 ranges; 50 51 linux,cma { 52 compatible = "shared-dma-pool"; 53 reusable; 54 size = <0x0 0x800000>; 55 alignment = <0x0 0x400000>; 56 linux,cma-default; 57 }; 58 }; 59 60 sm: secure-monitor { 61 compatible = "amlogic,meson-gxbb-sm"; 62 }; 63 64 soc { 65 compatible = "simple-bus"; 66 #address-cells = <2>; 67 #size-cells = <2>; 68 ranges; 69 70 apb: bus@fe000000 { 71 compatible = "simple-bus"; 72 reg = <0x0 0xfe000000 0x0 0x1000000>; 73 #address-cells = <2>; 74 #size-cells = <2>; 75 ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>; 76 77 uart_AO: serial@1c00 { 78 compatible = "amlogic,meson-gx-uart", 79 "amlogic,meson-ao-uart"; 80 reg = <0x0 0x1c00 0x0 0x18>; 81 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 82 clocks = <&xtal>, <&xtal>, <&xtal>; 83 clock-names = "xtal", "pclk", "baud"; 84 status = "disabled"; 85 }; 86 87 uart_AO_B: serial@2000 { 88 compatible = "amlogic,meson-gx-uart", 89 "amlogic,meson-ao-uart"; 90 reg = <0x0 0x2000 0x0 0x18>; 91 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 92 clocks = <&xtal>, <&xtal>, <&xtal>; 93 clock-names = "xtal", "pclk", "baud"; 94 status = "disabled"; 95 }; 96 }; 97 98 gic: interrupt-controller@ff901000 { 99 compatible = "arm,gic-400"; 100 reg = <0x0 0xff901000 0x0 0x1000>, 101 <0x0 0xff902000 0x0 0x2000>, 102 <0x0 0xff904000 0x0 0x2000>, 103 <0x0 0xff906000 0x0 0x2000>; 104 interrupt-controller; 105 interrupts = <GIC_PPI 9 106 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 107 #interrupt-cells = <3>; 108 #address-cells = <0>; 109 }; 110 }; 111 112 timer { 113 compatible = "arm,armv8-timer"; 114 interrupts = <GIC_PPI 13 115 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 116 <GIC_PPI 14 117 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 118 <GIC_PPI 11 119 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>, 120 <GIC_PPI 10 121 (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>; 122 }; 123 124 xtal: xtal-clk { 125 compatible = "fixed-clock"; 126 clock-frequency = <24000000>; 127 clock-output-names = "xtal"; 128 #clock-cells = <0>; 129 }; 130}; 131