1*6f048cc7SXianwei Zhao// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*6f048cc7SXianwei Zhao/* 3*6f048cc7SXianwei Zhao * Copyright (c) 2023 Amlogic, Inc. All rights reserved. 4*6f048cc7SXianwei Zhao */ 5*6f048cc7SXianwei Zhao 6*6f048cc7SXianwei Zhao/dts-v1/; 7*6f048cc7SXianwei Zhao 8*6f048cc7SXianwei Zhao#include "amlogic-t7.dtsi" 9*6f048cc7SXianwei Zhao 10*6f048cc7SXianwei Zhao/ { 11*6f048cc7SXianwei Zhao model = "Amlogic A311D2 AN400 Development Board"; 12*6f048cc7SXianwei Zhao compatible = "amlogic,an400", "amlogic,a311d2", "amlogic,t7"; 13*6f048cc7SXianwei Zhao interrupt-parent = <&gic>; 14*6f048cc7SXianwei Zhao #address-cells = <2>; 15*6f048cc7SXianwei Zhao #size-cells = <2>; 16*6f048cc7SXianwei Zhao 17*6f048cc7SXianwei Zhao aliases { 18*6f048cc7SXianwei Zhao serial0 = &uart_a; 19*6f048cc7SXianwei Zhao }; 20*6f048cc7SXianwei Zhao 21*6f048cc7SXianwei Zhao memory@0 { 22*6f048cc7SXianwei Zhao device_type = "memory"; 23*6f048cc7SXianwei Zhao reg = <0x00000000 0x00000000 0x00000000 0xE0000000 24*6f048cc7SXianwei Zhao 0x00000001 0x00000000 0x00000000 0x20000000>; 25*6f048cc7SXianwei Zhao }; 26*6f048cc7SXianwei Zhao 27*6f048cc7SXianwei Zhao xtal: xtal-clk { 28*6f048cc7SXianwei Zhao compatible = "fixed-clock"; 29*6f048cc7SXianwei Zhao clock-frequency = <24000000>; 30*6f048cc7SXianwei Zhao clock-output-names = "xtal"; 31*6f048cc7SXianwei Zhao #clock-cells = <0>; 32*6f048cc7SXianwei Zhao }; 33*6f048cc7SXianwei Zhao}; 34*6f048cc7SXianwei Zhao 35*6f048cc7SXianwei Zhao&uart_a { 36*6f048cc7SXianwei Zhao clocks = <&xtal>, <&xtal>, <&xtal>; 37*6f048cc7SXianwei Zhao clock-names = "xtal", "pclk", "baud"; 38*6f048cc7SXianwei Zhao status = "okay"; 39*6f048cc7SXianwei Zhao}; 40