1/* 2 * Copyright Altera Corporation (C) 2015. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17/dts-v1/; 18#include <dt-bindings/reset/altr,rst-mgr-s10.h> 19#include <dt-bindings/gpio/gpio.h> 20#include <dt-bindings/clock/stratix10-clock.h> 21 22/ { 23 compatible = "altr,socfpga-stratix10"; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 compatible = "arm,cortex-a53", "arm,armv8"; 33 device_type = "cpu"; 34 enable-method = "psci"; 35 reg = <0x0>; 36 }; 37 38 cpu1: cpu@1 { 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 device_type = "cpu"; 41 enable-method = "psci"; 42 reg = <0x1>; 43 }; 44 45 cpu2: cpu@2 { 46 compatible = "arm,cortex-a53", "arm,armv8"; 47 device_type = "cpu"; 48 enable-method = "psci"; 49 reg = <0x2>; 50 }; 51 52 cpu3: cpu@3 { 53 compatible = "arm,cortex-a53", "arm,armv8"; 54 device_type = "cpu"; 55 enable-method = "psci"; 56 reg = <0x3>; 57 }; 58 }; 59 60 pmu { 61 compatible = "arm,armv8-pmuv3"; 62 interrupts = <0 120 8>, 63 <0 121 8>, 64 <0 122 8>, 65 <0 123 8>; 66 interrupt-affinity = <&cpu0>, 67 <&cpu1>, 68 <&cpu2>, 69 <&cpu3>; 70 interrupt-parent = <&intc>; 71 }; 72 73 psci { 74 compatible = "arm,psci-0.2"; 75 method = "smc"; 76 }; 77 78 intc: intc@fffc1000 { 79 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 80 #interrupt-cells = <3>; 81 interrupt-controller; 82 reg = <0x0 0xfffc1000 0x0 0x1000>, 83 <0x0 0xfffc2000 0x0 0x2000>, 84 <0x0 0xfffc4000 0x0 0x2000>, 85 <0x0 0xfffc6000 0x0 0x2000>; 86 }; 87 88 soc { 89 #address-cells = <1>; 90 #size-cells = <1>; 91 compatible = "simple-bus"; 92 device_type = "soc"; 93 interrupt-parent = <&intc>; 94 ranges = <0 0 0 0xffffffff>; 95 96 clkmgr: clock-controller@ffd10000 { 97 compatible = "intel,stratix10-clkmgr"; 98 reg = <0xffd10000 0x1000>; 99 #clock-cells = <1>; 100 }; 101 102 clocks { 103 cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 104 #clock-cells = <0>; 105 compatible = "fixed-clock"; 106 }; 107 108 cb_intosc_ls_clk: cb-intosc-ls-clk { 109 #clock-cells = <0>; 110 compatible = "fixed-clock"; 111 }; 112 113 f2s_free_clk: f2s-free-clk { 114 #clock-cells = <0>; 115 compatible = "fixed-clock"; 116 }; 117 118 osc1: osc1 { 119 #clock-cells = <0>; 120 compatible = "fixed-clock"; 121 }; 122 123 qspi_clk: qspi-clk { 124 #clock-cells = <0>; 125 compatible = "fixed-clock"; 126 clock-frequency = <200000000>; 127 }; 128 }; 129 130 gmac0: ethernet@ff800000 { 131 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 132 reg = <0xff800000 0x2000>; 133 interrupts = <0 90 4>; 134 interrupt-names = "macirq"; 135 mac-address = [00 00 00 00 00 00]; 136 resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 137 reset-names = "stmmaceth", "stmmaceth-ocp"; 138 clocks = <&clkmgr STRATIX10_EMAC0_CLK>; 139 clock-names = "stmmaceth"; 140 tx-fifo-depth = <16384>; 141 rx-fifo-depth = <16384>; 142 snps,multicast-filter-bins = <256>; 143 status = "disabled"; 144 }; 145 146 gmac1: ethernet@ff802000 { 147 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 148 reg = <0xff802000 0x2000>; 149 interrupts = <0 91 4>; 150 interrupt-names = "macirq"; 151 mac-address = [00 00 00 00 00 00]; 152 resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 153 reset-names = "stmmaceth", "stmmaceth-ocp"; 154 clocks = <&clkmgr STRATIX10_EMAC1_CLK>; 155 clock-names = "stmmaceth"; 156 tx-fifo-depth = <16384>; 157 rx-fifo-depth = <16384>; 158 snps,multicast-filter-bins = <256>; 159 status = "disabled"; 160 }; 161 162 gmac2: ethernet@ff804000 { 163 compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 164 reg = <0xff804000 0x2000>; 165 interrupts = <0 92 4>; 166 interrupt-names = "macirq"; 167 mac-address = [00 00 00 00 00 00]; 168 resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 169 reset-names = "stmmaceth", "stmmaceth-ocp"; 170 clocks = <&clkmgr STRATIX10_EMAC2_CLK>; 171 clock-names = "stmmaceth"; 172 tx-fifo-depth = <16384>; 173 rx-fifo-depth = <16384>; 174 snps,multicast-filter-bins = <256>; 175 status = "disabled"; 176 }; 177 178 gpio0: gpio@ffc03200 { 179 #address-cells = <1>; 180 #size-cells = <0>; 181 compatible = "snps,dw-apb-gpio"; 182 reg = <0xffc03200 0x100>; 183 resets = <&rst GPIO0_RESET>; 184 status = "disabled"; 185 186 porta: gpio-controller@0 { 187 compatible = "snps,dw-apb-gpio-port"; 188 gpio-controller; 189 #gpio-cells = <2>; 190 snps,nr-gpios = <24>; 191 reg = <0>; 192 interrupt-controller; 193 #interrupt-cells = <2>; 194 interrupts = <0 110 4>; 195 }; 196 }; 197 198 gpio1: gpio@ffc03300 { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 compatible = "snps,dw-apb-gpio"; 202 reg = <0xffc03300 0x100>; 203 resets = <&rst GPIO1_RESET>; 204 status = "disabled"; 205 206 portb: gpio-controller@0 { 207 compatible = "snps,dw-apb-gpio-port"; 208 gpio-controller; 209 #gpio-cells = <2>; 210 snps,nr-gpios = <24>; 211 reg = <0>; 212 interrupt-controller; 213 #interrupt-cells = <2>; 214 interrupts = <0 111 4>; 215 }; 216 }; 217 218 i2c0: i2c@ffc02800 { 219 #address-cells = <1>; 220 #size-cells = <0>; 221 compatible = "snps,designware-i2c"; 222 reg = <0xffc02800 0x100>; 223 interrupts = <0 103 4>; 224 resets = <&rst I2C0_RESET>; 225 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 226 status = "disabled"; 227 }; 228 229 i2c1: i2c@ffc02900 { 230 #address-cells = <1>; 231 #size-cells = <0>; 232 compatible = "snps,designware-i2c"; 233 reg = <0xffc02900 0x100>; 234 interrupts = <0 104 4>; 235 resets = <&rst I2C1_RESET>; 236 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 237 status = "disabled"; 238 }; 239 240 i2c2: i2c@ffc02a00 { 241 #address-cells = <1>; 242 #size-cells = <0>; 243 compatible = "snps,designware-i2c"; 244 reg = <0xffc02a00 0x100>; 245 interrupts = <0 105 4>; 246 resets = <&rst I2C2_RESET>; 247 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 248 status = "disabled"; 249 }; 250 251 i2c3: i2c@ffc02b00 { 252 #address-cells = <1>; 253 #size-cells = <0>; 254 compatible = "snps,designware-i2c"; 255 reg = <0xffc02b00 0x100>; 256 interrupts = <0 106 4>; 257 resets = <&rst I2C3_RESET>; 258 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 259 status = "disabled"; 260 }; 261 262 i2c4: i2c@ffc02c00 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 compatible = "snps,designware-i2c"; 266 reg = <0xffc02c00 0x100>; 267 interrupts = <0 107 4>; 268 resets = <&rst I2C4_RESET>; 269 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 270 status = "disabled"; 271 }; 272 273 mmc: dwmmc0@ff808000 { 274 #address-cells = <1>; 275 #size-cells = <0>; 276 compatible = "altr,socfpga-dw-mshc"; 277 reg = <0xff808000 0x1000>; 278 interrupts = <0 96 4>; 279 fifo-depth = <0x400>; 280 resets = <&rst SDMMC_RESET>; 281 reset-names = "reset"; 282 clocks = <&clkmgr STRATIX10_L4_MP_CLK>, 283 <&clkmgr STRATIX10_SDMMC_CLK>; 284 clock-names = "biu", "ciu"; 285 status = "disabled"; 286 }; 287 288 ocram: sram@ffe00000 { 289 compatible = "mmio-sram"; 290 reg = <0xffe00000 0x100000>; 291 }; 292 293 pdma: pdma@ffda0000 { 294 compatible = "arm,pl330", "arm,primecell"; 295 reg = <0xffda0000 0x1000>; 296 interrupts = <0 81 4>, 297 <0 82 4>, 298 <0 83 4>, 299 <0 84 4>, 300 <0 85 4>, 301 <0 86 4>, 302 <0 87 4>, 303 <0 88 4>, 304 <0 89 4>; 305 #dma-cells = <1>; 306 #dma-channels = <8>; 307 #dma-requests = <32>; 308 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 309 clock-names = "apb_pclk"; 310 }; 311 312 rst: rstmgr@ffd11000 { 313 #reset-cells = <1>; 314 compatible = "altr,rst-mgr"; 315 reg = <0xffd11000 0x1000>; 316 altr,modrst-offset = <0x20>; 317 }; 318 319 spi0: spi@ffda4000 { 320 compatible = "snps,dw-apb-ssi"; 321 #address-cells = <1>; 322 #size-cells = <0>; 323 reg = <0xffda4000 0x1000>; 324 interrupts = <0 99 4>; 325 resets = <&rst SPIM0_RESET>; 326 reg-io-width = <4>; 327 num-cs = <4>; 328 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 329 status = "disabled"; 330 }; 331 332 spi1: spi@ffda5000 { 333 compatible = "snps,dw-apb-ssi"; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 reg = <0xffda5000 0x1000>; 337 interrupts = <0 100 4>; 338 resets = <&rst SPIM1_RESET>; 339 reg-io-width = <4>; 340 num-cs = <4>; 341 clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 342 status = "disabled"; 343 }; 344 345 sysmgr: sysmgr@ffd12000 { 346 compatible = "altr,sys-mgr", "syscon"; 347 reg = <0xffd12000 0x228>; 348 }; 349 350 /* Local timer */ 351 timer { 352 compatible = "arm,armv8-timer"; 353 interrupts = <1 13 0xf08>, 354 <1 14 0xf08>, 355 <1 11 0xf08>, 356 <1 10 0xf08>; 357 }; 358 359 timer0: timer0@ffc03000 { 360 compatible = "snps,dw-apb-timer"; 361 interrupts = <0 113 4>; 362 reg = <0xffc03000 0x100>; 363 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 364 clock-names = "timer"; 365 }; 366 367 timer1: timer1@ffc03100 { 368 compatible = "snps,dw-apb-timer"; 369 interrupts = <0 114 4>; 370 reg = <0xffc03100 0x100>; 371 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 372 clock-names = "timer"; 373 }; 374 375 timer2: timer2@ffd00000 { 376 compatible = "snps,dw-apb-timer"; 377 interrupts = <0 115 4>; 378 reg = <0xffd00000 0x100>; 379 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 380 clock-names = "timer"; 381 }; 382 383 timer3: timer3@ffd00100 { 384 compatible = "snps,dw-apb-timer"; 385 interrupts = <0 116 4>; 386 reg = <0xffd00100 0x100>; 387 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 388 clock-names = "timer"; 389 }; 390 391 uart0: serial0@ffc02000 { 392 compatible = "snps,dw-apb-uart"; 393 reg = <0xffc02000 0x100>; 394 interrupts = <0 108 4>; 395 reg-shift = <2>; 396 reg-io-width = <4>; 397 resets = <&rst UART0_RESET>; 398 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 399 status = "disabled"; 400 }; 401 402 uart1: serial1@ffc02100 { 403 compatible = "snps,dw-apb-uart"; 404 reg = <0xffc02100 0x100>; 405 interrupts = <0 109 4>; 406 reg-shift = <2>; 407 reg-io-width = <4>; 408 resets = <&rst UART1_RESET>; 409 clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 410 status = "disabled"; 411 }; 412 413 usbphy0: usbphy@0 { 414 #phy-cells = <0>; 415 compatible = "usb-nop-xceiv"; 416 status = "okay"; 417 }; 418 419 usb0: usb@ffb00000 { 420 compatible = "snps,dwc2"; 421 reg = <0xffb00000 0x40000>; 422 interrupts = <0 93 4>; 423 phys = <&usbphy0>; 424 phy-names = "usb2-phy"; 425 resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 426 reset-names = "dwc2", "dwc2-ecc"; 427 clocks = <&clkmgr STRATIX10_USB_CLK>; 428 status = "disabled"; 429 }; 430 431 usb1: usb@ffb40000 { 432 compatible = "snps,dwc2"; 433 reg = <0xffb40000 0x40000>; 434 interrupts = <0 94 4>; 435 phys = <&usbphy0>; 436 phy-names = "usb2-phy"; 437 resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 438 reset-names = "dwc2", "dwc2-ecc"; 439 clocks = <&clkmgr STRATIX10_USB_CLK>; 440 status = "disabled"; 441 }; 442 443 watchdog0: watchdog@ffd00200 { 444 compatible = "snps,dw-wdt"; 445 reg = <0xffd00200 0x100>; 446 interrupts = <0 117 4>; 447 resets = <&rst WATCHDOG0_RESET>; 448 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 449 status = "disabled"; 450 }; 451 452 watchdog1: watchdog@ffd00300 { 453 compatible = "snps,dw-wdt"; 454 reg = <0xffd00300 0x100>; 455 interrupts = <0 118 4>; 456 resets = <&rst WATCHDOG1_RESET>; 457 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 458 status = "disabled"; 459 }; 460 461 watchdog2: watchdog@ffd00400 { 462 compatible = "snps,dw-wdt"; 463 reg = <0xffd00400 0x100>; 464 interrupts = <0 125 4>; 465 resets = <&rst WATCHDOG2_RESET>; 466 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 467 status = "disabled"; 468 }; 469 470 watchdog3: watchdog@ffd00500 { 471 compatible = "snps,dw-wdt"; 472 reg = <0xffd00500 0x100>; 473 interrupts = <0 126 4>; 474 resets = <&rst WATCHDOG3_RESET>; 475 clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 476 status = "disabled"; 477 }; 478 479 sdr: sdr@f8011100 { 480 compatible = "altr,sdr-ctl", "syscon"; 481 reg = <0xf8011100 0xc0>; 482 }; 483 484 eccmgr { 485 compatible = "altr,socfpga-a10-ecc-manager"; 486 altr,sysmgr-syscon = <&sysmgr>; 487 #address-cells = <1>; 488 #size-cells = <1>; 489 interrupts = <0 15 4>, <0 95 4>; 490 interrupt-controller; 491 #interrupt-cells = <2>; 492 ranges; 493 494 sdramedac { 495 compatible = "altr,sdram-edac-s10"; 496 altr,sdr-syscon = <&sdr>; 497 interrupts = <16 4>, <48 4>; 498 }; 499 500 usb0-ecc@ff8c4000 { 501 compatible = "altr,socfpga-usb-ecc"; 502 reg = <0xff8c4000 0x100>; 503 altr,ecc-parent = <&usb0>; 504 interrupts = <2 4>, 505 <34 4>; 506 }; 507 508 emac0-rx-ecc@ff8c0000 { 509 compatible = "altr,socfpga-eth-mac-ecc"; 510 reg = <0xff8c0000 0x100>; 511 altr,ecc-parent = <&gmac0>; 512 interrupts = <4 4>, 513 <36 4>; 514 }; 515 516 emac0-tx-ecc@ff8c0400 { 517 compatible = "altr,socfpga-eth-mac-ecc"; 518 reg = <0xff8c0400 0x100>; 519 altr,ecc-parent = <&gmac0>; 520 interrupts = <5 4>, 521 <37 4>; 522 }; 523 524 }; 525 526 qspi: spi@ff8d2000 { 527 compatible = "cdns,qspi-nor"; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 reg = <0xff8d2000 0x100>, 531 <0xff900000 0x100000>; 532 interrupts = <0 3 4>; 533 cdns,fifo-depth = <128>; 534 cdns,fifo-width = <4>; 535 cdns,trigger-address = <0x00000000>; 536 clocks = <&qspi_clk>; 537 538 status = "disabled"; 539 }; 540 }; 541}; 542