1/*
2 * Copyright Altera Corporation (C) 2015. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18#include <dt-bindings/reset/altr,rst-mgr-s10.h>
19#include <dt-bindings/gpio/gpio.h>
20#include <dt-bindings/clock/stratix10-clock.h>
21
22/ {
23	compatible = "altr,socfpga-stratix10";
24	#address-cells = <2>;
25	#size-cells = <2>;
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu0: cpu@0 {
32			compatible = "arm,cortex-a53", "arm,armv8";
33			device_type = "cpu";
34			enable-method = "psci";
35			reg = <0x0>;
36		};
37
38		cpu1: cpu@1 {
39			compatible = "arm,cortex-a53", "arm,armv8";
40			device_type = "cpu";
41			enable-method = "psci";
42			reg = <0x1>;
43		};
44
45		cpu2: cpu@2 {
46			compatible = "arm,cortex-a53", "arm,armv8";
47			device_type = "cpu";
48			enable-method = "psci";
49			reg = <0x2>;
50		};
51
52		cpu3: cpu@3 {
53			compatible = "arm,cortex-a53", "arm,armv8";
54			device_type = "cpu";
55			enable-method = "psci";
56			reg = <0x3>;
57		};
58	};
59
60	pmu {
61		compatible = "arm,armv8-pmuv3";
62		interrupts = <0 120 8>,
63			     <0 121 8>,
64			     <0 122 8>,
65			     <0 123 8>;
66		interrupt-affinity = <&cpu0>,
67				     <&cpu1>,
68				     <&cpu2>,
69				     <&cpu3>;
70		interrupt-parent = <&intc>;
71	};
72
73	psci {
74		compatible = "arm,psci-0.2";
75		method = "smc";
76	};
77
78	intc: intc@fffc1000 {
79		compatible = "arm,gic-400", "arm,cortex-a15-gic";
80		#interrupt-cells = <3>;
81		interrupt-controller;
82		reg = <0x0 0xfffc1000 0x0 0x1000>,
83		      <0x0 0xfffc2000 0x0 0x2000>,
84		      <0x0 0xfffc4000 0x0 0x2000>,
85		      <0x0 0xfffc6000 0x0 0x2000>;
86	};
87
88	soc {
89		#address-cells = <1>;
90		#size-cells = <1>;
91		compatible = "simple-bus";
92		device_type = "soc";
93		interrupt-parent = <&intc>;
94		ranges = <0 0 0 0xffffffff>;
95
96		clkmgr: clock-controller@ffd10000 {
97			compatible = "intel,stratix10-clkmgr";
98			reg = <0xffd10000 0x1000>;
99			#clock-cells = <1>;
100		};
101
102		clocks {
103			cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
104				#clock-cells = <0>;
105				compatible = "fixed-clock";
106			};
107
108			cb_intosc_ls_clk: cb-intosc-ls-clk {
109				#clock-cells = <0>;
110				compatible = "fixed-clock";
111			};
112
113			f2s_free_clk: f2s-free-clk {
114				#clock-cells = <0>;
115				compatible = "fixed-clock";
116			};
117
118			osc1: osc1 {
119				#clock-cells = <0>;
120				compatible = "fixed-clock";
121			};
122		};
123
124		gmac0: ethernet@ff800000 {
125			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
126			reg = <0xff800000 0x2000>;
127			interrupts = <0 90 4>;
128			interrupt-names = "macirq";
129			mac-address = [00 00 00 00 00 00];
130			resets = <&rst EMAC0_RESET>;
131			reset-names = "stmmaceth";
132			clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
133			clock-names = "stmmaceth";
134			status = "disabled";
135		};
136
137		gmac1: ethernet@ff802000 {
138			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
139			reg = <0xff802000 0x2000>;
140			interrupts = <0 91 4>;
141			interrupt-names = "macirq";
142			mac-address = [00 00 00 00 00 00];
143			resets = <&rst EMAC1_RESET>;
144			reset-names = "stmmaceth";
145			clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
146			clock-names = "stmmaceth";
147			status = "disabled";
148		};
149
150		gmac2: ethernet@ff804000 {
151			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
152			reg = <0xff804000 0x2000>;
153			interrupts = <0 92 4>;
154			interrupt-names = "macirq";
155			mac-address = [00 00 00 00 00 00];
156			resets = <&rst EMAC2_RESET>;
157			reset-names = "stmmaceth";
158			clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
159			clock-names = "stmmaceth";
160			status = "disabled";
161		};
162
163		gpio0: gpio@ffc03200 {
164			#address-cells = <1>;
165			#size-cells = <0>;
166			compatible = "snps,dw-apb-gpio";
167			reg = <0xffc03200 0x100>;
168			resets = <&rst GPIO0_RESET>;
169			status = "disabled";
170
171			porta: gpio-controller@0 {
172				compatible = "snps,dw-apb-gpio-port";
173				gpio-controller;
174				#gpio-cells = <2>;
175				snps,nr-gpios = <24>;
176				reg = <0>;
177				interrupt-controller;
178				#interrupt-cells = <2>;
179				interrupts = <0 110 4>;
180			};
181		};
182
183		gpio1: gpio@ffc03300 {
184			#address-cells = <1>;
185			#size-cells = <0>;
186			compatible = "snps,dw-apb-gpio";
187			reg = <0xffc03300 0x100>;
188			resets = <&rst GPIO1_RESET>;
189			status = "disabled";
190
191			portb: gpio-controller@0 {
192				compatible = "snps,dw-apb-gpio-port";
193				gpio-controller;
194				#gpio-cells = <2>;
195				snps,nr-gpios = <24>;
196				reg = <0>;
197				interrupt-controller;
198				#interrupt-cells = <2>;
199				interrupts = <0 111 4>;
200			};
201		};
202
203		i2c0: i2c@ffc02800 {
204			#address-cells = <1>;
205			#size-cells = <0>;
206			compatible = "snps,designware-i2c";
207			reg = <0xffc02800 0x100>;
208			interrupts = <0 103 4>;
209			resets = <&rst I2C0_RESET>;
210			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
211			status = "disabled";
212		};
213
214		i2c1: i2c@ffc02900 {
215			#address-cells = <1>;
216			#size-cells = <0>;
217			compatible = "snps,designware-i2c";
218			reg = <0xffc02900 0x100>;
219			interrupts = <0 104 4>;
220			resets = <&rst I2C1_RESET>;
221			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
222			status = "disabled";
223		};
224
225		i2c2: i2c@ffc02a00 {
226			#address-cells = <1>;
227			#size-cells = <0>;
228			compatible = "snps,designware-i2c";
229			reg = <0xffc02a00 0x100>;
230			interrupts = <0 105 4>;
231			resets = <&rst I2C2_RESET>;
232			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
233			status = "disabled";
234		};
235
236		i2c3: i2c@ffc02b00 {
237			#address-cells = <1>;
238			#size-cells = <0>;
239			compatible = "snps,designware-i2c";
240			reg = <0xffc02b00 0x100>;
241			interrupts = <0 106 4>;
242			resets = <&rst I2C3_RESET>;
243			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
244			status = "disabled";
245		};
246
247		i2c4: i2c@ffc02c00 {
248			#address-cells = <1>;
249			#size-cells = <0>;
250			compatible = "snps,designware-i2c";
251			reg = <0xffc02c00 0x100>;
252			interrupts = <0 107 4>;
253			resets = <&rst I2C4_RESET>;
254			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
255			status = "disabled";
256		};
257
258		mmc: dwmmc0@ff808000 {
259			#address-cells = <1>;
260			#size-cells = <0>;
261			compatible = "altr,socfpga-dw-mshc";
262			reg = <0xff808000 0x1000>;
263			interrupts = <0 96 4>;
264			fifo-depth = <0x400>;
265			resets = <&rst SDMMC_RESET>;
266			reset-names = "reset";
267			clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
268				 <&clkmgr STRATIX10_SDMMC_CLK>;
269			clock-names = "biu", "ciu";
270			status = "disabled";
271		};
272
273		ocram: sram@ffe00000 {
274			compatible = "mmio-sram";
275			reg = <0xffe00000 0x100000>;
276		};
277
278		pdma: pdma@ffda0000 {
279			compatible = "arm,pl330", "arm,primecell";
280			reg = <0xffda0000 0x1000>;
281			interrupts = <0 81 4>,
282				     <0 82 4>,
283				     <0 83 4>,
284				     <0 84 4>,
285				     <0 85 4>,
286				     <0 86 4>,
287				     <0 87 4>,
288				     <0 88 4>,
289				     <0 89 4>;
290			#dma-cells = <1>;
291			#dma-channels = <8>;
292			#dma-requests = <32>;
293			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
294			clock-names = "apb_pclk";
295		};
296
297		rst: rstmgr@ffd11000 {
298			#reset-cells = <1>;
299			compatible = "altr,rst-mgr";
300			reg = <0xffd11000 0x1000>;
301			altr,modrst-offset = <0x20>;
302		};
303
304		spi0: spi@ffda4000 {
305			compatible = "snps,dw-apb-ssi";
306			#address-cells = <1>;
307			#size-cells = <0>;
308			reg = <0xffda4000 0x1000>;
309			interrupts = <0 99 4>;
310			resets = <&rst SPIM0_RESET>;
311			reg-io-width = <4>;
312			num-cs = <4>;
313			status = "disabled";
314		};
315
316		spi1: spi@ffda5000 {
317			compatible = "snps,dw-apb-ssi";
318			#address-cells = <1>;
319			#size-cells = <0>;
320			reg = <0xffda5000 0x1000>;
321			interrupts = <0 100 4>;
322			resets = <&rst SPIM1_RESET>;
323			reg-io-width = <4>;
324			num-cs = <4>;
325			status = "disabled";
326		};
327
328		sysmgr: sysmgr@ffd12000 {
329			compatible = "altr,sys-mgr", "syscon";
330			reg = <0xffd12000 0x1000>;
331		};
332
333		/* Local timer */
334		timer {
335			compatible = "arm,armv8-timer";
336			interrupts = <1 13 0xf08>,
337				     <1 14 0xf08>,
338				     <1 11 0xf08>,
339				     <1 10 0xf08>;
340		};
341
342		timer0: timer0@ffc03000 {
343			compatible = "snps,dw-apb-timer";
344			interrupts = <0 113 4>;
345			reg = <0xffc03000 0x100>;
346			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
347			clock-names = "timer";
348		};
349
350		timer1: timer1@ffc03100 {
351			compatible = "snps,dw-apb-timer";
352			interrupts = <0 114 4>;
353			reg = <0xffc03100 0x100>;
354			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
355			clock-names = "timer";
356		};
357
358		timer2: timer2@ffd00000 {
359			compatible = "snps,dw-apb-timer";
360			interrupts = <0 115 4>;
361			reg = <0xffd00000 0x100>;
362			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
363			clock-names = "timer";
364		};
365
366		timer3: timer3@ffd00100 {
367			compatible = "snps,dw-apb-timer";
368			interrupts = <0 116 4>;
369			reg = <0xffd00100 0x100>;
370			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
371			clock-names = "timer";
372		};
373
374		uart0: serial0@ffc02000 {
375			compatible = "snps,dw-apb-uart";
376			reg = <0xffc02000 0x100>;
377			interrupts = <0 108 4>;
378			reg-shift = <2>;
379			reg-io-width = <4>;
380			resets = <&rst UART0_RESET>;
381			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
382			status = "disabled";
383		};
384
385		uart1: serial1@ffc02100 {
386			compatible = "snps,dw-apb-uart";
387			reg = <0xffc02100 0x100>;
388			interrupts = <0 109 4>;
389			reg-shift = <2>;
390			reg-io-width = <4>;
391			resets = <&rst UART1_RESET>;
392			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
393			status = "disabled";
394		};
395
396		usbphy0: usbphy@0 {
397			#phy-cells = <0>;
398			compatible = "usb-nop-xceiv";
399			status = "okay";
400		};
401
402		usb0: usb@ffb00000 {
403			compatible = "snps,dwc2";
404			reg = <0xffb00000 0x40000>;
405			interrupts = <0 93 4>;
406			phys = <&usbphy0>;
407			phy-names = "usb2-phy";
408			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
409			reset-names = "dwc2", "dwc2-ecc";
410			status = "disabled";
411		};
412
413		usb1: usb@ffb40000 {
414			compatible = "snps,dwc2";
415			reg = <0xffb40000 0x40000>;
416			interrupts = <0 94 4>;
417			phys = <&usbphy0>;
418			phy-names = "usb2-phy";
419			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
420			reset-names = "dwc2", "dwc2-ecc";
421			status = "disabled";
422		};
423
424		watchdog0: watchdog@ffd00200 {
425			compatible = "snps,dw-wdt";
426			reg = <0xffd00200 0x100>;
427			interrupts = <0 117 4>;
428			resets = <&rst WATCHDOG0_RESET>;
429			status = "disabled";
430		};
431
432		watchdog1: watchdog@ffd00300 {
433			compatible = "snps,dw-wdt";
434			reg = <0xffd00300 0x100>;
435			interrupts = <0 118 4>;
436			resets = <&rst WATCHDOG1_RESET>;
437			status = "disabled";
438		};
439
440		watchdog2: watchdog@ffd00400 {
441			compatible = "snps,dw-wdt";
442			reg = <0xffd00400 0x100>;
443			interrupts = <0 125 4>;
444			resets = <&rst WATCHDOG2_RESET>;
445			status = "disabled";
446		};
447
448		watchdog3: watchdog@ffd00500 {
449			compatible = "snps,dw-wdt";
450			reg = <0xffd00500 0x100>;
451			interrupts = <0 126 4>;
452			resets = <&rst WATCHDOG3_RESET>;
453			status = "disabled";
454		};
455
456		eccmgr {
457			compatible = "altr,socfpga-s10-ecc-manager";
458			interrupts = <0 15 4>, <0 95 4>;
459			interrupt-controller;
460			#interrupt-cells = <2>;
461
462			sdramedac {
463				compatible = "altr,sdram-edac-s10";
464				interrupts = <16 4>, <48 4>;
465			};
466		};
467	};
468};
469