1/*
2 * Copyright Altera Corporation (C) 2015. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18#include <dt-bindings/reset/altr,rst-mgr-s10.h>
19#include <dt-bindings/gpio/gpio.h>
20#include <dt-bindings/clock/stratix10-clock.h>
21
22/ {
23	compatible = "altr,socfpga-stratix10";
24	#address-cells = <2>;
25	#size-cells = <2>;
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu0: cpu@0 {
32			compatible = "arm,cortex-a53", "arm,armv8";
33			device_type = "cpu";
34			enable-method = "psci";
35			reg = <0x0>;
36		};
37
38		cpu1: cpu@1 {
39			compatible = "arm,cortex-a53", "arm,armv8";
40			device_type = "cpu";
41			enable-method = "psci";
42			reg = <0x1>;
43		};
44
45		cpu2: cpu@2 {
46			compatible = "arm,cortex-a53", "arm,armv8";
47			device_type = "cpu";
48			enable-method = "psci";
49			reg = <0x2>;
50		};
51
52		cpu3: cpu@3 {
53			compatible = "arm,cortex-a53", "arm,armv8";
54			device_type = "cpu";
55			enable-method = "psci";
56			reg = <0x3>;
57		};
58	};
59
60	pmu {
61		compatible = "arm,armv8-pmuv3";
62		interrupts = <0 120 8>,
63			     <0 121 8>,
64			     <0 122 8>,
65			     <0 123 8>;
66		interrupt-affinity = <&cpu0>,
67				     <&cpu1>,
68				     <&cpu2>,
69				     <&cpu3>;
70		interrupt-parent = <&intc>;
71	};
72
73	psci {
74		compatible = "arm,psci-0.2";
75		method = "smc";
76	};
77
78	intc: intc@fffc1000 {
79		compatible = "arm,gic-400", "arm,cortex-a15-gic";
80		#interrupt-cells = <3>;
81		interrupt-controller;
82		reg = <0x0 0xfffc1000 0x0 0x1000>,
83		      <0x0 0xfffc2000 0x0 0x2000>,
84		      <0x0 0xfffc4000 0x0 0x2000>,
85		      <0x0 0xfffc6000 0x0 0x2000>;
86	};
87
88	soc {
89		#address-cells = <1>;
90		#size-cells = <1>;
91		compatible = "simple-bus";
92		device_type = "soc";
93		interrupt-parent = <&intc>;
94		ranges = <0 0 0 0xffffffff>;
95
96		clkmgr: clock-controller@ffd10000 {
97			compatible = "intel,stratix10-clkmgr";
98			reg = <0xffd10000 0x1000>;
99			#clock-cells = <1>;
100		};
101
102		clocks {
103			cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
104				#clock-cells = <0>;
105				compatible = "fixed-clock";
106			};
107
108			cb_intosc_ls_clk: cb-intosc-ls-clk {
109				#clock-cells = <0>;
110				compatible = "fixed-clock";
111			};
112
113			f2s_free_clk: f2s-free-clk {
114				#clock-cells = <0>;
115				compatible = "fixed-clock";
116			};
117
118			osc1: osc1 {
119				#clock-cells = <0>;
120				compatible = "fixed-clock";
121			};
122
123			qspi_clk: qspi-clk {
124				#clock-cells = <0>;
125				compatible = "fixed-clock";
126				clock-frequency = <200000000>;
127			};
128		};
129
130		gmac0: ethernet@ff800000 {
131			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
132			reg = <0xff800000 0x2000>;
133			interrupts = <0 90 4>;
134			interrupt-names = "macirq";
135			mac-address = [00 00 00 00 00 00];
136			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
137			reset-names = "stmmaceth", "stmmaceth-ocp";
138			clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
139			clock-names = "stmmaceth";
140			tx-fifo-depth = <16384>;
141			rx-fifo-depth = <16384>;
142			status = "disabled";
143		};
144
145		gmac1: ethernet@ff802000 {
146			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
147			reg = <0xff802000 0x2000>;
148			interrupts = <0 91 4>;
149			interrupt-names = "macirq";
150			mac-address = [00 00 00 00 00 00];
151			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
152			reset-names = "stmmaceth", "stmmaceth-ocp";
153			clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
154			clock-names = "stmmaceth";
155			tx-fifo-depth = <16384>;
156			rx-fifo-depth = <16384>;
157			status = "disabled";
158		};
159
160		gmac2: ethernet@ff804000 {
161			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
162			reg = <0xff804000 0x2000>;
163			interrupts = <0 92 4>;
164			interrupt-names = "macirq";
165			mac-address = [00 00 00 00 00 00];
166			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
167			reset-names = "stmmaceth", "stmmaceth-ocp";
168			clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
169			clock-names = "stmmaceth";
170			tx-fifo-depth = <16384>;
171			rx-fifo-depth = <16384>;
172			status = "disabled";
173		};
174
175		gpio0: gpio@ffc03200 {
176			#address-cells = <1>;
177			#size-cells = <0>;
178			compatible = "snps,dw-apb-gpio";
179			reg = <0xffc03200 0x100>;
180			resets = <&rst GPIO0_RESET>;
181			status = "disabled";
182
183			porta: gpio-controller@0 {
184				compatible = "snps,dw-apb-gpio-port";
185				gpio-controller;
186				#gpio-cells = <2>;
187				snps,nr-gpios = <24>;
188				reg = <0>;
189				interrupt-controller;
190				#interrupt-cells = <2>;
191				interrupts = <0 110 4>;
192			};
193		};
194
195		gpio1: gpio@ffc03300 {
196			#address-cells = <1>;
197			#size-cells = <0>;
198			compatible = "snps,dw-apb-gpio";
199			reg = <0xffc03300 0x100>;
200			resets = <&rst GPIO1_RESET>;
201			status = "disabled";
202
203			portb: gpio-controller@0 {
204				compatible = "snps,dw-apb-gpio-port";
205				gpio-controller;
206				#gpio-cells = <2>;
207				snps,nr-gpios = <24>;
208				reg = <0>;
209				interrupt-controller;
210				#interrupt-cells = <2>;
211				interrupts = <0 111 4>;
212			};
213		};
214
215		i2c0: i2c@ffc02800 {
216			#address-cells = <1>;
217			#size-cells = <0>;
218			compatible = "snps,designware-i2c";
219			reg = <0xffc02800 0x100>;
220			interrupts = <0 103 4>;
221			resets = <&rst I2C0_RESET>;
222			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
223			status = "disabled";
224		};
225
226		i2c1: i2c@ffc02900 {
227			#address-cells = <1>;
228			#size-cells = <0>;
229			compatible = "snps,designware-i2c";
230			reg = <0xffc02900 0x100>;
231			interrupts = <0 104 4>;
232			resets = <&rst I2C1_RESET>;
233			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
234			status = "disabled";
235		};
236
237		i2c2: i2c@ffc02a00 {
238			#address-cells = <1>;
239			#size-cells = <0>;
240			compatible = "snps,designware-i2c";
241			reg = <0xffc02a00 0x100>;
242			interrupts = <0 105 4>;
243			resets = <&rst I2C2_RESET>;
244			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
245			status = "disabled";
246		};
247
248		i2c3: i2c@ffc02b00 {
249			#address-cells = <1>;
250			#size-cells = <0>;
251			compatible = "snps,designware-i2c";
252			reg = <0xffc02b00 0x100>;
253			interrupts = <0 106 4>;
254			resets = <&rst I2C3_RESET>;
255			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
256			status = "disabled";
257		};
258
259		i2c4: i2c@ffc02c00 {
260			#address-cells = <1>;
261			#size-cells = <0>;
262			compatible = "snps,designware-i2c";
263			reg = <0xffc02c00 0x100>;
264			interrupts = <0 107 4>;
265			resets = <&rst I2C4_RESET>;
266			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
267			status = "disabled";
268		};
269
270		mmc: dwmmc0@ff808000 {
271			#address-cells = <1>;
272			#size-cells = <0>;
273			compatible = "altr,socfpga-dw-mshc";
274			reg = <0xff808000 0x1000>;
275			interrupts = <0 96 4>;
276			fifo-depth = <0x400>;
277			resets = <&rst SDMMC_RESET>;
278			reset-names = "reset";
279			clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
280				 <&clkmgr STRATIX10_SDMMC_CLK>;
281			clock-names = "biu", "ciu";
282			status = "disabled";
283		};
284
285		ocram: sram@ffe00000 {
286			compatible = "mmio-sram";
287			reg = <0xffe00000 0x100000>;
288		};
289
290		pdma: pdma@ffda0000 {
291			compatible = "arm,pl330", "arm,primecell";
292			reg = <0xffda0000 0x1000>;
293			interrupts = <0 81 4>,
294				     <0 82 4>,
295				     <0 83 4>,
296				     <0 84 4>,
297				     <0 85 4>,
298				     <0 86 4>,
299				     <0 87 4>,
300				     <0 88 4>,
301				     <0 89 4>;
302			#dma-cells = <1>;
303			#dma-channels = <8>;
304			#dma-requests = <32>;
305			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
306			clock-names = "apb_pclk";
307		};
308
309		rst: rstmgr@ffd11000 {
310			#reset-cells = <1>;
311			compatible = "altr,rst-mgr";
312			reg = <0xffd11000 0x1000>;
313			altr,modrst-offset = <0x20>;
314		};
315
316		spi0: spi@ffda4000 {
317			compatible = "snps,dw-apb-ssi";
318			#address-cells = <1>;
319			#size-cells = <0>;
320			reg = <0xffda4000 0x1000>;
321			interrupts = <0 99 4>;
322			resets = <&rst SPIM0_RESET>;
323			reg-io-width = <4>;
324			num-cs = <4>;
325			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
326			status = "disabled";
327		};
328
329		spi1: spi@ffda5000 {
330			compatible = "snps,dw-apb-ssi";
331			#address-cells = <1>;
332			#size-cells = <0>;
333			reg = <0xffda5000 0x1000>;
334			interrupts = <0 100 4>;
335			resets = <&rst SPIM1_RESET>;
336			reg-io-width = <4>;
337			num-cs = <4>;
338			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
339			status = "disabled";
340		};
341
342		sysmgr: sysmgr@ffd12000 {
343			compatible = "altr,sys-mgr", "syscon";
344			reg = <0xffd12000 0x228>;
345		};
346
347		/* Local timer */
348		timer {
349			compatible = "arm,armv8-timer";
350			interrupts = <1 13 0xf08>,
351				     <1 14 0xf08>,
352				     <1 11 0xf08>,
353				     <1 10 0xf08>;
354		};
355
356		timer0: timer0@ffc03000 {
357			compatible = "snps,dw-apb-timer";
358			interrupts = <0 113 4>;
359			reg = <0xffc03000 0x100>;
360			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
361			clock-names = "timer";
362		};
363
364		timer1: timer1@ffc03100 {
365			compatible = "snps,dw-apb-timer";
366			interrupts = <0 114 4>;
367			reg = <0xffc03100 0x100>;
368			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
369			clock-names = "timer";
370		};
371
372		timer2: timer2@ffd00000 {
373			compatible = "snps,dw-apb-timer";
374			interrupts = <0 115 4>;
375			reg = <0xffd00000 0x100>;
376			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
377			clock-names = "timer";
378		};
379
380		timer3: timer3@ffd00100 {
381			compatible = "snps,dw-apb-timer";
382			interrupts = <0 116 4>;
383			reg = <0xffd00100 0x100>;
384			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
385			clock-names = "timer";
386		};
387
388		uart0: serial0@ffc02000 {
389			compatible = "snps,dw-apb-uart";
390			reg = <0xffc02000 0x100>;
391			interrupts = <0 108 4>;
392			reg-shift = <2>;
393			reg-io-width = <4>;
394			resets = <&rst UART0_RESET>;
395			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
396			status = "disabled";
397		};
398
399		uart1: serial1@ffc02100 {
400			compatible = "snps,dw-apb-uart";
401			reg = <0xffc02100 0x100>;
402			interrupts = <0 109 4>;
403			reg-shift = <2>;
404			reg-io-width = <4>;
405			resets = <&rst UART1_RESET>;
406			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
407			status = "disabled";
408		};
409
410		usbphy0: usbphy@0 {
411			#phy-cells = <0>;
412			compatible = "usb-nop-xceiv";
413			status = "okay";
414		};
415
416		usb0: usb@ffb00000 {
417			compatible = "snps,dwc2";
418			reg = <0xffb00000 0x40000>;
419			interrupts = <0 93 4>;
420			phys = <&usbphy0>;
421			phy-names = "usb2-phy";
422			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
423			reset-names = "dwc2", "dwc2-ecc";
424			clocks = <&clkmgr STRATIX10_USB_CLK>;
425			status = "disabled";
426		};
427
428		usb1: usb@ffb40000 {
429			compatible = "snps,dwc2";
430			reg = <0xffb40000 0x40000>;
431			interrupts = <0 94 4>;
432			phys = <&usbphy0>;
433			phy-names = "usb2-phy";
434			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
435			reset-names = "dwc2", "dwc2-ecc";
436			clocks = <&clkmgr STRATIX10_USB_CLK>;
437			status = "disabled";
438		};
439
440		watchdog0: watchdog@ffd00200 {
441			compatible = "snps,dw-wdt";
442			reg = <0xffd00200 0x100>;
443			interrupts = <0 117 4>;
444			resets = <&rst WATCHDOG0_RESET>;
445			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
446			status = "disabled";
447		};
448
449		watchdog1: watchdog@ffd00300 {
450			compatible = "snps,dw-wdt";
451			reg = <0xffd00300 0x100>;
452			interrupts = <0 118 4>;
453			resets = <&rst WATCHDOG1_RESET>;
454			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
455			status = "disabled";
456		};
457
458		watchdog2: watchdog@ffd00400 {
459			compatible = "snps,dw-wdt";
460			reg = <0xffd00400 0x100>;
461			interrupts = <0 125 4>;
462			resets = <&rst WATCHDOG2_RESET>;
463			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
464			status = "disabled";
465		};
466
467		watchdog3: watchdog@ffd00500 {
468			compatible = "snps,dw-wdt";
469			reg = <0xffd00500 0x100>;
470			interrupts = <0 126 4>;
471			resets = <&rst WATCHDOG3_RESET>;
472			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
473			status = "disabled";
474		};
475
476		sdr: sdr@f8011100 {
477			compatible = "altr,sdr-ctl", "syscon";
478			reg = <0xf8011100 0xc0>;
479		};
480
481		eccmgr {
482			compatible = "altr,socfpga-a10-ecc-manager";
483			altr,sysmgr-syscon = <&sysmgr>;
484			#address-cells = <1>;
485			#size-cells = <1>;
486			interrupts = <0 15 4>, <0 95 4>;
487			interrupt-controller;
488			#interrupt-cells = <2>;
489			ranges;
490
491			sdramedac {
492				compatible = "altr,sdram-edac-s10";
493				altr,sdr-syscon = <&sdr>;
494				interrupts = <16 4>, <48 4>;
495			};
496
497			usb0-ecc@ff8c4000 {
498				compatible = "altr,socfpga-usb-ecc";
499				reg = <0xff8c4000 0x100>;
500				altr,ecc-parent = <&usb0>;
501				interrupts = <2 4>,
502					     <34 4>;
503			};
504
505			emac0-rx-ecc@ff8c0000 {
506				compatible = "altr,socfpga-eth-mac-ecc";
507				reg = <0xff8c0000 0x100>;
508				altr,ecc-parent = <&gmac0>;
509				interrupts = <4 4>,
510					     <36 4>;
511			};
512
513			emac0-tx-ecc@ff8c0400 {
514				compatible = "altr,socfpga-eth-mac-ecc";
515				reg = <0xff8c0400 0x100>;
516				altr,ecc-parent = <&gmac0>;
517				interrupts = <5 4>,
518					     <37 4>;
519			};
520
521		};
522
523		qspi: spi@ff8d2000 {
524			compatible = "cdns,qspi-nor";
525			#address-cells = <1>;
526			#size-cells = <0>;
527			reg = <0xff8d2000 0x100>,
528			      <0xff900000 0x100000>;
529			interrupts = <0 3 4>;
530			cdns,fifo-depth = <128>;
531			cdns,fifo-width = <4>;
532			cdns,trigger-address = <0x00000000>;
533			clocks = <&qspi_clk>;
534
535			status = "disabled";
536		};
537	};
538};
539