1/*
2 * Copyright Altera Corporation (C) 2015. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18#include <dt-bindings/reset/altr,rst-mgr-s10.h>
19#include <dt-bindings/gpio/gpio.h>
20
21/ {
22	compatible = "altr,socfpga-stratix10";
23	#address-cells = <2>;
24	#size-cells = <2>;
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu0: cpu@0 {
31			compatible = "arm,cortex-a53", "arm,armv8";
32			device_type = "cpu";
33			enable-method = "psci";
34			reg = <0x0>;
35		};
36
37		cpu1: cpu@1 {
38			compatible = "arm,cortex-a53", "arm,armv8";
39			device_type = "cpu";
40			enable-method = "psci";
41			reg = <0x1>;
42		};
43
44		cpu2: cpu@2 {
45			compatible = "arm,cortex-a53", "arm,armv8";
46			device_type = "cpu";
47			enable-method = "psci";
48			reg = <0x2>;
49		};
50
51		cpu3: cpu@3 {
52			compatible = "arm,cortex-a53", "arm,armv8";
53			device_type = "cpu";
54			enable-method = "psci";
55			reg = <0x3>;
56		};
57	};
58
59	pmu {
60		compatible = "arm,armv8-pmuv3";
61		interrupts = <0 120 8>,
62			     <0 121 8>,
63			     <0 122 8>,
64			     <0 123 8>;
65		interrupt-affinity = <&cpu0>,
66				     <&cpu1>,
67				     <&cpu2>,
68				     <&cpu3>;
69	};
70
71	psci {
72		compatible = "arm,psci-0.2";
73		method = "smc";
74	};
75
76	intc: intc@fffc1000 {
77		compatible = "arm,gic-400", "arm,cortex-a15-gic";
78		#interrupt-cells = <3>;
79		interrupt-controller;
80		reg = <0x0 0xfffc1000 0x0 0x1000>,
81		      <0x0 0xfffc2000 0x0 0x2000>,
82		      <0x0 0xfffc4000 0x0 0x2000>,
83		      <0x0 0xfffc6000 0x0 0x2000>;
84	};
85
86	soc {
87		#address-cells = <1>;
88		#size-cells = <1>;
89		compatible = "simple-bus";
90		device_type = "soc";
91		interrupt-parent = <&intc>;
92		ranges = <0 0 0 0xffffffff>;
93
94		clkmgr@ffd1000 {
95			compatible = "altr,clk-mgr";
96			reg = <0xffd10000 0x1000>;
97		};
98
99		gmac0: ethernet@ff800000 {
100			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
101			reg = <0xff800000 0x2000>;
102			interrupts = <0 90 4>;
103			interrupt-names = "macirq";
104			mac-address = [00 00 00 00 00 00];
105			resets = <&rst EMAC0_RESET>;
106			reset-names = "stmmaceth";
107			status = "disabled";
108		};
109
110		gmac1: ethernet@ff802000 {
111			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
112			reg = <0xff802000 0x2000>;
113			interrupts = <0 91 4>;
114			interrupt-names = "macirq";
115			mac-address = [00 00 00 00 00 00];
116			resets = <&rst EMAC1_RESET>;
117			reset-names = "stmmaceth";
118			status = "disabled";
119		};
120
121		gmac2: ethernet@ff804000 {
122			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
123			reg = <0xff804000 0x2000>;
124			interrupts = <0 92 4>;
125			interrupt-names = "macirq";
126			mac-address = [00 00 00 00 00 00];
127			resets = <&rst EMAC2_RESET>;
128			reset-names = "stmmaceth";
129			status = "disabled";
130		};
131
132		gpio0: gpio@ffc03200 {
133			#address-cells = <1>;
134			#size-cells = <0>;
135			compatible = "snps,dw-apb-gpio";
136			reg = <0xffc03200 0x100>;
137			resets = <&rst GPIO0_RESET>;
138			status = "disabled";
139
140			porta: gpio-controller@0 {
141				compatible = "snps,dw-apb-gpio-port";
142				gpio-controller;
143				#gpio-cells = <2>;
144				snps,nr-gpios = <24>;
145				reg = <0>;
146				interrupt-controller;
147				#interrupt-cells = <2>;
148				interrupts = <0 110 4>;
149			};
150		};
151
152		gpio1: gpio@ffc03300 {
153			#address-cells = <1>;
154			#size-cells = <0>;
155			compatible = "snps,dw-apb-gpio";
156			reg = <0xffc03300 0x100>;
157			resets = <&rst GPIO1_RESET>;
158			status = "disabled";
159
160			portb: gpio-controller@0 {
161				compatible = "snps,dw-apb-gpio-port";
162				gpio-controller;
163				#gpio-cells = <2>;
164				snps,nr-gpios = <24>;
165				reg = <0>;
166				interrupt-controller;
167				#interrupt-cells = <2>;
168				interrupts = <0 111 4>;
169			};
170		};
171
172		i2c0: i2c@ffc02800 {
173			#address-cells = <1>;
174			#size-cells = <0>;
175			compatible = "snps,designware-i2c";
176			reg = <0xffc02800 0x100>;
177			interrupts = <0 103 4>;
178			resets = <&rst I2C0_RESET>;
179			status = "disabled";
180		};
181
182		i2c1: i2c@ffc02900 {
183			#address-cells = <1>;
184			#size-cells = <0>;
185			compatible = "snps,designware-i2c";
186			reg = <0xffc02900 0x100>;
187			interrupts = <0 104 4>;
188			resets = <&rst I2C1_RESET>;
189			status = "disabled";
190		};
191
192		i2c2: i2c@ffc02a00 {
193			#address-cells = <1>;
194			#size-cells = <0>;
195			compatible = "snps,designware-i2c";
196			reg = <0xffc02a00 0x100>;
197			interrupts = <0 105 4>;
198			resets = <&rst I2C2_RESET>;
199			status = "disabled";
200		};
201
202		i2c3: i2c@ffc02b00 {
203			#address-cells = <1>;
204			#size-cells = <0>;
205			compatible = "snps,designware-i2c";
206			reg = <0xffc02b00 0x100>;
207			interrupts = <0 106 4>;
208			resets = <&rst I2C3_RESET>;
209			status = "disabled";
210		};
211
212		i2c4: i2c@ffc02c00 {
213			#address-cells = <1>;
214			#size-cells = <0>;
215			compatible = "snps,designware-i2c";
216			reg = <0xffc02c00 0x100>;
217			interrupts = <0 107 4>;
218			resets = <&rst I2C4_RESET>;
219			status = "disabled";
220		};
221
222		mmc: dwmmc0@ff808000 {
223			#address-cells = <1>;
224			#size-cells = <0>;
225			compatible = "altr,socfpga-dw-mshc";
226			reg = <0xff808000 0x1000>;
227			interrupts = <0 96 4>;
228			fifo-depth = <0x400>;
229			resets = <&rst SDMMC_RESET>;
230			reset-names = "reset";
231			status = "disabled";
232		};
233
234		ocram: sram@ffe00000 {
235			compatible = "mmio-sram";
236			reg = <0xffe00000 0x100000>;
237		};
238
239		rst: rstmgr@ffd11000 {
240			#reset-cells = <1>;
241			compatible = "altr,rst-mgr";
242			reg = <0xffd11000 0x1000>;
243			altr,modrst-offset = <0x20>;
244		};
245
246		spi0: spi@ffda4000 {
247			compatible = "snps,dw-apb-ssi";
248			#address-cells = <1>;
249			#size-cells = <0>;
250			reg = <0xffda4000 0x1000>;
251			interrupts = <0 101 4>;
252			num-chipselect = <4>;
253			bus-num = <0>;
254			status = "disabled";
255		};
256
257		spi1: spi@ffda5000 {
258			compatible = "snps,dw-apb-ssi";
259			#address-cells = <1>;
260			#size-cells = <0>;
261			reg = <0xffda5000 0x1000>;
262			interrupts = <0 102 4>;
263			num-chipselect = <4>;
264			bus-num = <0>;
265			status = "disabled";
266		};
267
268		sysmgr: sysmgr@ffd12000 {
269			compatible = "altr,sys-mgr", "syscon";
270			reg = <0xffd12000 0x1000>;
271		};
272
273		/* Local timer */
274		timer {
275			compatible = "arm,armv8-timer";
276			interrupts = <1 13 0xf08>,
277				     <1 14 0xf08>,
278				     <1 11 0xf08>,
279				     <1 10 0xf08>;
280		};
281
282		timer0: timer0@ffc03000 {
283			compatible = "snps,dw-apb-timer";
284			interrupts = <0 113 4>;
285			reg = <0xffc03000 0x100>;
286		};
287
288		timer1: timer1@ffc03100 {
289			compatible = "snps,dw-apb-timer";
290			interrupts = <0 114 4>;
291			reg = <0xffc03100 0x100>;
292		};
293
294		timer2: timer2@ffd00000 {
295			compatible = "snps,dw-apb-timer";
296			interrupts = <0 115 4>;
297			reg = <0xffd00000 0x100>;
298		};
299
300		timer3: timer3@ffd00100 {
301			compatible = "snps,dw-apb-timer";
302			interrupts = <0 116 4>;
303			reg = <0xffd00100 0x100>;
304		};
305
306		uart0: serial0@ffc02000 {
307			compatible = "snps,dw-apb-uart";
308			reg = <0xffc02000 0x100>;
309			interrupts = <0 108 4>;
310			reg-shift = <2>;
311			reg-io-width = <4>;
312			resets = <&rst UART0_RESET>;
313			status = "disabled";
314		};
315
316		uart1: serial1@ffc02100 {
317			compatible = "snps,dw-apb-uart";
318			reg = <0xffc02100 0x100>;
319			interrupts = <0 109 4>;
320			reg-shift = <2>;
321			reg-io-width = <4>;
322			resets = <&rst UART1_RESET>;
323			status = "disabled";
324		};
325
326		usbphy0: usbphy@0 {
327			#phy-cells = <0>;
328			compatible = "usb-nop-xceiv";
329			status = "okay";
330		};
331
332		usb0: usb@ffb00000 {
333			compatible = "snps,dwc2";
334			reg = <0xffb00000 0x40000>;
335			interrupts = <0 93 4>;
336			phys = <&usbphy0>;
337			phy-names = "usb2-phy";
338			resets = <&rst USB0_RESET>;
339			reset-names = "dwc2";
340			status = "disabled";
341		};
342
343		usb1: usb@ffb40000 {
344			compatible = "snps,dwc2";
345			reg = <0xffb40000 0x40000>;
346			interrupts = <0 94 4>;
347			phys = <&usbphy0>;
348			phy-names = "usb2-phy";
349			resets = <&rst USB1_RESET>;
350			reset-names = "dwc2";
351			status = "disabled";
352		};
353
354		watchdog0: watchdog@ffd00200 {
355			compatible = "snps,dw-wdt";
356			reg = <0xffd00200 0x100>;
357			interrupts = <0 117 4>;
358			resets = <&rst WATCHDOG0_RESET>;
359			status = "disabled";
360		};
361
362		watchdog1: watchdog@ffd00300 {
363			compatible = "snps,dw-wdt";
364			reg = <0xffd00300 0x100>;
365			interrupts = <0 118 4>;
366			resets = <&rst WATCHDOG1_RESET>;
367			status = "disabled";
368		};
369
370		watchdog2: watchdog@ffd00400 {
371			compatible = "snps,dw-wdt";
372			reg = <0xffd00400 0x100>;
373			interrupts = <0 125 4>;
374			resets = <&rst WATCHDOG2_RESET>;
375			status = "disabled";
376		};
377
378		watchdog3: watchdog@ffd00500 {
379			compatible = "snps,dw-wdt";
380			reg = <0xffd00500 0x100>;
381			interrupts = <0 126 4>;
382			resets = <&rst WATCHDOG3_RESET>;
383			status = "disabled";
384		};
385	};
386};
387