1/*
2 * Copyright Altera Corporation (C) 2015. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18#include <dt-bindings/reset/altr,rst-mgr-s10.h>
19#include <dt-bindings/gpio/gpio.h>
20#include <dt-bindings/clock/stratix10-clock.h>
21
22/ {
23	compatible = "altr,socfpga-stratix10";
24	#address-cells = <2>;
25	#size-cells = <2>;
26
27	cpus {
28		#address-cells = <1>;
29		#size-cells = <0>;
30
31		cpu0: cpu@0 {
32			compatible = "arm,cortex-a53", "arm,armv8";
33			device_type = "cpu";
34			enable-method = "psci";
35			reg = <0x0>;
36		};
37
38		cpu1: cpu@1 {
39			compatible = "arm,cortex-a53", "arm,armv8";
40			device_type = "cpu";
41			enable-method = "psci";
42			reg = <0x1>;
43		};
44
45		cpu2: cpu@2 {
46			compatible = "arm,cortex-a53", "arm,armv8";
47			device_type = "cpu";
48			enable-method = "psci";
49			reg = <0x2>;
50		};
51
52		cpu3: cpu@3 {
53			compatible = "arm,cortex-a53", "arm,armv8";
54			device_type = "cpu";
55			enable-method = "psci";
56			reg = <0x3>;
57		};
58	};
59
60	pmu {
61		compatible = "arm,armv8-pmuv3";
62		interrupts = <0 120 8>,
63			     <0 121 8>,
64			     <0 122 8>,
65			     <0 123 8>;
66		interrupt-affinity = <&cpu0>,
67				     <&cpu1>,
68				     <&cpu2>,
69				     <&cpu3>;
70		interrupt-parent = <&intc>;
71	};
72
73	psci {
74		compatible = "arm,psci-0.2";
75		method = "smc";
76	};
77
78	intc: intc@fffc1000 {
79		compatible = "arm,gic-400", "arm,cortex-a15-gic";
80		#interrupt-cells = <3>;
81		interrupt-controller;
82		reg = <0x0 0xfffc1000 0x0 0x1000>,
83		      <0x0 0xfffc2000 0x0 0x2000>,
84		      <0x0 0xfffc4000 0x0 0x2000>,
85		      <0x0 0xfffc6000 0x0 0x2000>;
86	};
87
88	soc {
89		#address-cells = <1>;
90		#size-cells = <1>;
91		compatible = "simple-bus";
92		device_type = "soc";
93		interrupt-parent = <&intc>;
94		ranges = <0 0 0 0xffffffff>;
95
96		clkmgr: clock-controller@ffd10000 {
97			compatible = "intel,stratix10-clkmgr";
98			reg = <0xffd10000 0x1000>;
99			#clock-cells = <1>;
100		};
101
102		clocks {
103			cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
104				#clock-cells = <0>;
105				compatible = "fixed-clock";
106			};
107
108			cb_intosc_ls_clk: cb-intosc-ls-clk {
109				#clock-cells = <0>;
110				compatible = "fixed-clock";
111			};
112
113			f2s_free_clk: f2s-free-clk {
114				#clock-cells = <0>;
115				compatible = "fixed-clock";
116			};
117
118			osc1: osc1 {
119				#clock-cells = <0>;
120				compatible = "fixed-clock";
121			};
122
123			qspi_clk: qspi-clk {
124				#clock-cells = <0>;
125				compatible = "fixed-clock";
126				clock-frequency = <200000000>;
127			};
128		};
129
130		gmac0: ethernet@ff800000 {
131			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
132			reg = <0xff800000 0x2000>;
133			interrupts = <0 90 4>;
134			interrupt-names = "macirq";
135			mac-address = [00 00 00 00 00 00];
136			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
137			reset-names = "stmmaceth", "stmmaceth-ocp";
138			clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
139			clock-names = "stmmaceth";
140			status = "disabled";
141		};
142
143		gmac1: ethernet@ff802000 {
144			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
145			reg = <0xff802000 0x2000>;
146			interrupts = <0 91 4>;
147			interrupt-names = "macirq";
148			mac-address = [00 00 00 00 00 00];
149			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
150			reset-names = "stmmaceth", "stmmaceth-ocp";
151			clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
152			clock-names = "stmmaceth";
153			status = "disabled";
154		};
155
156		gmac2: ethernet@ff804000 {
157			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
158			reg = <0xff804000 0x2000>;
159			interrupts = <0 92 4>;
160			interrupt-names = "macirq";
161			mac-address = [00 00 00 00 00 00];
162			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
163			reset-names = "stmmaceth", "stmmaceth-ocp";
164			clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
165			clock-names = "stmmaceth";
166			status = "disabled";
167		};
168
169		gpio0: gpio@ffc03200 {
170			#address-cells = <1>;
171			#size-cells = <0>;
172			compatible = "snps,dw-apb-gpio";
173			reg = <0xffc03200 0x100>;
174			resets = <&rst GPIO0_RESET>;
175			status = "disabled";
176
177			porta: gpio-controller@0 {
178				compatible = "snps,dw-apb-gpio-port";
179				gpio-controller;
180				#gpio-cells = <2>;
181				snps,nr-gpios = <24>;
182				reg = <0>;
183				interrupt-controller;
184				#interrupt-cells = <2>;
185				interrupts = <0 110 4>;
186			};
187		};
188
189		gpio1: gpio@ffc03300 {
190			#address-cells = <1>;
191			#size-cells = <0>;
192			compatible = "snps,dw-apb-gpio";
193			reg = <0xffc03300 0x100>;
194			resets = <&rst GPIO1_RESET>;
195			status = "disabled";
196
197			portb: gpio-controller@0 {
198				compatible = "snps,dw-apb-gpio-port";
199				gpio-controller;
200				#gpio-cells = <2>;
201				snps,nr-gpios = <24>;
202				reg = <0>;
203				interrupt-controller;
204				#interrupt-cells = <2>;
205				interrupts = <0 111 4>;
206			};
207		};
208
209		i2c0: i2c@ffc02800 {
210			#address-cells = <1>;
211			#size-cells = <0>;
212			compatible = "snps,designware-i2c";
213			reg = <0xffc02800 0x100>;
214			interrupts = <0 103 4>;
215			resets = <&rst I2C0_RESET>;
216			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
217			status = "disabled";
218		};
219
220		i2c1: i2c@ffc02900 {
221			#address-cells = <1>;
222			#size-cells = <0>;
223			compatible = "snps,designware-i2c";
224			reg = <0xffc02900 0x100>;
225			interrupts = <0 104 4>;
226			resets = <&rst I2C1_RESET>;
227			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
228			status = "disabled";
229		};
230
231		i2c2: i2c@ffc02a00 {
232			#address-cells = <1>;
233			#size-cells = <0>;
234			compatible = "snps,designware-i2c";
235			reg = <0xffc02a00 0x100>;
236			interrupts = <0 105 4>;
237			resets = <&rst I2C2_RESET>;
238			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
239			status = "disabled";
240		};
241
242		i2c3: i2c@ffc02b00 {
243			#address-cells = <1>;
244			#size-cells = <0>;
245			compatible = "snps,designware-i2c";
246			reg = <0xffc02b00 0x100>;
247			interrupts = <0 106 4>;
248			resets = <&rst I2C3_RESET>;
249			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
250			status = "disabled";
251		};
252
253		i2c4: i2c@ffc02c00 {
254			#address-cells = <1>;
255			#size-cells = <0>;
256			compatible = "snps,designware-i2c";
257			reg = <0xffc02c00 0x100>;
258			interrupts = <0 107 4>;
259			resets = <&rst I2C4_RESET>;
260			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
261			status = "disabled";
262		};
263
264		mmc: dwmmc0@ff808000 {
265			#address-cells = <1>;
266			#size-cells = <0>;
267			compatible = "altr,socfpga-dw-mshc";
268			reg = <0xff808000 0x1000>;
269			interrupts = <0 96 4>;
270			fifo-depth = <0x400>;
271			resets = <&rst SDMMC_RESET>;
272			reset-names = "reset";
273			clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
274				 <&clkmgr STRATIX10_SDMMC_CLK>;
275			clock-names = "biu", "ciu";
276			status = "disabled";
277		};
278
279		ocram: sram@ffe00000 {
280			compatible = "mmio-sram";
281			reg = <0xffe00000 0x100000>;
282		};
283
284		pdma: pdma@ffda0000 {
285			compatible = "arm,pl330", "arm,primecell";
286			reg = <0xffda0000 0x1000>;
287			interrupts = <0 81 4>,
288				     <0 82 4>,
289				     <0 83 4>,
290				     <0 84 4>,
291				     <0 85 4>,
292				     <0 86 4>,
293				     <0 87 4>,
294				     <0 88 4>,
295				     <0 89 4>;
296			#dma-cells = <1>;
297			#dma-channels = <8>;
298			#dma-requests = <32>;
299			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
300			clock-names = "apb_pclk";
301		};
302
303		rst: rstmgr@ffd11000 {
304			#reset-cells = <1>;
305			compatible = "altr,rst-mgr";
306			reg = <0xffd11000 0x1000>;
307			altr,modrst-offset = <0x20>;
308		};
309
310		spi0: spi@ffda4000 {
311			compatible = "snps,dw-apb-ssi";
312			#address-cells = <1>;
313			#size-cells = <0>;
314			reg = <0xffda4000 0x1000>;
315			interrupts = <0 99 4>;
316			resets = <&rst SPIM0_RESET>;
317			reg-io-width = <4>;
318			num-cs = <4>;
319			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
320			status = "disabled";
321		};
322
323		spi1: spi@ffda5000 {
324			compatible = "snps,dw-apb-ssi";
325			#address-cells = <1>;
326			#size-cells = <0>;
327			reg = <0xffda5000 0x1000>;
328			interrupts = <0 100 4>;
329			resets = <&rst SPIM1_RESET>;
330			reg-io-width = <4>;
331			num-cs = <4>;
332			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
333			status = "disabled";
334		};
335
336		sysmgr: sysmgr@ffd12000 {
337			compatible = "altr,sys-mgr", "syscon";
338			reg = <0xffd12000 0x1000>;
339		};
340
341		/* Local timer */
342		timer {
343			compatible = "arm,armv8-timer";
344			interrupts = <1 13 0xf08>,
345				     <1 14 0xf08>,
346				     <1 11 0xf08>,
347				     <1 10 0xf08>;
348		};
349
350		timer0: timer0@ffc03000 {
351			compatible = "snps,dw-apb-timer";
352			interrupts = <0 113 4>;
353			reg = <0xffc03000 0x100>;
354			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
355			clock-names = "timer";
356		};
357
358		timer1: timer1@ffc03100 {
359			compatible = "snps,dw-apb-timer";
360			interrupts = <0 114 4>;
361			reg = <0xffc03100 0x100>;
362			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
363			clock-names = "timer";
364		};
365
366		timer2: timer2@ffd00000 {
367			compatible = "snps,dw-apb-timer";
368			interrupts = <0 115 4>;
369			reg = <0xffd00000 0x100>;
370			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
371			clock-names = "timer";
372		};
373
374		timer3: timer3@ffd00100 {
375			compatible = "snps,dw-apb-timer";
376			interrupts = <0 116 4>;
377			reg = <0xffd00100 0x100>;
378			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
379			clock-names = "timer";
380		};
381
382		uart0: serial0@ffc02000 {
383			compatible = "snps,dw-apb-uart";
384			reg = <0xffc02000 0x100>;
385			interrupts = <0 108 4>;
386			reg-shift = <2>;
387			reg-io-width = <4>;
388			resets = <&rst UART0_RESET>;
389			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
390			status = "disabled";
391		};
392
393		uart1: serial1@ffc02100 {
394			compatible = "snps,dw-apb-uart";
395			reg = <0xffc02100 0x100>;
396			interrupts = <0 109 4>;
397			reg-shift = <2>;
398			reg-io-width = <4>;
399			resets = <&rst UART1_RESET>;
400			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
401			status = "disabled";
402		};
403
404		usbphy0: usbphy@0 {
405			#phy-cells = <0>;
406			compatible = "usb-nop-xceiv";
407			status = "okay";
408		};
409
410		usb0: usb@ffb00000 {
411			compatible = "snps,dwc2";
412			reg = <0xffb00000 0x40000>;
413			interrupts = <0 93 4>;
414			phys = <&usbphy0>;
415			phy-names = "usb2-phy";
416			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
417			reset-names = "dwc2", "dwc2-ecc";
418			clocks = <&clkmgr STRATIX10_USB_CLK>;
419			status = "disabled";
420		};
421
422		usb1: usb@ffb40000 {
423			compatible = "snps,dwc2";
424			reg = <0xffb40000 0x40000>;
425			interrupts = <0 94 4>;
426			phys = <&usbphy0>;
427			phy-names = "usb2-phy";
428			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
429			reset-names = "dwc2", "dwc2-ecc";
430			clocks = <&clkmgr STRATIX10_USB_CLK>;
431			status = "disabled";
432		};
433
434		watchdog0: watchdog@ffd00200 {
435			compatible = "snps,dw-wdt";
436			reg = <0xffd00200 0x100>;
437			interrupts = <0 117 4>;
438			resets = <&rst WATCHDOG0_RESET>;
439			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
440			status = "disabled";
441		};
442
443		watchdog1: watchdog@ffd00300 {
444			compatible = "snps,dw-wdt";
445			reg = <0xffd00300 0x100>;
446			interrupts = <0 118 4>;
447			resets = <&rst WATCHDOG1_RESET>;
448			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
449			status = "disabled";
450		};
451
452		watchdog2: watchdog@ffd00400 {
453			compatible = "snps,dw-wdt";
454			reg = <0xffd00400 0x100>;
455			interrupts = <0 125 4>;
456			resets = <&rst WATCHDOG2_RESET>;
457			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
458			status = "disabled";
459		};
460
461		watchdog3: watchdog@ffd00500 {
462			compatible = "snps,dw-wdt";
463			reg = <0xffd00500 0x100>;
464			interrupts = <0 126 4>;
465			resets = <&rst WATCHDOG3_RESET>;
466			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
467			status = "disabled";
468		};
469
470		eccmgr {
471			compatible = "altr,socfpga-s10-ecc-manager";
472			interrupts = <0 15 4>, <0 95 4>;
473			interrupt-controller;
474			#interrupt-cells = <2>;
475
476			sdramedac {
477				compatible = "altr,sdram-edac-s10";
478				interrupts = <16 4>, <48 4>;
479			};
480		};
481
482		qspi: spi@ff8d2000 {
483			compatible = "cdns,qspi-nor";
484			#address-cells = <1>;
485			#size-cells = <0>;
486			reg = <0xff8d2000 0x100>,
487			      <0xff900000 0x100000>;
488			interrupts = <0 3 4>;
489			cdns,fifo-depth = <128>;
490			cdns,fifo-width = <4>;
491			cdns,trigger-address = <0x00000000>;
492			clocks = <&qspi_clk>;
493
494			status = "disabled";
495		};
496	};
497};
498