1/*
2 * Copyright Altera Corporation (C) 2015. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18#include <dt-bindings/reset/altr,rst-mgr-s10.h>
19#include <dt-bindings/gpio/gpio.h>
20
21/ {
22	compatible = "altr,socfpga-stratix10";
23	#address-cells = <2>;
24	#size-cells = <2>;
25
26	cpus {
27		#address-cells = <1>;
28		#size-cells = <0>;
29
30		cpu0: cpu@0 {
31			compatible = "arm,cortex-a53", "arm,armv8";
32			device_type = "cpu";
33			enable-method = "psci";
34			reg = <0x0>;
35		};
36
37		cpu1: cpu@1 {
38			compatible = "arm,cortex-a53", "arm,armv8";
39			device_type = "cpu";
40			enable-method = "psci";
41			reg = <0x1>;
42		};
43
44		cpu2: cpu@2 {
45			compatible = "arm,cortex-a53", "arm,armv8";
46			device_type = "cpu";
47			enable-method = "psci";
48			reg = <0x2>;
49		};
50
51		cpu3: cpu@3 {
52			compatible = "arm,cortex-a53", "arm,armv8";
53			device_type = "cpu";
54			enable-method = "psci";
55			reg = <0x3>;
56		};
57	};
58
59	pmu {
60		compatible = "arm,armv8-pmuv3";
61		interrupts = <0 120 8>,
62			     <0 121 8>,
63			     <0 122 8>,
64			     <0 123 8>;
65		interrupt-affinity = <&cpu0>,
66				     <&cpu1>,
67				     <&cpu2>,
68				     <&cpu3>;
69		interrupt-parent = <&intc>;
70	};
71
72	psci {
73		compatible = "arm,psci-0.2";
74		method = "smc";
75	};
76
77	intc: intc@fffc1000 {
78		compatible = "arm,gic-400", "arm,cortex-a15-gic";
79		#interrupt-cells = <3>;
80		interrupt-controller;
81		reg = <0x0 0xfffc1000 0x0 0x1000>,
82		      <0x0 0xfffc2000 0x0 0x2000>,
83		      <0x0 0xfffc4000 0x0 0x2000>,
84		      <0x0 0xfffc6000 0x0 0x2000>;
85	};
86
87	soc {
88		#address-cells = <1>;
89		#size-cells = <1>;
90		compatible = "simple-bus";
91		device_type = "soc";
92		interrupt-parent = <&intc>;
93		ranges = <0 0 0 0xffffffff>;
94
95		clkmgr@ffd1000 {
96			compatible = "altr,clk-mgr";
97			reg = <0xffd10000 0x1000>;
98		};
99
100		gmac0: ethernet@ff800000 {
101			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
102			reg = <0xff800000 0x2000>;
103			interrupts = <0 90 4>;
104			interrupt-names = "macirq";
105			mac-address = [00 00 00 00 00 00];
106			resets = <&rst EMAC0_RESET>;
107			reset-names = "stmmaceth";
108			status = "disabled";
109		};
110
111		gmac1: ethernet@ff802000 {
112			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
113			reg = <0xff802000 0x2000>;
114			interrupts = <0 91 4>;
115			interrupt-names = "macirq";
116			mac-address = [00 00 00 00 00 00];
117			resets = <&rst EMAC1_RESET>;
118			reset-names = "stmmaceth";
119			status = "disabled";
120		};
121
122		gmac2: ethernet@ff804000 {
123			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
124			reg = <0xff804000 0x2000>;
125			interrupts = <0 92 4>;
126			interrupt-names = "macirq";
127			mac-address = [00 00 00 00 00 00];
128			resets = <&rst EMAC2_RESET>;
129			reset-names = "stmmaceth";
130			status = "disabled";
131		};
132
133		gpio0: gpio@ffc03200 {
134			#address-cells = <1>;
135			#size-cells = <0>;
136			compatible = "snps,dw-apb-gpio";
137			reg = <0xffc03200 0x100>;
138			resets = <&rst GPIO0_RESET>;
139			status = "disabled";
140
141			porta: gpio-controller@0 {
142				compatible = "snps,dw-apb-gpio-port";
143				gpio-controller;
144				#gpio-cells = <2>;
145				snps,nr-gpios = <24>;
146				reg = <0>;
147				interrupt-controller;
148				#interrupt-cells = <2>;
149				interrupts = <0 110 4>;
150			};
151		};
152
153		gpio1: gpio@ffc03300 {
154			#address-cells = <1>;
155			#size-cells = <0>;
156			compatible = "snps,dw-apb-gpio";
157			reg = <0xffc03300 0x100>;
158			resets = <&rst GPIO1_RESET>;
159			status = "disabled";
160
161			portb: gpio-controller@0 {
162				compatible = "snps,dw-apb-gpio-port";
163				gpio-controller;
164				#gpio-cells = <2>;
165				snps,nr-gpios = <24>;
166				reg = <0>;
167				interrupt-controller;
168				#interrupt-cells = <2>;
169				interrupts = <0 111 4>;
170			};
171		};
172
173		i2c0: i2c@ffc02800 {
174			#address-cells = <1>;
175			#size-cells = <0>;
176			compatible = "snps,designware-i2c";
177			reg = <0xffc02800 0x100>;
178			interrupts = <0 103 4>;
179			resets = <&rst I2C0_RESET>;
180			status = "disabled";
181		};
182
183		i2c1: i2c@ffc02900 {
184			#address-cells = <1>;
185			#size-cells = <0>;
186			compatible = "snps,designware-i2c";
187			reg = <0xffc02900 0x100>;
188			interrupts = <0 104 4>;
189			resets = <&rst I2C1_RESET>;
190			status = "disabled";
191		};
192
193		i2c2: i2c@ffc02a00 {
194			#address-cells = <1>;
195			#size-cells = <0>;
196			compatible = "snps,designware-i2c";
197			reg = <0xffc02a00 0x100>;
198			interrupts = <0 105 4>;
199			resets = <&rst I2C2_RESET>;
200			status = "disabled";
201		};
202
203		i2c3: i2c@ffc02b00 {
204			#address-cells = <1>;
205			#size-cells = <0>;
206			compatible = "snps,designware-i2c";
207			reg = <0xffc02b00 0x100>;
208			interrupts = <0 106 4>;
209			resets = <&rst I2C3_RESET>;
210			status = "disabled";
211		};
212
213		i2c4: i2c@ffc02c00 {
214			#address-cells = <1>;
215			#size-cells = <0>;
216			compatible = "snps,designware-i2c";
217			reg = <0xffc02c00 0x100>;
218			interrupts = <0 107 4>;
219			resets = <&rst I2C4_RESET>;
220			status = "disabled";
221		};
222
223		mmc: dwmmc0@ff808000 {
224			#address-cells = <1>;
225			#size-cells = <0>;
226			compatible = "altr,socfpga-dw-mshc";
227			reg = <0xff808000 0x1000>;
228			interrupts = <0 96 4>;
229			fifo-depth = <0x400>;
230			resets = <&rst SDMMC_RESET>;
231			reset-names = "reset";
232			status = "disabled";
233		};
234
235		ocram: sram@ffe00000 {
236			compatible = "mmio-sram";
237			reg = <0xffe00000 0x100000>;
238		};
239
240		rst: rstmgr@ffd11000 {
241			#reset-cells = <1>;
242			compatible = "altr,rst-mgr";
243			reg = <0xffd11000 0x1000>;
244			altr,modrst-offset = <0x20>;
245		};
246
247		spi0: spi@ffda4000 {
248			compatible = "snps,dw-apb-ssi";
249			#address-cells = <1>;
250			#size-cells = <0>;
251			reg = <0xffda4000 0x1000>;
252			interrupts = <0 99 4>;
253			resets = <&rst SPIM0_RESET>;
254			reg-io-width = <4>;
255			num-chipselect = <4>;
256			bus-num = <0>;
257			status = "disabled";
258		};
259
260		spi1: spi@ffda5000 {
261			compatible = "snps,dw-apb-ssi";
262			#address-cells = <1>;
263			#size-cells = <0>;
264			reg = <0xffda5000 0x1000>;
265			interrupts = <0 100 4>;
266			resets = <&rst SPIM1_RESET>;
267			reg-io-width = <4>;
268			num-chipselect = <4>;
269			bus-num = <0>;
270			status = "disabled";
271		};
272
273		sysmgr: sysmgr@ffd12000 {
274			compatible = "altr,sys-mgr", "syscon";
275			reg = <0xffd12000 0x1000>;
276		};
277
278		/* Local timer */
279		timer {
280			compatible = "arm,armv8-timer";
281			interrupts = <1 13 0xf08>,
282				     <1 14 0xf08>,
283				     <1 11 0xf08>,
284				     <1 10 0xf08>;
285		};
286
287		timer0: timer0@ffc03000 {
288			compatible = "snps,dw-apb-timer";
289			interrupts = <0 113 4>;
290			reg = <0xffc03000 0x100>;
291		};
292
293		timer1: timer1@ffc03100 {
294			compatible = "snps,dw-apb-timer";
295			interrupts = <0 114 4>;
296			reg = <0xffc03100 0x100>;
297		};
298
299		timer2: timer2@ffd00000 {
300			compatible = "snps,dw-apb-timer";
301			interrupts = <0 115 4>;
302			reg = <0xffd00000 0x100>;
303		};
304
305		timer3: timer3@ffd00100 {
306			compatible = "snps,dw-apb-timer";
307			interrupts = <0 116 4>;
308			reg = <0xffd00100 0x100>;
309		};
310
311		uart0: serial0@ffc02000 {
312			compatible = "snps,dw-apb-uart";
313			reg = <0xffc02000 0x100>;
314			interrupts = <0 108 4>;
315			reg-shift = <2>;
316			reg-io-width = <4>;
317			resets = <&rst UART0_RESET>;
318			status = "disabled";
319		};
320
321		uart1: serial1@ffc02100 {
322			compatible = "snps,dw-apb-uart";
323			reg = <0xffc02100 0x100>;
324			interrupts = <0 109 4>;
325			reg-shift = <2>;
326			reg-io-width = <4>;
327			resets = <&rst UART1_RESET>;
328			status = "disabled";
329		};
330
331		usbphy0: usbphy@0 {
332			#phy-cells = <0>;
333			compatible = "usb-nop-xceiv";
334			status = "okay";
335		};
336
337		usb0: usb@ffb00000 {
338			compatible = "snps,dwc2";
339			reg = <0xffb00000 0x40000>;
340			interrupts = <0 93 4>;
341			phys = <&usbphy0>;
342			phy-names = "usb2-phy";
343			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
344			reset-names = "dwc2", "dwc2-ecc";
345			status = "disabled";
346		};
347
348		usb1: usb@ffb40000 {
349			compatible = "snps,dwc2";
350			reg = <0xffb40000 0x40000>;
351			interrupts = <0 94 4>;
352			phys = <&usbphy0>;
353			phy-names = "usb2-phy";
354			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
355			reset-names = "dwc2", "dwc2-ecc";
356			status = "disabled";
357		};
358
359		watchdog0: watchdog@ffd00200 {
360			compatible = "snps,dw-wdt";
361			reg = <0xffd00200 0x100>;
362			interrupts = <0 117 4>;
363			resets = <&rst WATCHDOG0_RESET>;
364			status = "disabled";
365		};
366
367		watchdog1: watchdog@ffd00300 {
368			compatible = "snps,dw-wdt";
369			reg = <0xffd00300 0x100>;
370			interrupts = <0 118 4>;
371			resets = <&rst WATCHDOG1_RESET>;
372			status = "disabled";
373		};
374
375		watchdog2: watchdog@ffd00400 {
376			compatible = "snps,dw-wdt";
377			reg = <0xffd00400 0x100>;
378			interrupts = <0 125 4>;
379			resets = <&rst WATCHDOG2_RESET>;
380			status = "disabled";
381		};
382
383		watchdog3: watchdog@ffd00500 {
384			compatible = "snps,dw-wdt";
385			reg = <0xffd00500 0x100>;
386			interrupts = <0 126 4>;
387			resets = <&rst WATCHDOG3_RESET>;
388			status = "disabled";
389		};
390	};
391};
392