1/*
2 * Copyright Altera Corporation (C) 2015. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program.  If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/dts-v1/;
18#include <dt-bindings/reset/altr,rst-mgr-s10.h>
19#include <dt-bindings/gpio/gpio.h>
20#include <dt-bindings/clock/stratix10-clock.h>
21
22/ {
23	compatible = "altr,socfpga-stratix10";
24	#address-cells = <2>;
25	#size-cells = <2>;
26
27	reserved-memory {
28		#address-cells = <2>;
29		#size-cells = <2>;
30		ranges;
31
32		service_reserved: svcbuffer@0 {
33			compatible = "shared-dma-pool";
34			reg = <0x0 0x0 0x0 0x1000000>;
35			alignment = <0x1000>;
36			no-map;
37		};
38	};
39
40	cpus {
41		#address-cells = <1>;
42		#size-cells = <0>;
43
44		cpu0: cpu@0 {
45			compatible = "arm,cortex-a53", "arm,armv8";
46			device_type = "cpu";
47			enable-method = "psci";
48			reg = <0x0>;
49		};
50
51		cpu1: cpu@1 {
52			compatible = "arm,cortex-a53", "arm,armv8";
53			device_type = "cpu";
54			enable-method = "psci";
55			reg = <0x1>;
56		};
57
58		cpu2: cpu@2 {
59			compatible = "arm,cortex-a53", "arm,armv8";
60			device_type = "cpu";
61			enable-method = "psci";
62			reg = <0x2>;
63		};
64
65		cpu3: cpu@3 {
66			compatible = "arm,cortex-a53", "arm,armv8";
67			device_type = "cpu";
68			enable-method = "psci";
69			reg = <0x3>;
70		};
71	};
72
73	pmu {
74		compatible = "arm,armv8-pmuv3";
75		interrupts = <0 120 8>,
76			     <0 121 8>,
77			     <0 122 8>,
78			     <0 123 8>;
79		interrupt-affinity = <&cpu0>,
80				     <&cpu1>,
81				     <&cpu2>,
82				     <&cpu3>;
83		interrupt-parent = <&intc>;
84	};
85
86	psci {
87		compatible = "arm,psci-0.2";
88		method = "smc";
89	};
90
91	intc: intc@fffc1000 {
92		compatible = "arm,gic-400", "arm,cortex-a15-gic";
93		#interrupt-cells = <3>;
94		interrupt-controller;
95		reg = <0x0 0xfffc1000 0x0 0x1000>,
96		      <0x0 0xfffc2000 0x0 0x2000>,
97		      <0x0 0xfffc4000 0x0 0x2000>,
98		      <0x0 0xfffc6000 0x0 0x2000>;
99	};
100
101	soc {
102		#address-cells = <1>;
103		#size-cells = <1>;
104		compatible = "simple-bus";
105		device_type = "soc";
106		interrupt-parent = <&intc>;
107		ranges = <0 0 0 0xffffffff>;
108
109		base_fpga_region {
110			#address-cells = <0x1>;
111			#size-cells = <0x1>;
112
113			compatible = "fpga-region";
114			fpga-mgr = <&fpga_mgr>;
115		};
116
117		clkmgr: clock-controller@ffd10000 {
118			compatible = "intel,stratix10-clkmgr";
119			reg = <0xffd10000 0x1000>;
120			#clock-cells = <1>;
121		};
122
123		clocks {
124			cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
125				#clock-cells = <0>;
126				compatible = "fixed-clock";
127			};
128
129			cb_intosc_ls_clk: cb-intosc-ls-clk {
130				#clock-cells = <0>;
131				compatible = "fixed-clock";
132			};
133
134			f2s_free_clk: f2s-free-clk {
135				#clock-cells = <0>;
136				compatible = "fixed-clock";
137			};
138
139			osc1: osc1 {
140				#clock-cells = <0>;
141				compatible = "fixed-clock";
142			};
143
144			qspi_clk: qspi-clk {
145				#clock-cells = <0>;
146				compatible = "fixed-clock";
147				clock-frequency = <200000000>;
148			};
149		};
150
151		gmac0: ethernet@ff800000 {
152			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
153			reg = <0xff800000 0x2000>;
154			interrupts = <0 90 4>;
155			interrupt-names = "macirq";
156			mac-address = [00 00 00 00 00 00];
157			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
158			reset-names = "stmmaceth", "stmmaceth-ocp";
159			clocks = <&clkmgr STRATIX10_EMAC0_CLK>;
160			clock-names = "stmmaceth";
161			tx-fifo-depth = <16384>;
162			rx-fifo-depth = <16384>;
163			snps,multicast-filter-bins = <256>;
164			status = "disabled";
165		};
166
167		gmac1: ethernet@ff802000 {
168			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
169			reg = <0xff802000 0x2000>;
170			interrupts = <0 91 4>;
171			interrupt-names = "macirq";
172			mac-address = [00 00 00 00 00 00];
173			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
174			reset-names = "stmmaceth", "stmmaceth-ocp";
175			clocks = <&clkmgr STRATIX10_EMAC1_CLK>;
176			clock-names = "stmmaceth";
177			tx-fifo-depth = <16384>;
178			rx-fifo-depth = <16384>;
179			snps,multicast-filter-bins = <256>;
180			status = "disabled";
181		};
182
183		gmac2: ethernet@ff804000 {
184			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
185			reg = <0xff804000 0x2000>;
186			interrupts = <0 92 4>;
187			interrupt-names = "macirq";
188			mac-address = [00 00 00 00 00 00];
189			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
190			reset-names = "stmmaceth", "stmmaceth-ocp";
191			clocks = <&clkmgr STRATIX10_EMAC2_CLK>;
192			clock-names = "stmmaceth";
193			tx-fifo-depth = <16384>;
194			rx-fifo-depth = <16384>;
195			snps,multicast-filter-bins = <256>;
196			status = "disabled";
197		};
198
199		gpio0: gpio@ffc03200 {
200			#address-cells = <1>;
201			#size-cells = <0>;
202			compatible = "snps,dw-apb-gpio";
203			reg = <0xffc03200 0x100>;
204			resets = <&rst GPIO0_RESET>;
205			status = "disabled";
206
207			porta: gpio-controller@0 {
208				compatible = "snps,dw-apb-gpio-port";
209				gpio-controller;
210				#gpio-cells = <2>;
211				snps,nr-gpios = <24>;
212				reg = <0>;
213				interrupt-controller;
214				#interrupt-cells = <2>;
215				interrupts = <0 110 4>;
216			};
217		};
218
219		gpio1: gpio@ffc03300 {
220			#address-cells = <1>;
221			#size-cells = <0>;
222			compatible = "snps,dw-apb-gpio";
223			reg = <0xffc03300 0x100>;
224			resets = <&rst GPIO1_RESET>;
225			status = "disabled";
226
227			portb: gpio-controller@0 {
228				compatible = "snps,dw-apb-gpio-port";
229				gpio-controller;
230				#gpio-cells = <2>;
231				snps,nr-gpios = <24>;
232				reg = <0>;
233				interrupt-controller;
234				#interrupt-cells = <2>;
235				interrupts = <0 111 4>;
236			};
237		};
238
239		i2c0: i2c@ffc02800 {
240			#address-cells = <1>;
241			#size-cells = <0>;
242			compatible = "snps,designware-i2c";
243			reg = <0xffc02800 0x100>;
244			interrupts = <0 103 4>;
245			resets = <&rst I2C0_RESET>;
246			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
247			status = "disabled";
248		};
249
250		i2c1: i2c@ffc02900 {
251			#address-cells = <1>;
252			#size-cells = <0>;
253			compatible = "snps,designware-i2c";
254			reg = <0xffc02900 0x100>;
255			interrupts = <0 104 4>;
256			resets = <&rst I2C1_RESET>;
257			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
258			status = "disabled";
259		};
260
261		i2c2: i2c@ffc02a00 {
262			#address-cells = <1>;
263			#size-cells = <0>;
264			compatible = "snps,designware-i2c";
265			reg = <0xffc02a00 0x100>;
266			interrupts = <0 105 4>;
267			resets = <&rst I2C2_RESET>;
268			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
269			status = "disabled";
270		};
271
272		i2c3: i2c@ffc02b00 {
273			#address-cells = <1>;
274			#size-cells = <0>;
275			compatible = "snps,designware-i2c";
276			reg = <0xffc02b00 0x100>;
277			interrupts = <0 106 4>;
278			resets = <&rst I2C3_RESET>;
279			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
280			status = "disabled";
281		};
282
283		i2c4: i2c@ffc02c00 {
284			#address-cells = <1>;
285			#size-cells = <0>;
286			compatible = "snps,designware-i2c";
287			reg = <0xffc02c00 0x100>;
288			interrupts = <0 107 4>;
289			resets = <&rst I2C4_RESET>;
290			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
291			status = "disabled";
292		};
293
294		mmc: dwmmc0@ff808000 {
295			#address-cells = <1>;
296			#size-cells = <0>;
297			compatible = "altr,socfpga-dw-mshc";
298			reg = <0xff808000 0x1000>;
299			interrupts = <0 96 4>;
300			fifo-depth = <0x400>;
301			resets = <&rst SDMMC_RESET>;
302			reset-names = "reset";
303			clocks = <&clkmgr STRATIX10_L4_MP_CLK>,
304				 <&clkmgr STRATIX10_SDMMC_CLK>;
305			clock-names = "biu", "ciu";
306			status = "disabled";
307		};
308
309		ocram: sram@ffe00000 {
310			compatible = "mmio-sram";
311			reg = <0xffe00000 0x100000>;
312		};
313
314		pdma: pdma@ffda0000 {
315			compatible = "arm,pl330", "arm,primecell";
316			reg = <0xffda0000 0x1000>;
317			interrupts = <0 81 4>,
318				     <0 82 4>,
319				     <0 83 4>,
320				     <0 84 4>,
321				     <0 85 4>,
322				     <0 86 4>,
323				     <0 87 4>,
324				     <0 88 4>,
325				     <0 89 4>;
326			#dma-cells = <1>;
327			#dma-channels = <8>;
328			#dma-requests = <32>;
329			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
330			clock-names = "apb_pclk";
331		};
332
333		rst: rstmgr@ffd11000 {
334			#reset-cells = <1>;
335			compatible = "altr,stratix10-rst-mgr";
336			reg = <0xffd11000 0x1000>;
337		};
338
339		spi0: spi@ffda4000 {
340			compatible = "snps,dw-apb-ssi";
341			#address-cells = <1>;
342			#size-cells = <0>;
343			reg = <0xffda4000 0x1000>;
344			interrupts = <0 99 4>;
345			resets = <&rst SPIM0_RESET>;
346			reg-io-width = <4>;
347			num-cs = <4>;
348			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
349			status = "disabled";
350		};
351
352		spi1: spi@ffda5000 {
353			compatible = "snps,dw-apb-ssi";
354			#address-cells = <1>;
355			#size-cells = <0>;
356			reg = <0xffda5000 0x1000>;
357			interrupts = <0 100 4>;
358			resets = <&rst SPIM1_RESET>;
359			reg-io-width = <4>;
360			num-cs = <4>;
361			clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>;
362			status = "disabled";
363		};
364
365		sysmgr: sysmgr@ffd12000 {
366			compatible = "altr,sys-mgr", "syscon";
367			reg = <0xffd12000 0x228>;
368		};
369
370		/* Local timer */
371		timer {
372			compatible = "arm,armv8-timer";
373			interrupts = <1 13 0xf08>,
374				     <1 14 0xf08>,
375				     <1 11 0xf08>,
376				     <1 10 0xf08>;
377		};
378
379		timer0: timer0@ffc03000 {
380			compatible = "snps,dw-apb-timer";
381			interrupts = <0 113 4>;
382			reg = <0xffc03000 0x100>;
383			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
384			clock-names = "timer";
385		};
386
387		timer1: timer1@ffc03100 {
388			compatible = "snps,dw-apb-timer";
389			interrupts = <0 114 4>;
390			reg = <0xffc03100 0x100>;
391			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
392			clock-names = "timer";
393		};
394
395		timer2: timer2@ffd00000 {
396			compatible = "snps,dw-apb-timer";
397			interrupts = <0 115 4>;
398			reg = <0xffd00000 0x100>;
399			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
400			clock-names = "timer";
401		};
402
403		timer3: timer3@ffd00100 {
404			compatible = "snps,dw-apb-timer";
405			interrupts = <0 116 4>;
406			reg = <0xffd00100 0x100>;
407			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
408			clock-names = "timer";
409		};
410
411		uart0: serial0@ffc02000 {
412			compatible = "snps,dw-apb-uart";
413			reg = <0xffc02000 0x100>;
414			interrupts = <0 108 4>;
415			reg-shift = <2>;
416			reg-io-width = <4>;
417			resets = <&rst UART0_RESET>;
418			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
419			status = "disabled";
420		};
421
422		uart1: serial1@ffc02100 {
423			compatible = "snps,dw-apb-uart";
424			reg = <0xffc02100 0x100>;
425			interrupts = <0 109 4>;
426			reg-shift = <2>;
427			reg-io-width = <4>;
428			resets = <&rst UART1_RESET>;
429			clocks = <&clkmgr STRATIX10_L4_SP_CLK>;
430			status = "disabled";
431		};
432
433		usbphy0: usbphy@0 {
434			#phy-cells = <0>;
435			compatible = "usb-nop-xceiv";
436			status = "okay";
437		};
438
439		usb0: usb@ffb00000 {
440			compatible = "snps,dwc2";
441			reg = <0xffb00000 0x40000>;
442			interrupts = <0 93 4>;
443			phys = <&usbphy0>;
444			phy-names = "usb2-phy";
445			resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
446			reset-names = "dwc2", "dwc2-ecc";
447			clocks = <&clkmgr STRATIX10_USB_CLK>;
448			status = "disabled";
449		};
450
451		usb1: usb@ffb40000 {
452			compatible = "snps,dwc2";
453			reg = <0xffb40000 0x40000>;
454			interrupts = <0 94 4>;
455			phys = <&usbphy0>;
456			phy-names = "usb2-phy";
457			resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
458			reset-names = "dwc2", "dwc2-ecc";
459			clocks = <&clkmgr STRATIX10_USB_CLK>;
460			status = "disabled";
461		};
462
463		watchdog0: watchdog@ffd00200 {
464			compatible = "snps,dw-wdt";
465			reg = <0xffd00200 0x100>;
466			interrupts = <0 117 4>;
467			resets = <&rst WATCHDOG0_RESET>;
468			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
469			status = "disabled";
470		};
471
472		watchdog1: watchdog@ffd00300 {
473			compatible = "snps,dw-wdt";
474			reg = <0xffd00300 0x100>;
475			interrupts = <0 118 4>;
476			resets = <&rst WATCHDOG1_RESET>;
477			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
478			status = "disabled";
479		};
480
481		watchdog2: watchdog@ffd00400 {
482			compatible = "snps,dw-wdt";
483			reg = <0xffd00400 0x100>;
484			interrupts = <0 125 4>;
485			resets = <&rst WATCHDOG2_RESET>;
486			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
487			status = "disabled";
488		};
489
490		watchdog3: watchdog@ffd00500 {
491			compatible = "snps,dw-wdt";
492			reg = <0xffd00500 0x100>;
493			interrupts = <0 126 4>;
494			resets = <&rst WATCHDOG3_RESET>;
495			clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>;
496			status = "disabled";
497		};
498
499		sdr: sdr@f8011100 {
500			compatible = "altr,sdr-ctl", "syscon";
501			reg = <0xf8011100 0xc0>;
502		};
503
504		eccmgr {
505			compatible = "altr,socfpga-a10-ecc-manager";
506			altr,sysmgr-syscon = <&sysmgr>;
507			#address-cells = <1>;
508			#size-cells = <1>;
509			interrupts = <0 15 4>, <0 95 4>;
510			interrupt-controller;
511			#interrupt-cells = <2>;
512			ranges;
513
514			sdramedac {
515				compatible = "altr,sdram-edac-s10";
516				altr,sdr-syscon = <&sdr>;
517				interrupts = <16 4>, <48 4>;
518			};
519
520			usb0-ecc@ff8c4000 {
521				compatible = "altr,socfpga-usb-ecc";
522				reg = <0xff8c4000 0x100>;
523				altr,ecc-parent = <&usb0>;
524				interrupts = <2 4>,
525					     <34 4>;
526			};
527
528			emac0-rx-ecc@ff8c0000 {
529				compatible = "altr,socfpga-eth-mac-ecc";
530				reg = <0xff8c0000 0x100>;
531				altr,ecc-parent = <&gmac0>;
532				interrupts = <4 4>,
533					     <36 4>;
534			};
535
536			emac0-tx-ecc@ff8c0400 {
537				compatible = "altr,socfpga-eth-mac-ecc";
538				reg = <0xff8c0400 0x100>;
539				altr,ecc-parent = <&gmac0>;
540				interrupts = <5 4>,
541					     <37 4>;
542			};
543
544		};
545
546		qspi: spi@ff8d2000 {
547			compatible = "cdns,qspi-nor";
548			#address-cells = <1>;
549			#size-cells = <0>;
550			reg = <0xff8d2000 0x100>,
551			      <0xff900000 0x100000>;
552			interrupts = <0 3 4>;
553			cdns,fifo-depth = <128>;
554			cdns,fifo-width = <4>;
555			cdns,trigger-address = <0x00000000>;
556			clocks = <&qspi_clk>;
557
558			status = "disabled";
559		};
560
561		firmware {
562			svc {
563				compatible = "intel,stratix10-svc";
564				method = "smc";
565				memory-region = <&service_reserved>;
566
567				fpga_mgr: fpga-mgr {
568					compatible = "intel,stratix10-soc-fpga-mgr";
569				};
570			};
571		};
572	};
573};
574