178cd6a9dSDinh Nguyen/* 278cd6a9dSDinh Nguyen * Copyright Altera Corporation (C) 2015. All rights reserved. 378cd6a9dSDinh Nguyen * 478cd6a9dSDinh Nguyen * This program is free software; you can redistribute it and/or modify 578cd6a9dSDinh Nguyen * it under the terms and conditions of the GNU General Public License, 678cd6a9dSDinh Nguyen * version 2, as published by the Free Software Foundation. 778cd6a9dSDinh Nguyen * 878cd6a9dSDinh Nguyen * This program is distributed in the hope it will be useful, but WITHOUT 978cd6a9dSDinh Nguyen * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1078cd6a9dSDinh Nguyen * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1178cd6a9dSDinh Nguyen * more details. 1278cd6a9dSDinh Nguyen * 1378cd6a9dSDinh Nguyen * You should have received a copy of the GNU General Public License along with 1478cd6a9dSDinh Nguyen * this program. If not, see <http://www.gnu.org/licenses/>. 1578cd6a9dSDinh Nguyen */ 1678cd6a9dSDinh Nguyen 1778cd6a9dSDinh Nguyen/dts-v1/; 18e519922eSDinh Nguyen#include <dt-bindings/reset/altr,rst-mgr-s10.h> 195a0e622eSAlan Tull#include <dt-bindings/gpio/gpio.h> 20d93101abSDinh Nguyen#include <dt-bindings/clock/stratix10-clock.h> 2178cd6a9dSDinh Nguyen 2278cd6a9dSDinh Nguyen/ { 2378cd6a9dSDinh Nguyen compatible = "altr,socfpga-stratix10"; 2478cd6a9dSDinh Nguyen #address-cells = <2>; 2578cd6a9dSDinh Nguyen #size-cells = <2>; 2678cd6a9dSDinh Nguyen 27adb9e354SRichard Gong reserved-memory { 28adb9e354SRichard Gong #address-cells = <2>; 29adb9e354SRichard Gong #size-cells = <2>; 30adb9e354SRichard Gong ranges; 31adb9e354SRichard Gong 32adb9e354SRichard Gong service_reserved: svcbuffer@0 { 33adb9e354SRichard Gong compatible = "shared-dma-pool"; 34adb9e354SRichard Gong reg = <0x0 0x0 0x0 0x1000000>; 35adb9e354SRichard Gong alignment = <0x1000>; 36adb9e354SRichard Gong no-map; 37adb9e354SRichard Gong }; 38adb9e354SRichard Gong }; 39adb9e354SRichard Gong 4078cd6a9dSDinh Nguyen cpus { 4178cd6a9dSDinh Nguyen #address-cells = <1>; 4278cd6a9dSDinh Nguyen #size-cells = <0>; 4378cd6a9dSDinh Nguyen 4478cd6a9dSDinh Nguyen cpu0: cpu@0 { 4578cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 4678cd6a9dSDinh Nguyen device_type = "cpu"; 4778cd6a9dSDinh Nguyen enable-method = "psci"; 4878cd6a9dSDinh Nguyen reg = <0x0>; 4978cd6a9dSDinh Nguyen }; 5078cd6a9dSDinh Nguyen 5178cd6a9dSDinh Nguyen cpu1: cpu@1 { 5278cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 5378cd6a9dSDinh Nguyen device_type = "cpu"; 5478cd6a9dSDinh Nguyen enable-method = "psci"; 5578cd6a9dSDinh Nguyen reg = <0x1>; 5678cd6a9dSDinh Nguyen }; 5778cd6a9dSDinh Nguyen 5878cd6a9dSDinh Nguyen cpu2: cpu@2 { 5978cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 6078cd6a9dSDinh Nguyen device_type = "cpu"; 6178cd6a9dSDinh Nguyen enable-method = "psci"; 6278cd6a9dSDinh Nguyen reg = <0x2>; 6378cd6a9dSDinh Nguyen }; 6478cd6a9dSDinh Nguyen 6578cd6a9dSDinh Nguyen cpu3: cpu@3 { 6678cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 6778cd6a9dSDinh Nguyen device_type = "cpu"; 6878cd6a9dSDinh Nguyen enable-method = "psci"; 6978cd6a9dSDinh Nguyen reg = <0x3>; 7078cd6a9dSDinh Nguyen }; 7178cd6a9dSDinh Nguyen }; 7278cd6a9dSDinh Nguyen 7378cd6a9dSDinh Nguyen pmu { 7478cd6a9dSDinh Nguyen compatible = "arm,armv8-pmuv3"; 7578cd6a9dSDinh Nguyen interrupts = <0 120 8>, 7678cd6a9dSDinh Nguyen <0 121 8>, 7778cd6a9dSDinh Nguyen <0 122 8>, 7878cd6a9dSDinh Nguyen <0 123 8>; 7978cd6a9dSDinh Nguyen interrupt-affinity = <&cpu0>, 8078cd6a9dSDinh Nguyen <&cpu1>, 8178cd6a9dSDinh Nguyen <&cpu2>, 8278cd6a9dSDinh Nguyen <&cpu3>; 8369c4d8edSArnd Bergmann interrupt-parent = <&intc>; 8478cd6a9dSDinh Nguyen }; 8578cd6a9dSDinh Nguyen 8678cd6a9dSDinh Nguyen psci { 8778cd6a9dSDinh Nguyen compatible = "arm,psci-0.2"; 8878cd6a9dSDinh Nguyen method = "smc"; 8978cd6a9dSDinh Nguyen }; 9078cd6a9dSDinh Nguyen 9178cd6a9dSDinh Nguyen intc: intc@fffc1000 { 9278cd6a9dSDinh Nguyen compatible = "arm,gic-400", "arm,cortex-a15-gic"; 9378cd6a9dSDinh Nguyen #interrupt-cells = <3>; 9478cd6a9dSDinh Nguyen interrupt-controller; 95f973bfa0SDinh Nguyen reg = <0x0 0xfffc1000 0x0 0x1000>, 96f973bfa0SDinh Nguyen <0x0 0xfffc2000 0x0 0x2000>, 97f973bfa0SDinh Nguyen <0x0 0xfffc4000 0x0 0x2000>, 98f973bfa0SDinh Nguyen <0x0 0xfffc6000 0x0 0x2000>; 9978cd6a9dSDinh Nguyen }; 10078cd6a9dSDinh Nguyen 10178cd6a9dSDinh Nguyen soc { 10278cd6a9dSDinh Nguyen #address-cells = <1>; 10378cd6a9dSDinh Nguyen #size-cells = <1>; 10478cd6a9dSDinh Nguyen compatible = "simple-bus"; 10578cd6a9dSDinh Nguyen device_type = "soc"; 10678cd6a9dSDinh Nguyen interrupt-parent = <&intc>; 10778cd6a9dSDinh Nguyen ranges = <0 0 0 0xffffffff>; 10878cd6a9dSDinh Nguyen 109919d1100SAlan Tull base_fpga_region { 110919d1100SAlan Tull #address-cells = <0x1>; 111919d1100SAlan Tull #size-cells = <0x1>; 112919d1100SAlan Tull 113919d1100SAlan Tull compatible = "fpga-region"; 114919d1100SAlan Tull fpga-mgr = <&fpga_mgr>; 115919d1100SAlan Tull }; 116919d1100SAlan Tull 117d93101abSDinh Nguyen clkmgr: clock-controller@ffd10000 { 118d93101abSDinh Nguyen compatible = "intel,stratix10-clkmgr"; 11978cd6a9dSDinh Nguyen reg = <0xffd10000 0x1000>; 120d93101abSDinh Nguyen #clock-cells = <1>; 121d93101abSDinh Nguyen }; 122d93101abSDinh Nguyen 123d93101abSDinh Nguyen clocks { 124d93101abSDinh Nguyen cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 125d93101abSDinh Nguyen #clock-cells = <0>; 126d93101abSDinh Nguyen compatible = "fixed-clock"; 127d93101abSDinh Nguyen }; 128d93101abSDinh Nguyen 129d93101abSDinh Nguyen cb_intosc_ls_clk: cb-intosc-ls-clk { 130d93101abSDinh Nguyen #clock-cells = <0>; 131d93101abSDinh Nguyen compatible = "fixed-clock"; 132d93101abSDinh Nguyen }; 133d93101abSDinh Nguyen 134d93101abSDinh Nguyen f2s_free_clk: f2s-free-clk { 135d93101abSDinh Nguyen #clock-cells = <0>; 136d93101abSDinh Nguyen compatible = "fixed-clock"; 137d93101abSDinh Nguyen }; 138d93101abSDinh Nguyen 139d93101abSDinh Nguyen osc1: osc1 { 140d93101abSDinh Nguyen #clock-cells = <0>; 141d93101abSDinh Nguyen compatible = "fixed-clock"; 142d93101abSDinh Nguyen }; 1430cb140d0SThor Thayer 1440cb140d0SThor Thayer qspi_clk: qspi-clk { 1450cb140d0SThor Thayer #clock-cells = <0>; 1460cb140d0SThor Thayer compatible = "fixed-clock"; 1470cb140d0SThor Thayer clock-frequency = <200000000>; 1480cb140d0SThor Thayer }; 14978cd6a9dSDinh Nguyen }; 15078cd6a9dSDinh Nguyen 15178cd6a9dSDinh Nguyen gmac0: ethernet@ff800000 { 15278cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 15378cd6a9dSDinh Nguyen reg = <0xff800000 0x2000>; 15478cd6a9dSDinh Nguyen interrupts = <0 90 4>; 15578cd6a9dSDinh Nguyen interrupt-names = "macirq"; 15678cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 15705690e8aSDinh Nguyen resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 15805690e8aSDinh Nguyen reset-names = "stmmaceth", "stmmaceth-ocp"; 159d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_EMAC0_CLK>; 160d93101abSDinh Nguyen clock-names = "stmmaceth"; 161a27460c9SThor Thayer tx-fifo-depth = <16384>; 162a27460c9SThor Thayer rx-fifo-depth = <16384>; 163fd5ba6eeSAaro Koskinen snps,multicast-filter-bins = <256>; 164ae3f46c8SThor Thayer iommus = <&smmu 1>; 16578cd6a9dSDinh Nguyen status = "disabled"; 16678cd6a9dSDinh Nguyen }; 16778cd6a9dSDinh Nguyen 16878cd6a9dSDinh Nguyen gmac1: ethernet@ff802000 { 16978cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 17078cd6a9dSDinh Nguyen reg = <0xff802000 0x2000>; 17178cd6a9dSDinh Nguyen interrupts = <0 91 4>; 17278cd6a9dSDinh Nguyen interrupt-names = "macirq"; 17378cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 17405690e8aSDinh Nguyen resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 17505690e8aSDinh Nguyen reset-names = "stmmaceth", "stmmaceth-ocp"; 176d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_EMAC1_CLK>; 177d93101abSDinh Nguyen clock-names = "stmmaceth"; 178a27460c9SThor Thayer tx-fifo-depth = <16384>; 179a27460c9SThor Thayer rx-fifo-depth = <16384>; 180fd5ba6eeSAaro Koskinen snps,multicast-filter-bins = <256>; 181ae3f46c8SThor Thayer iommus = <&smmu 2>; 18278cd6a9dSDinh Nguyen status = "disabled"; 18378cd6a9dSDinh Nguyen }; 18478cd6a9dSDinh Nguyen 18578cd6a9dSDinh Nguyen gmac2: ethernet@ff804000 { 18678cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 18778cd6a9dSDinh Nguyen reg = <0xff804000 0x2000>; 18878cd6a9dSDinh Nguyen interrupts = <0 92 4>; 18978cd6a9dSDinh Nguyen interrupt-names = "macirq"; 19078cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 19105690e8aSDinh Nguyen resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 19205690e8aSDinh Nguyen reset-names = "stmmaceth", "stmmaceth-ocp"; 193d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_EMAC2_CLK>; 194d93101abSDinh Nguyen clock-names = "stmmaceth"; 195a27460c9SThor Thayer tx-fifo-depth = <16384>; 196a27460c9SThor Thayer rx-fifo-depth = <16384>; 197fd5ba6eeSAaro Koskinen snps,multicast-filter-bins = <256>; 198ae3f46c8SThor Thayer iommus = <&smmu 3>; 19978cd6a9dSDinh Nguyen status = "disabled"; 20078cd6a9dSDinh Nguyen }; 20178cd6a9dSDinh Nguyen 20278cd6a9dSDinh Nguyen gpio0: gpio@ffc03200 { 20378cd6a9dSDinh Nguyen #address-cells = <1>; 20478cd6a9dSDinh Nguyen #size-cells = <0>; 20578cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio"; 20678cd6a9dSDinh Nguyen reg = <0xffc03200 0x100>; 207788251faSDinh Nguyen resets = <&rst GPIO0_RESET>; 20878cd6a9dSDinh Nguyen status = "disabled"; 20978cd6a9dSDinh Nguyen 21078cd6a9dSDinh Nguyen porta: gpio-controller@0 { 21178cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio-port"; 21278cd6a9dSDinh Nguyen gpio-controller; 21378cd6a9dSDinh Nguyen #gpio-cells = <2>; 21478cd6a9dSDinh Nguyen snps,nr-gpios = <24>; 21578cd6a9dSDinh Nguyen reg = <0>; 21678cd6a9dSDinh Nguyen interrupt-controller; 21778cd6a9dSDinh Nguyen #interrupt-cells = <2>; 21878cd6a9dSDinh Nguyen interrupts = <0 110 4>; 21978cd6a9dSDinh Nguyen }; 22078cd6a9dSDinh Nguyen }; 22178cd6a9dSDinh Nguyen 22278cd6a9dSDinh Nguyen gpio1: gpio@ffc03300 { 22378cd6a9dSDinh Nguyen #address-cells = <1>; 22478cd6a9dSDinh Nguyen #size-cells = <0>; 22578cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio"; 22678cd6a9dSDinh Nguyen reg = <0xffc03300 0x100>; 227788251faSDinh Nguyen resets = <&rst GPIO1_RESET>; 22878cd6a9dSDinh Nguyen status = "disabled"; 22978cd6a9dSDinh Nguyen 23078cd6a9dSDinh Nguyen portb: gpio-controller@0 { 23178cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio-port"; 23278cd6a9dSDinh Nguyen gpio-controller; 23378cd6a9dSDinh Nguyen #gpio-cells = <2>; 23478cd6a9dSDinh Nguyen snps,nr-gpios = <24>; 23578cd6a9dSDinh Nguyen reg = <0>; 23678cd6a9dSDinh Nguyen interrupt-controller; 23778cd6a9dSDinh Nguyen #interrupt-cells = <2>; 238a067fb42SDinh Nguyen interrupts = <0 111 4>; 23978cd6a9dSDinh Nguyen }; 24078cd6a9dSDinh Nguyen }; 24178cd6a9dSDinh Nguyen 24278cd6a9dSDinh Nguyen i2c0: i2c@ffc02800 { 24378cd6a9dSDinh Nguyen #address-cells = <1>; 24478cd6a9dSDinh Nguyen #size-cells = <0>; 24578cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 24678cd6a9dSDinh Nguyen reg = <0xffc02800 0x100>; 24778cd6a9dSDinh Nguyen interrupts = <0 103 4>; 248788251faSDinh Nguyen resets = <&rst I2C0_RESET>; 249eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 25078cd6a9dSDinh Nguyen status = "disabled"; 25178cd6a9dSDinh Nguyen }; 25278cd6a9dSDinh Nguyen 25378cd6a9dSDinh Nguyen i2c1: i2c@ffc02900 { 25478cd6a9dSDinh Nguyen #address-cells = <1>; 25578cd6a9dSDinh Nguyen #size-cells = <0>; 25678cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 25778cd6a9dSDinh Nguyen reg = <0xffc02900 0x100>; 25878cd6a9dSDinh Nguyen interrupts = <0 104 4>; 259788251faSDinh Nguyen resets = <&rst I2C1_RESET>; 260eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 26178cd6a9dSDinh Nguyen status = "disabled"; 26278cd6a9dSDinh Nguyen }; 26378cd6a9dSDinh Nguyen 26478cd6a9dSDinh Nguyen i2c2: i2c@ffc02a00 { 26578cd6a9dSDinh Nguyen #address-cells = <1>; 26678cd6a9dSDinh Nguyen #size-cells = <0>; 26778cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 26878cd6a9dSDinh Nguyen reg = <0xffc02a00 0x100>; 26978cd6a9dSDinh Nguyen interrupts = <0 105 4>; 270788251faSDinh Nguyen resets = <&rst I2C2_RESET>; 271eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 27278cd6a9dSDinh Nguyen status = "disabled"; 27378cd6a9dSDinh Nguyen }; 27478cd6a9dSDinh Nguyen 27578cd6a9dSDinh Nguyen i2c3: i2c@ffc02b00 { 27678cd6a9dSDinh Nguyen #address-cells = <1>; 27778cd6a9dSDinh Nguyen #size-cells = <0>; 27878cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 27978cd6a9dSDinh Nguyen reg = <0xffc02b00 0x100>; 28078cd6a9dSDinh Nguyen interrupts = <0 106 4>; 281788251faSDinh Nguyen resets = <&rst I2C3_RESET>; 282eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 28378cd6a9dSDinh Nguyen status = "disabled"; 28478cd6a9dSDinh Nguyen }; 28578cd6a9dSDinh Nguyen 28678cd6a9dSDinh Nguyen i2c4: i2c@ffc02c00 { 28778cd6a9dSDinh Nguyen #address-cells = <1>; 28878cd6a9dSDinh Nguyen #size-cells = <0>; 28978cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 29078cd6a9dSDinh Nguyen reg = <0xffc02c00 0x100>; 29178cd6a9dSDinh Nguyen interrupts = <0 107 4>; 292788251faSDinh Nguyen resets = <&rst I2C4_RESET>; 293eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 29478cd6a9dSDinh Nguyen status = "disabled"; 29578cd6a9dSDinh Nguyen }; 29678cd6a9dSDinh Nguyen 29778cd6a9dSDinh Nguyen mmc: dwmmc0@ff808000 { 29878cd6a9dSDinh Nguyen #address-cells = <1>; 29978cd6a9dSDinh Nguyen #size-cells = <0>; 30078cd6a9dSDinh Nguyen compatible = "altr,socfpga-dw-mshc"; 30178cd6a9dSDinh Nguyen reg = <0xff808000 0x1000>; 30278cd6a9dSDinh Nguyen interrupts = <0 96 4>; 30378cd6a9dSDinh Nguyen fifo-depth = <0x400>; 304788251faSDinh Nguyen resets = <&rst SDMMC_RESET>; 305788251faSDinh Nguyen reset-names = "reset"; 306d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_MP_CLK>, 307d93101abSDinh Nguyen <&clkmgr STRATIX10_SDMMC_CLK>; 308d93101abSDinh Nguyen clock-names = "biu", "ciu"; 309ae3f46c8SThor Thayer iommus = <&smmu 5>; 31078cd6a9dSDinh Nguyen status = "disabled"; 31178cd6a9dSDinh Nguyen }; 31278cd6a9dSDinh Nguyen 31378cd6a9dSDinh Nguyen ocram: sram@ffe00000 { 31478cd6a9dSDinh Nguyen compatible = "mmio-sram"; 31578cd6a9dSDinh Nguyen reg = <0xffe00000 0x100000>; 31678cd6a9dSDinh Nguyen }; 31778cd6a9dSDinh Nguyen 318ab50a444SGraham Moore pdma: pdma@ffda0000 { 319ab50a444SGraham Moore compatible = "arm,pl330", "arm,primecell"; 320ab50a444SGraham Moore reg = <0xffda0000 0x1000>; 321ab50a444SGraham Moore interrupts = <0 81 4>, 322ab50a444SGraham Moore <0 82 4>, 323ab50a444SGraham Moore <0 83 4>, 324ab50a444SGraham Moore <0 84 4>, 325ab50a444SGraham Moore <0 85 4>, 326ab50a444SGraham Moore <0 86 4>, 327ab50a444SGraham Moore <0 87 4>, 328ab50a444SGraham Moore <0 88 4>, 329ab50a444SGraham Moore <0 89 4>; 330ab50a444SGraham Moore #dma-cells = <1>; 331ab50a444SGraham Moore #dma-channels = <8>; 332ab50a444SGraham Moore #dma-requests = <32>; 333ab50a444SGraham Moore clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 334ab50a444SGraham Moore clock-names = "apb_pclk"; 335ab50a444SGraham Moore }; 336ab50a444SGraham Moore 33778cd6a9dSDinh Nguyen rst: rstmgr@ffd11000 { 33878cd6a9dSDinh Nguyen #reset-cells = <1>; 3398bb4f3f5SDinh Nguyen compatible = "altr,stratix10-rst-mgr"; 34078cd6a9dSDinh Nguyen reg = <0xffd11000 0x1000>; 34178cd6a9dSDinh Nguyen }; 34278cd6a9dSDinh Nguyen 343ae3f46c8SThor Thayer smmu: iommu@fa000000 { 344ae3f46c8SThor Thayer compatible = "arm,mmu-500", "arm,smmu-v2"; 345ae3f46c8SThor Thayer reg = <0xfa000000 0x40000>; 346ae3f46c8SThor Thayer #global-interrupts = <2>; 347ae3f46c8SThor Thayer #iommu-cells = <1>; 348ae3f46c8SThor Thayer clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 349ae3f46c8SThor Thayer clock-names = "iommu"; 350ae3f46c8SThor Thayer interrupt-parent = <&intc>; 351ae3f46c8SThor Thayer interrupts = <0 128 4>, /* Global Secure Fault */ 352ae3f46c8SThor Thayer <0 129 4>, /* Global Non-secure Fault */ 353ae3f46c8SThor Thayer /* Non-secure Context Interrupts (32) */ 354ae3f46c8SThor Thayer <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 355ae3f46c8SThor Thayer <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 356ae3f46c8SThor Thayer <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 357ae3f46c8SThor Thayer <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 358ae3f46c8SThor Thayer <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 359ae3f46c8SThor Thayer <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 360ae3f46c8SThor Thayer <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 361ae3f46c8SThor Thayer <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 362ae3f46c8SThor Thayer stream-match-mask = <0x7ff0>; 363ae3f46c8SThor Thayer status = "disabled"; 364ae3f46c8SThor Thayer }; 365ae3f46c8SThor Thayer 36678cd6a9dSDinh Nguyen spi0: spi@ffda4000 { 36778cd6a9dSDinh Nguyen compatible = "snps,dw-apb-ssi"; 36878cd6a9dSDinh Nguyen #address-cells = <1>; 36978cd6a9dSDinh Nguyen #size-cells = <0>; 37078cd6a9dSDinh Nguyen reg = <0xffda4000 0x1000>; 371889d1509SThor Thayer interrupts = <0 99 4>; 372889d1509SThor Thayer resets = <&rst SPIM0_RESET>; 373889d1509SThor Thayer reg-io-width = <4>; 3744595299cSThor Thayer num-cs = <4>; 37570455ac7SThor Thayer clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 37678cd6a9dSDinh Nguyen status = "disabled"; 37778cd6a9dSDinh Nguyen }; 37878cd6a9dSDinh Nguyen 37978cd6a9dSDinh Nguyen spi1: spi@ffda5000 { 38078cd6a9dSDinh Nguyen compatible = "snps,dw-apb-ssi"; 38178cd6a9dSDinh Nguyen #address-cells = <1>; 38278cd6a9dSDinh Nguyen #size-cells = <0>; 38378cd6a9dSDinh Nguyen reg = <0xffda5000 0x1000>; 384889d1509SThor Thayer interrupts = <0 100 4>; 385889d1509SThor Thayer resets = <&rst SPIM1_RESET>; 386889d1509SThor Thayer reg-io-width = <4>; 3874595299cSThor Thayer num-cs = <4>; 38870455ac7SThor Thayer clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 38978cd6a9dSDinh Nguyen status = "disabled"; 39078cd6a9dSDinh Nguyen }; 39178cd6a9dSDinh Nguyen 39278cd6a9dSDinh Nguyen sysmgr: sysmgr@ffd12000 { 39378cd6a9dSDinh Nguyen compatible = "altr,sys-mgr", "syscon"; 39474121b9aSThor Thayer reg = <0xffd12000 0x228>; 39578cd6a9dSDinh Nguyen }; 39678cd6a9dSDinh Nguyen 39778cd6a9dSDinh Nguyen /* Local timer */ 39878cd6a9dSDinh Nguyen timer { 39978cd6a9dSDinh Nguyen compatible = "arm,armv8-timer"; 400f2a89d3bSMarc Zyngier interrupts = <1 13 0xf08>, 401f2a89d3bSMarc Zyngier <1 14 0xf08>, 402f2a89d3bSMarc Zyngier <1 11 0xf08>, 403f2a89d3bSMarc Zyngier <1 10 0xf08>; 40478cd6a9dSDinh Nguyen }; 40578cd6a9dSDinh Nguyen 40678cd6a9dSDinh Nguyen timer0: timer0@ffc03000 { 40778cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 40878cd6a9dSDinh Nguyen interrupts = <0 113 4>; 40978cd6a9dSDinh Nguyen reg = <0xffc03000 0x100>; 410d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 411d93101abSDinh Nguyen clock-names = "timer"; 41278cd6a9dSDinh Nguyen }; 41378cd6a9dSDinh Nguyen 41478cd6a9dSDinh Nguyen timer1: timer1@ffc03100 { 41578cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 41678cd6a9dSDinh Nguyen interrupts = <0 114 4>; 41778cd6a9dSDinh Nguyen reg = <0xffc03100 0x100>; 418d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 419d93101abSDinh Nguyen clock-names = "timer"; 42078cd6a9dSDinh Nguyen }; 42178cd6a9dSDinh Nguyen 42278cd6a9dSDinh Nguyen timer2: timer2@ffd00000 { 42378cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 42478cd6a9dSDinh Nguyen interrupts = <0 115 4>; 42578cd6a9dSDinh Nguyen reg = <0xffd00000 0x100>; 426d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 427d93101abSDinh Nguyen clock-names = "timer"; 42878cd6a9dSDinh Nguyen }; 42978cd6a9dSDinh Nguyen 43078cd6a9dSDinh Nguyen timer3: timer3@ffd00100 { 43178cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 43278cd6a9dSDinh Nguyen interrupts = <0 116 4>; 43378cd6a9dSDinh Nguyen reg = <0xffd00100 0x100>; 434d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 435d93101abSDinh Nguyen clock-names = "timer"; 43678cd6a9dSDinh Nguyen }; 43778cd6a9dSDinh Nguyen 43878cd6a9dSDinh Nguyen uart0: serial0@ffc02000 { 43978cd6a9dSDinh Nguyen compatible = "snps,dw-apb-uart"; 44078cd6a9dSDinh Nguyen reg = <0xffc02000 0x100>; 44178cd6a9dSDinh Nguyen interrupts = <0 108 4>; 44278cd6a9dSDinh Nguyen reg-shift = <2>; 44378cd6a9dSDinh Nguyen reg-io-width = <4>; 444788251faSDinh Nguyen resets = <&rst UART0_RESET>; 445d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 44678cd6a9dSDinh Nguyen status = "disabled"; 44778cd6a9dSDinh Nguyen }; 44878cd6a9dSDinh Nguyen 44978cd6a9dSDinh Nguyen uart1: serial1@ffc02100 { 45078cd6a9dSDinh Nguyen compatible = "snps,dw-apb-uart"; 45178cd6a9dSDinh Nguyen reg = <0xffc02100 0x100>; 45278cd6a9dSDinh Nguyen interrupts = <0 109 4>; 45378cd6a9dSDinh Nguyen reg-shift = <2>; 45478cd6a9dSDinh Nguyen reg-io-width = <4>; 455788251faSDinh Nguyen resets = <&rst UART1_RESET>; 456d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 45778cd6a9dSDinh Nguyen status = "disabled"; 45878cd6a9dSDinh Nguyen }; 45978cd6a9dSDinh Nguyen 46078cd6a9dSDinh Nguyen usbphy0: usbphy@0 { 46178cd6a9dSDinh Nguyen #phy-cells = <0>; 46278cd6a9dSDinh Nguyen compatible = "usb-nop-xceiv"; 46378cd6a9dSDinh Nguyen status = "okay"; 46478cd6a9dSDinh Nguyen }; 46578cd6a9dSDinh Nguyen 46678cd6a9dSDinh Nguyen usb0: usb@ffb00000 { 46778cd6a9dSDinh Nguyen compatible = "snps,dwc2"; 46878cd6a9dSDinh Nguyen reg = <0xffb00000 0x40000>; 46978cd6a9dSDinh Nguyen interrupts = <0 93 4>; 47078cd6a9dSDinh Nguyen phys = <&usbphy0>; 47178cd6a9dSDinh Nguyen phy-names = "usb2-phy"; 47233af8ca0SDinh Nguyen resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 47333af8ca0SDinh Nguyen reset-names = "dwc2", "dwc2-ecc"; 47403761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_USB_CLK>; 475ae3f46c8SThor Thayer iommus = <&smmu 6>; 47678cd6a9dSDinh Nguyen status = "disabled"; 47778cd6a9dSDinh Nguyen }; 47878cd6a9dSDinh Nguyen 47978cd6a9dSDinh Nguyen usb1: usb@ffb40000 { 48078cd6a9dSDinh Nguyen compatible = "snps,dwc2"; 48178cd6a9dSDinh Nguyen reg = <0xffb40000 0x40000>; 48278cd6a9dSDinh Nguyen interrupts = <0 94 4>; 48378cd6a9dSDinh Nguyen phys = <&usbphy0>; 48478cd6a9dSDinh Nguyen phy-names = "usb2-phy"; 48533af8ca0SDinh Nguyen resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 48633af8ca0SDinh Nguyen reset-names = "dwc2", "dwc2-ecc"; 48703761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_USB_CLK>; 488ae3f46c8SThor Thayer iommus = <&smmu 7>; 48978cd6a9dSDinh Nguyen status = "disabled"; 49078cd6a9dSDinh Nguyen }; 49178cd6a9dSDinh Nguyen 49278cd6a9dSDinh Nguyen watchdog0: watchdog@ffd00200 { 49378cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 49478cd6a9dSDinh Nguyen reg = <0xffd00200 0x100>; 49578cd6a9dSDinh Nguyen interrupts = <0 117 4>; 496788251faSDinh Nguyen resets = <&rst WATCHDOG0_RESET>; 49703761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 49878cd6a9dSDinh Nguyen status = "disabled"; 49978cd6a9dSDinh Nguyen }; 50078cd6a9dSDinh Nguyen 50178cd6a9dSDinh Nguyen watchdog1: watchdog@ffd00300 { 50278cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 50378cd6a9dSDinh Nguyen reg = <0xffd00300 0x100>; 50478cd6a9dSDinh Nguyen interrupts = <0 118 4>; 505788251faSDinh Nguyen resets = <&rst WATCHDOG1_RESET>; 50603761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 50778cd6a9dSDinh Nguyen status = "disabled"; 50878cd6a9dSDinh Nguyen }; 50978cd6a9dSDinh Nguyen 51078cd6a9dSDinh Nguyen watchdog2: watchdog@ffd00400 { 51178cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 51278cd6a9dSDinh Nguyen reg = <0xffd00400 0x100>; 51378cd6a9dSDinh Nguyen interrupts = <0 125 4>; 514788251faSDinh Nguyen resets = <&rst WATCHDOG2_RESET>; 51503761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 51678cd6a9dSDinh Nguyen status = "disabled"; 51778cd6a9dSDinh Nguyen }; 51878cd6a9dSDinh Nguyen 51978cd6a9dSDinh Nguyen watchdog3: watchdog@ffd00500 { 52078cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 52178cd6a9dSDinh Nguyen reg = <0xffd00500 0x100>; 52278cd6a9dSDinh Nguyen interrupts = <0 126 4>; 523788251faSDinh Nguyen resets = <&rst WATCHDOG3_RESET>; 52403761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 52578cd6a9dSDinh Nguyen status = "disabled"; 52678cd6a9dSDinh Nguyen }; 52791fdd827SThor Thayer 528446fd7afSThor Thayer sdr: sdr@f8011100 { 529446fd7afSThor Thayer compatible = "altr,sdr-ctl", "syscon"; 530446fd7afSThor Thayer reg = <0xf8011100 0xc0>; 531446fd7afSThor Thayer }; 532446fd7afSThor Thayer 53391fdd827SThor Thayer eccmgr { 5346b2da9ffSThor Thayer compatible = "altr,socfpga-a10-ecc-manager"; 5353ce078ffSThor Thayer altr,sysmgr-syscon = <&sysmgr>; 5363ce078ffSThor Thayer #address-cells = <1>; 5373ce078ffSThor Thayer #size-cells = <1>; 53891fdd827SThor Thayer interrupts = <0 15 4>, <0 95 4>; 53991fdd827SThor Thayer interrupt-controller; 54091fdd827SThor Thayer #interrupt-cells = <2>; 5413ce078ffSThor Thayer ranges; 54291fdd827SThor Thayer 54391fdd827SThor Thayer sdramedac { 54491fdd827SThor Thayer compatible = "altr,sdram-edac-s10"; 545446fd7afSThor Thayer altr,sdr-syscon = <&sdr>; 54691fdd827SThor Thayer interrupts = <16 4>, <48 4>; 54791fdd827SThor Thayer }; 5486b2da9ffSThor Thayer 5496b2da9ffSThor Thayer usb0-ecc@ff8c4000 { 5506b2da9ffSThor Thayer compatible = "altr,socfpga-usb-ecc"; 5516b2da9ffSThor Thayer reg = <0xff8c4000 0x100>; 5526b2da9ffSThor Thayer altr,ecc-parent = <&usb0>; 5536b2da9ffSThor Thayer interrupts = <2 4>, 5546b2da9ffSThor Thayer <34 4>; 5556b2da9ffSThor Thayer }; 5566b2da9ffSThor Thayer 5576b2da9ffSThor Thayer emac0-rx-ecc@ff8c0000 { 5586b2da9ffSThor Thayer compatible = "altr,socfpga-eth-mac-ecc"; 5596b2da9ffSThor Thayer reg = <0xff8c0000 0x100>; 5606b2da9ffSThor Thayer altr,ecc-parent = <&gmac0>; 5616b2da9ffSThor Thayer interrupts = <4 4>, 5626b2da9ffSThor Thayer <36 4>; 5636b2da9ffSThor Thayer }; 5646b2da9ffSThor Thayer 5656b2da9ffSThor Thayer emac0-tx-ecc@ff8c0400 { 5666b2da9ffSThor Thayer compatible = "altr,socfpga-eth-mac-ecc"; 5676b2da9ffSThor Thayer reg = <0xff8c0400 0x100>; 5686b2da9ffSThor Thayer altr,ecc-parent = <&gmac0>; 5696b2da9ffSThor Thayer interrupts = <5 4>, 5706b2da9ffSThor Thayer <37 4>; 5716b2da9ffSThor Thayer }; 5726b2da9ffSThor Thayer 57391fdd827SThor Thayer }; 5740cb140d0SThor Thayer 5750cb140d0SThor Thayer qspi: spi@ff8d2000 { 5760cb140d0SThor Thayer compatible = "cdns,qspi-nor"; 5770cb140d0SThor Thayer #address-cells = <1>; 5780cb140d0SThor Thayer #size-cells = <0>; 5790cb140d0SThor Thayer reg = <0xff8d2000 0x100>, 5800cb140d0SThor Thayer <0xff900000 0x100000>; 5810cb140d0SThor Thayer interrupts = <0 3 4>; 5820cb140d0SThor Thayer cdns,fifo-depth = <128>; 5830cb140d0SThor Thayer cdns,fifo-width = <4>; 5840cb140d0SThor Thayer cdns,trigger-address = <0x00000000>; 5850cb140d0SThor Thayer clocks = <&qspi_clk>; 5860cb140d0SThor Thayer 5870cb140d0SThor Thayer status = "disabled"; 5880cb140d0SThor Thayer }; 589adb9e354SRichard Gong 590adb9e354SRichard Gong firmware { 591adb9e354SRichard Gong svc { 592adb9e354SRichard Gong compatible = "intel,stratix10-svc"; 593adb9e354SRichard Gong method = "smc"; 594adb9e354SRichard Gong memory-region = <&service_reserved>; 595919d1100SAlan Tull 596919d1100SAlan Tull fpga_mgr: fpga-mgr { 597919d1100SAlan Tull compatible = "intel,stratix10-soc-fpga-mgr"; 598919d1100SAlan Tull }; 599adb9e354SRichard Gong }; 600adb9e354SRichard Gong }; 60178cd6a9dSDinh Nguyen }; 60278cd6a9dSDinh Nguyen}; 603