19952f691SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 278cd6a9dSDinh Nguyen/* 378cd6a9dSDinh Nguyen * Copyright Altera Corporation (C) 2015. All rights reserved. 478cd6a9dSDinh Nguyen */ 578cd6a9dSDinh Nguyen 678cd6a9dSDinh Nguyen/dts-v1/; 7e519922eSDinh Nguyen#include <dt-bindings/reset/altr,rst-mgr-s10.h> 85a0e622eSAlan Tull#include <dt-bindings/gpio/gpio.h> 9d93101abSDinh Nguyen#include <dt-bindings/clock/stratix10-clock.h> 1078cd6a9dSDinh Nguyen 1178cd6a9dSDinh Nguyen/ { 1278cd6a9dSDinh Nguyen compatible = "altr,socfpga-stratix10"; 1378cd6a9dSDinh Nguyen #address-cells = <2>; 1478cd6a9dSDinh Nguyen #size-cells = <2>; 1578cd6a9dSDinh Nguyen 16adb9e354SRichard Gong reserved-memory { 17adb9e354SRichard Gong #address-cells = <2>; 18adb9e354SRichard Gong #size-cells = <2>; 19adb9e354SRichard Gong ranges; 20adb9e354SRichard Gong 21adb9e354SRichard Gong service_reserved: svcbuffer@0 { 22adb9e354SRichard Gong compatible = "shared-dma-pool"; 23adb9e354SRichard Gong reg = <0x0 0x0 0x0 0x1000000>; 24adb9e354SRichard Gong alignment = <0x1000>; 25adb9e354SRichard Gong no-map; 26adb9e354SRichard Gong }; 27adb9e354SRichard Gong }; 28adb9e354SRichard Gong 2978cd6a9dSDinh Nguyen cpus { 3078cd6a9dSDinh Nguyen #address-cells = <1>; 3178cd6a9dSDinh Nguyen #size-cells = <0>; 3278cd6a9dSDinh Nguyen 3378cd6a9dSDinh Nguyen cpu0: cpu@0 { 3431af04cdSRob Herring compatible = "arm,cortex-a53"; 3578cd6a9dSDinh Nguyen device_type = "cpu"; 3678cd6a9dSDinh Nguyen enable-method = "psci"; 3778cd6a9dSDinh Nguyen reg = <0x0>; 3878cd6a9dSDinh Nguyen }; 3978cd6a9dSDinh Nguyen 4078cd6a9dSDinh Nguyen cpu1: cpu@1 { 4131af04cdSRob Herring compatible = "arm,cortex-a53"; 4278cd6a9dSDinh Nguyen device_type = "cpu"; 4378cd6a9dSDinh Nguyen enable-method = "psci"; 4478cd6a9dSDinh Nguyen reg = <0x1>; 4578cd6a9dSDinh Nguyen }; 4678cd6a9dSDinh Nguyen 4778cd6a9dSDinh Nguyen cpu2: cpu@2 { 4831af04cdSRob Herring compatible = "arm,cortex-a53"; 4978cd6a9dSDinh Nguyen device_type = "cpu"; 5078cd6a9dSDinh Nguyen enable-method = "psci"; 5178cd6a9dSDinh Nguyen reg = <0x2>; 5278cd6a9dSDinh Nguyen }; 5378cd6a9dSDinh Nguyen 5478cd6a9dSDinh Nguyen cpu3: cpu@3 { 5531af04cdSRob Herring compatible = "arm,cortex-a53"; 5678cd6a9dSDinh Nguyen device_type = "cpu"; 5778cd6a9dSDinh Nguyen enable-method = "psci"; 5878cd6a9dSDinh Nguyen reg = <0x3>; 5978cd6a9dSDinh Nguyen }; 6078cd6a9dSDinh Nguyen }; 6178cd6a9dSDinh Nguyen 6278cd6a9dSDinh Nguyen pmu { 6378cd6a9dSDinh Nguyen compatible = "arm,armv8-pmuv3"; 6478cd6a9dSDinh Nguyen interrupts = <0 120 8>, 6578cd6a9dSDinh Nguyen <0 121 8>, 6678cd6a9dSDinh Nguyen <0 122 8>, 6778cd6a9dSDinh Nguyen <0 123 8>; 6878cd6a9dSDinh Nguyen interrupt-affinity = <&cpu0>, 6978cd6a9dSDinh Nguyen <&cpu1>, 7078cd6a9dSDinh Nguyen <&cpu2>, 7178cd6a9dSDinh Nguyen <&cpu3>; 7269c4d8edSArnd Bergmann interrupt-parent = <&intc>; 7378cd6a9dSDinh Nguyen }; 7478cd6a9dSDinh Nguyen 7578cd6a9dSDinh Nguyen psci { 7678cd6a9dSDinh Nguyen compatible = "arm,psci-0.2"; 7778cd6a9dSDinh Nguyen method = "smc"; 7878cd6a9dSDinh Nguyen }; 7978cd6a9dSDinh Nguyen 8078cd6a9dSDinh Nguyen intc: intc@fffc1000 { 8178cd6a9dSDinh Nguyen compatible = "arm,gic-400", "arm,cortex-a15-gic"; 8278cd6a9dSDinh Nguyen #interrupt-cells = <3>; 8378cd6a9dSDinh Nguyen interrupt-controller; 84f973bfa0SDinh Nguyen reg = <0x0 0xfffc1000 0x0 0x1000>, 85f973bfa0SDinh Nguyen <0x0 0xfffc2000 0x0 0x2000>, 86f973bfa0SDinh Nguyen <0x0 0xfffc4000 0x0 0x2000>, 87f973bfa0SDinh Nguyen <0x0 0xfffc6000 0x0 0x2000>; 8878cd6a9dSDinh Nguyen }; 8978cd6a9dSDinh Nguyen 9078cd6a9dSDinh Nguyen soc { 9178cd6a9dSDinh Nguyen #address-cells = <1>; 9278cd6a9dSDinh Nguyen #size-cells = <1>; 9378cd6a9dSDinh Nguyen compatible = "simple-bus"; 9478cd6a9dSDinh Nguyen device_type = "soc"; 9578cd6a9dSDinh Nguyen interrupt-parent = <&intc>; 9678cd6a9dSDinh Nguyen ranges = <0 0 0 0xffffffff>; 9778cd6a9dSDinh Nguyen 98919d1100SAlan Tull base_fpga_region { 99919d1100SAlan Tull #address-cells = <0x1>; 100919d1100SAlan Tull #size-cells = <0x1>; 101919d1100SAlan Tull 102919d1100SAlan Tull compatible = "fpga-region"; 103919d1100SAlan Tull fpga-mgr = <&fpga_mgr>; 104919d1100SAlan Tull }; 105919d1100SAlan Tull 106d93101abSDinh Nguyen clkmgr: clock-controller@ffd10000 { 107d93101abSDinh Nguyen compatible = "intel,stratix10-clkmgr"; 10878cd6a9dSDinh Nguyen reg = <0xffd10000 0x1000>; 109d93101abSDinh Nguyen #clock-cells = <1>; 110d93101abSDinh Nguyen }; 111d93101abSDinh Nguyen 112d93101abSDinh Nguyen clocks { 113d93101abSDinh Nguyen cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 114d93101abSDinh Nguyen #clock-cells = <0>; 115d93101abSDinh Nguyen compatible = "fixed-clock"; 116d93101abSDinh Nguyen }; 117d93101abSDinh Nguyen 118d93101abSDinh Nguyen cb_intosc_ls_clk: cb-intosc-ls-clk { 119d93101abSDinh Nguyen #clock-cells = <0>; 120d93101abSDinh Nguyen compatible = "fixed-clock"; 121d93101abSDinh Nguyen }; 122d93101abSDinh Nguyen 123d93101abSDinh Nguyen f2s_free_clk: f2s-free-clk { 124d93101abSDinh Nguyen #clock-cells = <0>; 125d93101abSDinh Nguyen compatible = "fixed-clock"; 126d93101abSDinh Nguyen }; 127d93101abSDinh Nguyen 128d93101abSDinh Nguyen osc1: osc1 { 129d93101abSDinh Nguyen #clock-cells = <0>; 130d93101abSDinh Nguyen compatible = "fixed-clock"; 131d93101abSDinh Nguyen }; 1320cb140d0SThor Thayer 1330cb140d0SThor Thayer qspi_clk: qspi-clk { 1340cb140d0SThor Thayer #clock-cells = <0>; 1350cb140d0SThor Thayer compatible = "fixed-clock"; 1360cb140d0SThor Thayer clock-frequency = <200000000>; 1370cb140d0SThor Thayer }; 13878cd6a9dSDinh Nguyen }; 13978cd6a9dSDinh Nguyen 14078cd6a9dSDinh Nguyen gmac0: ethernet@ff800000 { 14178cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 14278cd6a9dSDinh Nguyen reg = <0xff800000 0x2000>; 14378cd6a9dSDinh Nguyen interrupts = <0 90 4>; 14478cd6a9dSDinh Nguyen interrupt-names = "macirq"; 14578cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 14605690e8aSDinh Nguyen resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 14705690e8aSDinh Nguyen reset-names = "stmmaceth", "stmmaceth-ocp"; 148d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_EMAC0_CLK>; 149d93101abSDinh Nguyen clock-names = "stmmaceth"; 150a27460c9SThor Thayer tx-fifo-depth = <16384>; 151a27460c9SThor Thayer rx-fifo-depth = <16384>; 152fd5ba6eeSAaro Koskinen snps,multicast-filter-bins = <256>; 153ae3f46c8SThor Thayer iommus = <&smmu 1>; 1548efd6365SDinh Nguyen altr,sysmgr-syscon = <&sysmgr 0x44 0>; 15578cd6a9dSDinh Nguyen status = "disabled"; 15678cd6a9dSDinh Nguyen }; 15778cd6a9dSDinh Nguyen 15878cd6a9dSDinh Nguyen gmac1: ethernet@ff802000 { 15978cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 16078cd6a9dSDinh Nguyen reg = <0xff802000 0x2000>; 16178cd6a9dSDinh Nguyen interrupts = <0 91 4>; 16278cd6a9dSDinh Nguyen interrupt-names = "macirq"; 16378cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 16405690e8aSDinh Nguyen resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 16505690e8aSDinh Nguyen reset-names = "stmmaceth", "stmmaceth-ocp"; 166d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_EMAC1_CLK>; 167d93101abSDinh Nguyen clock-names = "stmmaceth"; 168a27460c9SThor Thayer tx-fifo-depth = <16384>; 169a27460c9SThor Thayer rx-fifo-depth = <16384>; 170fd5ba6eeSAaro Koskinen snps,multicast-filter-bins = <256>; 171ae3f46c8SThor Thayer iommus = <&smmu 2>; 1728efd6365SDinh Nguyen altr,sysmgr-syscon = <&sysmgr 0x48 0>; 17378cd6a9dSDinh Nguyen status = "disabled"; 17478cd6a9dSDinh Nguyen }; 17578cd6a9dSDinh Nguyen 17678cd6a9dSDinh Nguyen gmac2: ethernet@ff804000 { 17778cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 17878cd6a9dSDinh Nguyen reg = <0xff804000 0x2000>; 17978cd6a9dSDinh Nguyen interrupts = <0 92 4>; 18078cd6a9dSDinh Nguyen interrupt-names = "macirq"; 18178cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 18205690e8aSDinh Nguyen resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 18305690e8aSDinh Nguyen reset-names = "stmmaceth", "stmmaceth-ocp"; 184d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_EMAC2_CLK>; 185d93101abSDinh Nguyen clock-names = "stmmaceth"; 186a27460c9SThor Thayer tx-fifo-depth = <16384>; 187a27460c9SThor Thayer rx-fifo-depth = <16384>; 188fd5ba6eeSAaro Koskinen snps,multicast-filter-bins = <256>; 189ae3f46c8SThor Thayer iommus = <&smmu 3>; 1908efd6365SDinh Nguyen altr,sysmgr-syscon = <&sysmgr 0x4c 0>; 19178cd6a9dSDinh Nguyen status = "disabled"; 19278cd6a9dSDinh Nguyen }; 19378cd6a9dSDinh Nguyen 19478cd6a9dSDinh Nguyen gpio0: gpio@ffc03200 { 19578cd6a9dSDinh Nguyen #address-cells = <1>; 19678cd6a9dSDinh Nguyen #size-cells = <0>; 19778cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio"; 19878cd6a9dSDinh Nguyen reg = <0xffc03200 0x100>; 199788251faSDinh Nguyen resets = <&rst GPIO0_RESET>; 20078cd6a9dSDinh Nguyen status = "disabled"; 20178cd6a9dSDinh Nguyen 20278cd6a9dSDinh Nguyen porta: gpio-controller@0 { 20378cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio-port"; 20478cd6a9dSDinh Nguyen gpio-controller; 20578cd6a9dSDinh Nguyen #gpio-cells = <2>; 20678cd6a9dSDinh Nguyen snps,nr-gpios = <24>; 20778cd6a9dSDinh Nguyen reg = <0>; 20878cd6a9dSDinh Nguyen interrupt-controller; 20978cd6a9dSDinh Nguyen #interrupt-cells = <2>; 21078cd6a9dSDinh Nguyen interrupts = <0 110 4>; 21178cd6a9dSDinh Nguyen }; 21278cd6a9dSDinh Nguyen }; 21378cd6a9dSDinh Nguyen 21478cd6a9dSDinh Nguyen gpio1: gpio@ffc03300 { 21578cd6a9dSDinh Nguyen #address-cells = <1>; 21678cd6a9dSDinh Nguyen #size-cells = <0>; 21778cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio"; 21878cd6a9dSDinh Nguyen reg = <0xffc03300 0x100>; 219788251faSDinh Nguyen resets = <&rst GPIO1_RESET>; 22078cd6a9dSDinh Nguyen status = "disabled"; 22178cd6a9dSDinh Nguyen 22278cd6a9dSDinh Nguyen portb: gpio-controller@0 { 22378cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio-port"; 22478cd6a9dSDinh Nguyen gpio-controller; 22578cd6a9dSDinh Nguyen #gpio-cells = <2>; 22678cd6a9dSDinh Nguyen snps,nr-gpios = <24>; 22778cd6a9dSDinh Nguyen reg = <0>; 22878cd6a9dSDinh Nguyen interrupt-controller; 22978cd6a9dSDinh Nguyen #interrupt-cells = <2>; 230a067fb42SDinh Nguyen interrupts = <0 111 4>; 23178cd6a9dSDinh Nguyen }; 23278cd6a9dSDinh Nguyen }; 23378cd6a9dSDinh Nguyen 23478cd6a9dSDinh Nguyen i2c0: i2c@ffc02800 { 23578cd6a9dSDinh Nguyen #address-cells = <1>; 23678cd6a9dSDinh Nguyen #size-cells = <0>; 23778cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 23878cd6a9dSDinh Nguyen reg = <0xffc02800 0x100>; 23978cd6a9dSDinh Nguyen interrupts = <0 103 4>; 240788251faSDinh Nguyen resets = <&rst I2C0_RESET>; 241eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 24278cd6a9dSDinh Nguyen status = "disabled"; 24378cd6a9dSDinh Nguyen }; 24478cd6a9dSDinh Nguyen 24578cd6a9dSDinh Nguyen i2c1: i2c@ffc02900 { 24678cd6a9dSDinh Nguyen #address-cells = <1>; 24778cd6a9dSDinh Nguyen #size-cells = <0>; 24878cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 24978cd6a9dSDinh Nguyen reg = <0xffc02900 0x100>; 25078cd6a9dSDinh Nguyen interrupts = <0 104 4>; 251788251faSDinh Nguyen resets = <&rst I2C1_RESET>; 252eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 25378cd6a9dSDinh Nguyen status = "disabled"; 25478cd6a9dSDinh Nguyen }; 25578cd6a9dSDinh Nguyen 25678cd6a9dSDinh Nguyen i2c2: i2c@ffc02a00 { 25778cd6a9dSDinh Nguyen #address-cells = <1>; 25878cd6a9dSDinh Nguyen #size-cells = <0>; 25978cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 26078cd6a9dSDinh Nguyen reg = <0xffc02a00 0x100>; 26178cd6a9dSDinh Nguyen interrupts = <0 105 4>; 262788251faSDinh Nguyen resets = <&rst I2C2_RESET>; 263eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 26478cd6a9dSDinh Nguyen status = "disabled"; 26578cd6a9dSDinh Nguyen }; 26678cd6a9dSDinh Nguyen 26778cd6a9dSDinh Nguyen i2c3: i2c@ffc02b00 { 26878cd6a9dSDinh Nguyen #address-cells = <1>; 26978cd6a9dSDinh Nguyen #size-cells = <0>; 27078cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 27178cd6a9dSDinh Nguyen reg = <0xffc02b00 0x100>; 27278cd6a9dSDinh Nguyen interrupts = <0 106 4>; 273788251faSDinh Nguyen resets = <&rst I2C3_RESET>; 274eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 27578cd6a9dSDinh Nguyen status = "disabled"; 27678cd6a9dSDinh Nguyen }; 27778cd6a9dSDinh Nguyen 27878cd6a9dSDinh Nguyen i2c4: i2c@ffc02c00 { 27978cd6a9dSDinh Nguyen #address-cells = <1>; 28078cd6a9dSDinh Nguyen #size-cells = <0>; 28178cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 28278cd6a9dSDinh Nguyen reg = <0xffc02c00 0x100>; 28378cd6a9dSDinh Nguyen interrupts = <0 107 4>; 284788251faSDinh Nguyen resets = <&rst I2C4_RESET>; 285eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 28678cd6a9dSDinh Nguyen status = "disabled"; 28778cd6a9dSDinh Nguyen }; 28878cd6a9dSDinh Nguyen 28978cd6a9dSDinh Nguyen mmc: dwmmc0@ff808000 { 29078cd6a9dSDinh Nguyen #address-cells = <1>; 29178cd6a9dSDinh Nguyen #size-cells = <0>; 29278cd6a9dSDinh Nguyen compatible = "altr,socfpga-dw-mshc"; 29378cd6a9dSDinh Nguyen reg = <0xff808000 0x1000>; 29478cd6a9dSDinh Nguyen interrupts = <0 96 4>; 29578cd6a9dSDinh Nguyen fifo-depth = <0x400>; 296788251faSDinh Nguyen resets = <&rst SDMMC_RESET>; 297788251faSDinh Nguyen reset-names = "reset"; 298d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_MP_CLK>, 299d93101abSDinh Nguyen <&clkmgr STRATIX10_SDMMC_CLK>; 300d93101abSDinh Nguyen clock-names = "biu", "ciu"; 301ae3f46c8SThor Thayer iommus = <&smmu 5>; 30278cd6a9dSDinh Nguyen status = "disabled"; 30378cd6a9dSDinh Nguyen }; 30478cd6a9dSDinh Nguyen 30578cd6a9dSDinh Nguyen ocram: sram@ffe00000 { 30678cd6a9dSDinh Nguyen compatible = "mmio-sram"; 30778cd6a9dSDinh Nguyen reg = <0xffe00000 0x100000>; 30878cd6a9dSDinh Nguyen }; 30978cd6a9dSDinh Nguyen 310ab50a444SGraham Moore pdma: pdma@ffda0000 { 311ab50a444SGraham Moore compatible = "arm,pl330", "arm,primecell"; 312ab50a444SGraham Moore reg = <0xffda0000 0x1000>; 313ab50a444SGraham Moore interrupts = <0 81 4>, 314ab50a444SGraham Moore <0 82 4>, 315ab50a444SGraham Moore <0 83 4>, 316ab50a444SGraham Moore <0 84 4>, 317ab50a444SGraham Moore <0 85 4>, 318ab50a444SGraham Moore <0 86 4>, 319ab50a444SGraham Moore <0 87 4>, 320ab50a444SGraham Moore <0 88 4>, 321ab50a444SGraham Moore <0 89 4>; 322ab50a444SGraham Moore #dma-cells = <1>; 323ab50a444SGraham Moore #dma-channels = <8>; 324ab50a444SGraham Moore #dma-requests = <32>; 325ab50a444SGraham Moore clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 326ab50a444SGraham Moore clock-names = "apb_pclk"; 327ab50a444SGraham Moore }; 328ab50a444SGraham Moore 32978cd6a9dSDinh Nguyen rst: rstmgr@ffd11000 { 33078cd6a9dSDinh Nguyen #reset-cells = <1>; 3318bb4f3f5SDinh Nguyen compatible = "altr,stratix10-rst-mgr"; 33278cd6a9dSDinh Nguyen reg = <0xffd11000 0x1000>; 33378cd6a9dSDinh Nguyen }; 33478cd6a9dSDinh Nguyen 335ae3f46c8SThor Thayer smmu: iommu@fa000000 { 336ae3f46c8SThor Thayer compatible = "arm,mmu-500", "arm,smmu-v2"; 337ae3f46c8SThor Thayer reg = <0xfa000000 0x40000>; 338ae3f46c8SThor Thayer #global-interrupts = <2>; 339ae3f46c8SThor Thayer #iommu-cells = <1>; 340ae3f46c8SThor Thayer clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 341ae3f46c8SThor Thayer clock-names = "iommu"; 342ae3f46c8SThor Thayer interrupt-parent = <&intc>; 343ae3f46c8SThor Thayer interrupts = <0 128 4>, /* Global Secure Fault */ 344ae3f46c8SThor Thayer <0 129 4>, /* Global Non-secure Fault */ 345ae3f46c8SThor Thayer /* Non-secure Context Interrupts (32) */ 346ae3f46c8SThor Thayer <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>, 347ae3f46c8SThor Thayer <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>, 348ae3f46c8SThor Thayer <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>, 349ae3f46c8SThor Thayer <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>, 350ae3f46c8SThor Thayer <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>, 351ae3f46c8SThor Thayer <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>, 352ae3f46c8SThor Thayer <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>, 353ae3f46c8SThor Thayer <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>; 354ae3f46c8SThor Thayer stream-match-mask = <0x7ff0>; 355ae3f46c8SThor Thayer status = "disabled"; 356ae3f46c8SThor Thayer }; 357ae3f46c8SThor Thayer 35878cd6a9dSDinh Nguyen spi0: spi@ffda4000 { 35978cd6a9dSDinh Nguyen compatible = "snps,dw-apb-ssi"; 36078cd6a9dSDinh Nguyen #address-cells = <1>; 36178cd6a9dSDinh Nguyen #size-cells = <0>; 36278cd6a9dSDinh Nguyen reg = <0xffda4000 0x1000>; 363889d1509SThor Thayer interrupts = <0 99 4>; 364889d1509SThor Thayer resets = <&rst SPIM0_RESET>; 365889d1509SThor Thayer reg-io-width = <4>; 3664595299cSThor Thayer num-cs = <4>; 36770455ac7SThor Thayer clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 36878cd6a9dSDinh Nguyen status = "disabled"; 36978cd6a9dSDinh Nguyen }; 37078cd6a9dSDinh Nguyen 37178cd6a9dSDinh Nguyen spi1: spi@ffda5000 { 37278cd6a9dSDinh Nguyen compatible = "snps,dw-apb-ssi"; 37378cd6a9dSDinh Nguyen #address-cells = <1>; 37478cd6a9dSDinh Nguyen #size-cells = <0>; 37578cd6a9dSDinh Nguyen reg = <0xffda5000 0x1000>; 376889d1509SThor Thayer interrupts = <0 100 4>; 377889d1509SThor Thayer resets = <&rst SPIM1_RESET>; 378889d1509SThor Thayer reg-io-width = <4>; 3794595299cSThor Thayer num-cs = <4>; 38070455ac7SThor Thayer clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 38178cd6a9dSDinh Nguyen status = "disabled"; 38278cd6a9dSDinh Nguyen }; 38378cd6a9dSDinh Nguyen 38478cd6a9dSDinh Nguyen sysmgr: sysmgr@ffd12000 { 3858f4ebe9bSThor Thayer compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 38674121b9aSThor Thayer reg = <0xffd12000 0x228>; 38778cd6a9dSDinh Nguyen }; 38878cd6a9dSDinh Nguyen 38978cd6a9dSDinh Nguyen /* Local timer */ 39078cd6a9dSDinh Nguyen timer { 39178cd6a9dSDinh Nguyen compatible = "arm,armv8-timer"; 392f2a89d3bSMarc Zyngier interrupts = <1 13 0xf08>, 393f2a89d3bSMarc Zyngier <1 14 0xf08>, 394f2a89d3bSMarc Zyngier <1 11 0xf08>, 395f2a89d3bSMarc Zyngier <1 10 0xf08>; 39678cd6a9dSDinh Nguyen }; 39778cd6a9dSDinh Nguyen 39878cd6a9dSDinh Nguyen timer0: timer0@ffc03000 { 39978cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 40078cd6a9dSDinh Nguyen interrupts = <0 113 4>; 40178cd6a9dSDinh Nguyen reg = <0xffc03000 0x100>; 402d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 403d93101abSDinh Nguyen clock-names = "timer"; 40478cd6a9dSDinh Nguyen }; 40578cd6a9dSDinh Nguyen 40678cd6a9dSDinh Nguyen timer1: timer1@ffc03100 { 40778cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 40878cd6a9dSDinh Nguyen interrupts = <0 114 4>; 40978cd6a9dSDinh Nguyen reg = <0xffc03100 0x100>; 410d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 411d93101abSDinh Nguyen clock-names = "timer"; 41278cd6a9dSDinh Nguyen }; 41378cd6a9dSDinh Nguyen 41478cd6a9dSDinh Nguyen timer2: timer2@ffd00000 { 41578cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 41678cd6a9dSDinh Nguyen interrupts = <0 115 4>; 41778cd6a9dSDinh Nguyen reg = <0xffd00000 0x100>; 418d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 419d93101abSDinh Nguyen clock-names = "timer"; 42078cd6a9dSDinh Nguyen }; 42178cd6a9dSDinh Nguyen 42278cd6a9dSDinh Nguyen timer3: timer3@ffd00100 { 42378cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 42478cd6a9dSDinh Nguyen interrupts = <0 116 4>; 42578cd6a9dSDinh Nguyen reg = <0xffd00100 0x100>; 426d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 427d93101abSDinh Nguyen clock-names = "timer"; 42878cd6a9dSDinh Nguyen }; 42978cd6a9dSDinh Nguyen 43078cd6a9dSDinh Nguyen uart0: serial0@ffc02000 { 43178cd6a9dSDinh Nguyen compatible = "snps,dw-apb-uart"; 43278cd6a9dSDinh Nguyen reg = <0xffc02000 0x100>; 43378cd6a9dSDinh Nguyen interrupts = <0 108 4>; 43478cd6a9dSDinh Nguyen reg-shift = <2>; 43578cd6a9dSDinh Nguyen reg-io-width = <4>; 436788251faSDinh Nguyen resets = <&rst UART0_RESET>; 437d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 43878cd6a9dSDinh Nguyen status = "disabled"; 43978cd6a9dSDinh Nguyen }; 44078cd6a9dSDinh Nguyen 44178cd6a9dSDinh Nguyen uart1: serial1@ffc02100 { 44278cd6a9dSDinh Nguyen compatible = "snps,dw-apb-uart"; 44378cd6a9dSDinh Nguyen reg = <0xffc02100 0x100>; 44478cd6a9dSDinh Nguyen interrupts = <0 109 4>; 44578cd6a9dSDinh Nguyen reg-shift = <2>; 44678cd6a9dSDinh Nguyen reg-io-width = <4>; 447788251faSDinh Nguyen resets = <&rst UART1_RESET>; 448d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 44978cd6a9dSDinh Nguyen status = "disabled"; 45078cd6a9dSDinh Nguyen }; 45178cd6a9dSDinh Nguyen 45278cd6a9dSDinh Nguyen usbphy0: usbphy@0 { 45378cd6a9dSDinh Nguyen #phy-cells = <0>; 45478cd6a9dSDinh Nguyen compatible = "usb-nop-xceiv"; 45578cd6a9dSDinh Nguyen status = "okay"; 45678cd6a9dSDinh Nguyen }; 45778cd6a9dSDinh Nguyen 45878cd6a9dSDinh Nguyen usb0: usb@ffb00000 { 45978cd6a9dSDinh Nguyen compatible = "snps,dwc2"; 46078cd6a9dSDinh Nguyen reg = <0xffb00000 0x40000>; 46178cd6a9dSDinh Nguyen interrupts = <0 93 4>; 46278cd6a9dSDinh Nguyen phys = <&usbphy0>; 46378cd6a9dSDinh Nguyen phy-names = "usb2-phy"; 46433af8ca0SDinh Nguyen resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 46533af8ca0SDinh Nguyen reset-names = "dwc2", "dwc2-ecc"; 46603761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_USB_CLK>; 467ae3f46c8SThor Thayer iommus = <&smmu 6>; 46878cd6a9dSDinh Nguyen status = "disabled"; 46978cd6a9dSDinh Nguyen }; 47078cd6a9dSDinh Nguyen 47178cd6a9dSDinh Nguyen usb1: usb@ffb40000 { 47278cd6a9dSDinh Nguyen compatible = "snps,dwc2"; 47378cd6a9dSDinh Nguyen reg = <0xffb40000 0x40000>; 47478cd6a9dSDinh Nguyen interrupts = <0 94 4>; 47578cd6a9dSDinh Nguyen phys = <&usbphy0>; 47678cd6a9dSDinh Nguyen phy-names = "usb2-phy"; 47733af8ca0SDinh Nguyen resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 47833af8ca0SDinh Nguyen reset-names = "dwc2", "dwc2-ecc"; 47903761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_USB_CLK>; 480ae3f46c8SThor Thayer iommus = <&smmu 7>; 48178cd6a9dSDinh Nguyen status = "disabled"; 48278cd6a9dSDinh Nguyen }; 48378cd6a9dSDinh Nguyen 48478cd6a9dSDinh Nguyen watchdog0: watchdog@ffd00200 { 48578cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 48678cd6a9dSDinh Nguyen reg = <0xffd00200 0x100>; 48778cd6a9dSDinh Nguyen interrupts = <0 117 4>; 488788251faSDinh Nguyen resets = <&rst WATCHDOG0_RESET>; 48903761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 49078cd6a9dSDinh Nguyen status = "disabled"; 49178cd6a9dSDinh Nguyen }; 49278cd6a9dSDinh Nguyen 49378cd6a9dSDinh Nguyen watchdog1: watchdog@ffd00300 { 49478cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 49578cd6a9dSDinh Nguyen reg = <0xffd00300 0x100>; 49678cd6a9dSDinh Nguyen interrupts = <0 118 4>; 497788251faSDinh Nguyen resets = <&rst WATCHDOG1_RESET>; 49803761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 49978cd6a9dSDinh Nguyen status = "disabled"; 50078cd6a9dSDinh Nguyen }; 50178cd6a9dSDinh Nguyen 50278cd6a9dSDinh Nguyen watchdog2: watchdog@ffd00400 { 50378cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 50478cd6a9dSDinh Nguyen reg = <0xffd00400 0x100>; 50578cd6a9dSDinh Nguyen interrupts = <0 125 4>; 506788251faSDinh Nguyen resets = <&rst WATCHDOG2_RESET>; 50703761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 50878cd6a9dSDinh Nguyen status = "disabled"; 50978cd6a9dSDinh Nguyen }; 51078cd6a9dSDinh Nguyen 51178cd6a9dSDinh Nguyen watchdog3: watchdog@ffd00500 { 51278cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 51378cd6a9dSDinh Nguyen reg = <0xffd00500 0x100>; 51478cd6a9dSDinh Nguyen interrupts = <0 126 4>; 515788251faSDinh Nguyen resets = <&rst WATCHDOG3_RESET>; 51603761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 51778cd6a9dSDinh Nguyen status = "disabled"; 51878cd6a9dSDinh Nguyen }; 51991fdd827SThor Thayer 520446fd7afSThor Thayer sdr: sdr@f8011100 { 521446fd7afSThor Thayer compatible = "altr,sdr-ctl", "syscon"; 522446fd7afSThor Thayer reg = <0xf8011100 0xc0>; 523446fd7afSThor Thayer }; 524446fd7afSThor Thayer 52591fdd827SThor Thayer eccmgr { 52674676a8eSThor Thayer compatible = "altr,socfpga-s10-ecc-manager", 52774676a8eSThor Thayer "altr,socfpga-a10-ecc-manager"; 5283ce078ffSThor Thayer altr,sysmgr-syscon = <&sysmgr>; 5293ce078ffSThor Thayer #address-cells = <1>; 5303ce078ffSThor Thayer #size-cells = <1>; 53174676a8eSThor Thayer interrupts = <0 15 4>; 53291fdd827SThor Thayer interrupt-controller; 53391fdd827SThor Thayer #interrupt-cells = <2>; 5343ce078ffSThor Thayer ranges; 53591fdd827SThor Thayer 53691fdd827SThor Thayer sdramedac { 53791fdd827SThor Thayer compatible = "altr,sdram-edac-s10"; 538446fd7afSThor Thayer altr,sdr-syscon = <&sdr>; 53974676a8eSThor Thayer interrupts = <16 4>; 54091fdd827SThor Thayer }; 5416b2da9ffSThor Thayer 5426b2da9ffSThor Thayer usb0-ecc@ff8c4000 { 54374676a8eSThor Thayer compatible = "altr,socfpga-s10-usb-ecc", 54474676a8eSThor Thayer "altr,socfpga-usb-ecc"; 5456b2da9ffSThor Thayer reg = <0xff8c4000 0x100>; 5466b2da9ffSThor Thayer altr,ecc-parent = <&usb0>; 54774676a8eSThor Thayer interrupts = <2 4>; 5486b2da9ffSThor Thayer }; 5496b2da9ffSThor Thayer 5506b2da9ffSThor Thayer emac0-rx-ecc@ff8c0000 { 55174676a8eSThor Thayer compatible = "altr,socfpga-s10-eth-mac-ecc", 55274676a8eSThor Thayer "altr,socfpga-eth-mac-ecc"; 5536b2da9ffSThor Thayer reg = <0xff8c0000 0x100>; 5546b2da9ffSThor Thayer altr,ecc-parent = <&gmac0>; 55574676a8eSThor Thayer interrupts = <4 4>; 5566b2da9ffSThor Thayer }; 5576b2da9ffSThor Thayer 5586b2da9ffSThor Thayer emac0-tx-ecc@ff8c0400 { 55974676a8eSThor Thayer compatible = "altr,socfpga-s10-eth-mac-ecc", 56074676a8eSThor Thayer "altr,socfpga-eth-mac-ecc"; 5616b2da9ffSThor Thayer reg = <0xff8c0400 0x100>; 5626b2da9ffSThor Thayer altr,ecc-parent = <&gmac0>; 56374676a8eSThor Thayer interrupts = <5 4>; 5646b2da9ffSThor Thayer }; 5656b2da9ffSThor Thayer 56691fdd827SThor Thayer }; 5670cb140d0SThor Thayer 5680cb140d0SThor Thayer qspi: spi@ff8d2000 { 5690cb140d0SThor Thayer compatible = "cdns,qspi-nor"; 5700cb140d0SThor Thayer #address-cells = <1>; 5710cb140d0SThor Thayer #size-cells = <0>; 5720cb140d0SThor Thayer reg = <0xff8d2000 0x100>, 5730cb140d0SThor Thayer <0xff900000 0x100000>; 5740cb140d0SThor Thayer interrupts = <0 3 4>; 5750cb140d0SThor Thayer cdns,fifo-depth = <128>; 5760cb140d0SThor Thayer cdns,fifo-width = <4>; 5770cb140d0SThor Thayer cdns,trigger-address = <0x00000000>; 5780cb140d0SThor Thayer clocks = <&qspi_clk>; 5790cb140d0SThor Thayer 5800cb140d0SThor Thayer status = "disabled"; 5810cb140d0SThor Thayer }; 582adb9e354SRichard Gong 583adb9e354SRichard Gong firmware { 584adb9e354SRichard Gong svc { 585adb9e354SRichard Gong compatible = "intel,stratix10-svc"; 586adb9e354SRichard Gong method = "smc"; 587adb9e354SRichard Gong memory-region = <&service_reserved>; 588919d1100SAlan Tull 589919d1100SAlan Tull fpga_mgr: fpga-mgr { 590919d1100SAlan Tull compatible = "intel,stratix10-soc-fpga-mgr"; 591919d1100SAlan Tull }; 592adb9e354SRichard Gong }; 593adb9e354SRichard Gong }; 59478cd6a9dSDinh Nguyen }; 59578cd6a9dSDinh Nguyen}; 596