178cd6a9dSDinh Nguyen/* 278cd6a9dSDinh Nguyen * Copyright Altera Corporation (C) 2015. All rights reserved. 378cd6a9dSDinh Nguyen * 478cd6a9dSDinh Nguyen * This program is free software; you can redistribute it and/or modify 578cd6a9dSDinh Nguyen * it under the terms and conditions of the GNU General Public License, 678cd6a9dSDinh Nguyen * version 2, as published by the Free Software Foundation. 778cd6a9dSDinh Nguyen * 878cd6a9dSDinh Nguyen * This program is distributed in the hope it will be useful, but WITHOUT 978cd6a9dSDinh Nguyen * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1078cd6a9dSDinh Nguyen * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1178cd6a9dSDinh Nguyen * more details. 1278cd6a9dSDinh Nguyen * 1378cd6a9dSDinh Nguyen * You should have received a copy of the GNU General Public License along with 1478cd6a9dSDinh Nguyen * this program. If not, see <http://www.gnu.org/licenses/>. 1578cd6a9dSDinh Nguyen */ 1678cd6a9dSDinh Nguyen 1778cd6a9dSDinh Nguyen/dts-v1/; 18e519922eSDinh Nguyen#include <dt-bindings/reset/altr,rst-mgr-s10.h> 1978cd6a9dSDinh Nguyen 2078cd6a9dSDinh Nguyen/ { 2178cd6a9dSDinh Nguyen compatible = "altr,socfpga-stratix10"; 2278cd6a9dSDinh Nguyen #address-cells = <2>; 2378cd6a9dSDinh Nguyen #size-cells = <2>; 2478cd6a9dSDinh Nguyen 2578cd6a9dSDinh Nguyen cpus { 2678cd6a9dSDinh Nguyen #address-cells = <1>; 2778cd6a9dSDinh Nguyen #size-cells = <0>; 2878cd6a9dSDinh Nguyen 2978cd6a9dSDinh Nguyen cpu0: cpu@0 { 3078cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 3178cd6a9dSDinh Nguyen device_type = "cpu"; 3278cd6a9dSDinh Nguyen enable-method = "psci"; 3378cd6a9dSDinh Nguyen reg = <0x0>; 3478cd6a9dSDinh Nguyen }; 3578cd6a9dSDinh Nguyen 3678cd6a9dSDinh Nguyen cpu1: cpu@1 { 3778cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 3878cd6a9dSDinh Nguyen device_type = "cpu"; 3978cd6a9dSDinh Nguyen enable-method = "psci"; 4078cd6a9dSDinh Nguyen reg = <0x1>; 4178cd6a9dSDinh Nguyen }; 4278cd6a9dSDinh Nguyen 4378cd6a9dSDinh Nguyen cpu2: cpu@2 { 4478cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 4578cd6a9dSDinh Nguyen device_type = "cpu"; 4678cd6a9dSDinh Nguyen enable-method = "psci"; 4778cd6a9dSDinh Nguyen reg = <0x2>; 4878cd6a9dSDinh Nguyen }; 4978cd6a9dSDinh Nguyen 5078cd6a9dSDinh Nguyen cpu3: cpu@3 { 5178cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 5278cd6a9dSDinh Nguyen device_type = "cpu"; 5378cd6a9dSDinh Nguyen enable-method = "psci"; 5478cd6a9dSDinh Nguyen reg = <0x3>; 5578cd6a9dSDinh Nguyen }; 5678cd6a9dSDinh Nguyen }; 5778cd6a9dSDinh Nguyen 5878cd6a9dSDinh Nguyen pmu { 5978cd6a9dSDinh Nguyen compatible = "arm,armv8-pmuv3"; 6078cd6a9dSDinh Nguyen interrupts = <0 120 8>, 6178cd6a9dSDinh Nguyen <0 121 8>, 6278cd6a9dSDinh Nguyen <0 122 8>, 6378cd6a9dSDinh Nguyen <0 123 8>; 6478cd6a9dSDinh Nguyen interrupt-affinity = <&cpu0>, 6578cd6a9dSDinh Nguyen <&cpu1>, 6678cd6a9dSDinh Nguyen <&cpu2>, 6778cd6a9dSDinh Nguyen <&cpu3>; 6878cd6a9dSDinh Nguyen }; 6978cd6a9dSDinh Nguyen 7078cd6a9dSDinh Nguyen psci { 7178cd6a9dSDinh Nguyen compatible = "arm,psci-0.2"; 7278cd6a9dSDinh Nguyen method = "smc"; 7378cd6a9dSDinh Nguyen }; 7478cd6a9dSDinh Nguyen 7578cd6a9dSDinh Nguyen intc: intc@fffc1000 { 7678cd6a9dSDinh Nguyen compatible = "arm,gic-400", "arm,cortex-a15-gic"; 7778cd6a9dSDinh Nguyen #interrupt-cells = <3>; 7878cd6a9dSDinh Nguyen interrupt-controller; 79f973bfa0SDinh Nguyen reg = <0x0 0xfffc1000 0x0 0x1000>, 80f973bfa0SDinh Nguyen <0x0 0xfffc2000 0x0 0x2000>, 81f973bfa0SDinh Nguyen <0x0 0xfffc4000 0x0 0x2000>, 82f973bfa0SDinh Nguyen <0x0 0xfffc6000 0x0 0x2000>; 8378cd6a9dSDinh Nguyen }; 8478cd6a9dSDinh Nguyen 8578cd6a9dSDinh Nguyen soc { 8678cd6a9dSDinh Nguyen #address-cells = <1>; 8778cd6a9dSDinh Nguyen #size-cells = <1>; 8878cd6a9dSDinh Nguyen compatible = "simple-bus"; 8978cd6a9dSDinh Nguyen device_type = "soc"; 9078cd6a9dSDinh Nguyen interrupt-parent = <&intc>; 9178cd6a9dSDinh Nguyen ranges = <0 0 0 0xffffffff>; 9278cd6a9dSDinh Nguyen 9378cd6a9dSDinh Nguyen clkmgr@ffd1000 { 9478cd6a9dSDinh Nguyen compatible = "altr,clk-mgr"; 9578cd6a9dSDinh Nguyen reg = <0xffd10000 0x1000>; 9678cd6a9dSDinh Nguyen }; 9778cd6a9dSDinh Nguyen 9878cd6a9dSDinh Nguyen gmac0: ethernet@ff800000 { 9978cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 10078cd6a9dSDinh Nguyen reg = <0xff800000 0x2000>; 10178cd6a9dSDinh Nguyen interrupts = <0 90 4>; 10278cd6a9dSDinh Nguyen interrupt-names = "macirq"; 10378cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 10478cd6a9dSDinh Nguyen status = "disabled"; 10578cd6a9dSDinh Nguyen }; 10678cd6a9dSDinh Nguyen 10778cd6a9dSDinh Nguyen gmac1: ethernet@ff802000 { 10878cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 10978cd6a9dSDinh Nguyen reg = <0xff802000 0x2000>; 11078cd6a9dSDinh Nguyen interrupts = <0 91 4>; 11178cd6a9dSDinh Nguyen interrupt-names = "macirq"; 11278cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 11378cd6a9dSDinh Nguyen status = "disabled"; 11478cd6a9dSDinh Nguyen }; 11578cd6a9dSDinh Nguyen 11678cd6a9dSDinh Nguyen gmac2: ethernet@ff804000 { 11778cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 11878cd6a9dSDinh Nguyen reg = <0xff804000 0x2000>; 11978cd6a9dSDinh Nguyen interrupts = <0 92 4>; 12078cd6a9dSDinh Nguyen interrupt-names = "macirq"; 12178cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 12278cd6a9dSDinh Nguyen status = "disabled"; 12378cd6a9dSDinh Nguyen }; 12478cd6a9dSDinh Nguyen 12578cd6a9dSDinh Nguyen gpio0: gpio@ffc03200 { 12678cd6a9dSDinh Nguyen #address-cells = <1>; 12778cd6a9dSDinh Nguyen #size-cells = <0>; 12878cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio"; 12978cd6a9dSDinh Nguyen reg = <0xffc03200 0x100>; 13078cd6a9dSDinh Nguyen status = "disabled"; 13178cd6a9dSDinh Nguyen 13278cd6a9dSDinh Nguyen porta: gpio-controller@0 { 13378cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio-port"; 13478cd6a9dSDinh Nguyen gpio-controller; 13578cd6a9dSDinh Nguyen #gpio-cells = <2>; 13678cd6a9dSDinh Nguyen snps,nr-gpios = <24>; 13778cd6a9dSDinh Nguyen reg = <0>; 13878cd6a9dSDinh Nguyen interrupt-controller; 13978cd6a9dSDinh Nguyen #interrupt-cells = <2>; 14078cd6a9dSDinh Nguyen interrupts = <0 110 4>; 14178cd6a9dSDinh Nguyen }; 14278cd6a9dSDinh Nguyen }; 14378cd6a9dSDinh Nguyen 14478cd6a9dSDinh Nguyen gpio1: gpio@ffc03300 { 14578cd6a9dSDinh Nguyen #address-cells = <1>; 14678cd6a9dSDinh Nguyen #size-cells = <0>; 14778cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio"; 14878cd6a9dSDinh Nguyen reg = <0xffc03300 0x100>; 14978cd6a9dSDinh Nguyen status = "disabled"; 15078cd6a9dSDinh Nguyen 15178cd6a9dSDinh Nguyen portb: gpio-controller@0 { 15278cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio-port"; 15378cd6a9dSDinh Nguyen gpio-controller; 15478cd6a9dSDinh Nguyen #gpio-cells = <2>; 15578cd6a9dSDinh Nguyen snps,nr-gpios = <24>; 15678cd6a9dSDinh Nguyen reg = <0>; 15778cd6a9dSDinh Nguyen interrupt-controller; 15878cd6a9dSDinh Nguyen #interrupt-cells = <2>; 15978cd6a9dSDinh Nguyen interrupts = <0 110 4>; 16078cd6a9dSDinh Nguyen }; 16178cd6a9dSDinh Nguyen }; 16278cd6a9dSDinh Nguyen 16378cd6a9dSDinh Nguyen i2c0: i2c@ffc02800 { 16478cd6a9dSDinh Nguyen #address-cells = <1>; 16578cd6a9dSDinh Nguyen #size-cells = <0>; 16678cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 16778cd6a9dSDinh Nguyen reg = <0xffc02800 0x100>; 16878cd6a9dSDinh Nguyen interrupts = <0 103 4>; 16978cd6a9dSDinh Nguyen status = "disabled"; 17078cd6a9dSDinh Nguyen }; 17178cd6a9dSDinh Nguyen 17278cd6a9dSDinh Nguyen i2c1: i2c@ffc02900 { 17378cd6a9dSDinh Nguyen #address-cells = <1>; 17478cd6a9dSDinh Nguyen #size-cells = <0>; 17578cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 17678cd6a9dSDinh Nguyen reg = <0xffc02900 0x100>; 17778cd6a9dSDinh Nguyen interrupts = <0 104 4>; 17878cd6a9dSDinh Nguyen status = "disabled"; 17978cd6a9dSDinh Nguyen }; 18078cd6a9dSDinh Nguyen 18178cd6a9dSDinh Nguyen i2c2: i2c@ffc02a00 { 18278cd6a9dSDinh Nguyen #address-cells = <1>; 18378cd6a9dSDinh Nguyen #size-cells = <0>; 18478cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 18578cd6a9dSDinh Nguyen reg = <0xffc02a00 0x100>; 18678cd6a9dSDinh Nguyen interrupts = <0 105 4>; 18778cd6a9dSDinh Nguyen status = "disabled"; 18878cd6a9dSDinh Nguyen }; 18978cd6a9dSDinh Nguyen 19078cd6a9dSDinh Nguyen i2c3: i2c@ffc02b00 { 19178cd6a9dSDinh Nguyen #address-cells = <1>; 19278cd6a9dSDinh Nguyen #size-cells = <0>; 19378cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 19478cd6a9dSDinh Nguyen reg = <0xffc02b00 0x100>; 19578cd6a9dSDinh Nguyen interrupts = <0 106 4>; 19678cd6a9dSDinh Nguyen status = "disabled"; 19778cd6a9dSDinh Nguyen }; 19878cd6a9dSDinh Nguyen 19978cd6a9dSDinh Nguyen i2c4: i2c@ffc02c00 { 20078cd6a9dSDinh Nguyen #address-cells = <1>; 20178cd6a9dSDinh Nguyen #size-cells = <0>; 20278cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 20378cd6a9dSDinh Nguyen reg = <0xffc02c00 0x100>; 20478cd6a9dSDinh Nguyen interrupts = <0 107 4>; 20578cd6a9dSDinh Nguyen status = "disabled"; 20678cd6a9dSDinh Nguyen }; 20778cd6a9dSDinh Nguyen 20878cd6a9dSDinh Nguyen mmc: dwmmc0@ff808000 { 20978cd6a9dSDinh Nguyen #address-cells = <1>; 21078cd6a9dSDinh Nguyen #size-cells = <0>; 21178cd6a9dSDinh Nguyen compatible = "altr,socfpga-dw-mshc"; 21278cd6a9dSDinh Nguyen reg = <0xff808000 0x1000>; 21378cd6a9dSDinh Nguyen interrupts = <0 96 4>; 21478cd6a9dSDinh Nguyen fifo-depth = <0x400>; 21578cd6a9dSDinh Nguyen status = "disabled"; 21678cd6a9dSDinh Nguyen }; 21778cd6a9dSDinh Nguyen 21878cd6a9dSDinh Nguyen ocram: sram@ffe00000 { 21978cd6a9dSDinh Nguyen compatible = "mmio-sram"; 22078cd6a9dSDinh Nguyen reg = <0xffe00000 0x100000>; 22178cd6a9dSDinh Nguyen }; 22278cd6a9dSDinh Nguyen 22378cd6a9dSDinh Nguyen rst: rstmgr@ffd11000 { 22478cd6a9dSDinh Nguyen #reset-cells = <1>; 22578cd6a9dSDinh Nguyen compatible = "altr,rst-mgr"; 22678cd6a9dSDinh Nguyen reg = <0xffd11000 0x1000>; 2277691d626SDinh Nguyen altr,modrst-offset = <0x20>; 22878cd6a9dSDinh Nguyen }; 22978cd6a9dSDinh Nguyen 23078cd6a9dSDinh Nguyen spi0: spi@ffda4000 { 23178cd6a9dSDinh Nguyen compatible = "snps,dw-apb-ssi"; 23278cd6a9dSDinh Nguyen #address-cells = <1>; 23378cd6a9dSDinh Nguyen #size-cells = <0>; 23478cd6a9dSDinh Nguyen reg = <0xffda4000 0x1000>; 23578cd6a9dSDinh Nguyen interrupts = <0 101 4>; 23678cd6a9dSDinh Nguyen num-chipselect = <4>; 23778cd6a9dSDinh Nguyen bus-num = <0>; 23878cd6a9dSDinh Nguyen status = "disabled"; 23978cd6a9dSDinh Nguyen }; 24078cd6a9dSDinh Nguyen 24178cd6a9dSDinh Nguyen spi1: spi@ffda5000 { 24278cd6a9dSDinh Nguyen compatible = "snps,dw-apb-ssi"; 24378cd6a9dSDinh Nguyen #address-cells = <1>; 24478cd6a9dSDinh Nguyen #size-cells = <0>; 24578cd6a9dSDinh Nguyen reg = <0xffda5000 0x1000>; 24678cd6a9dSDinh Nguyen interrupts = <0 102 4>; 24778cd6a9dSDinh Nguyen num-chipselect = <4>; 24878cd6a9dSDinh Nguyen bus-num = <0>; 24978cd6a9dSDinh Nguyen status = "disabled"; 25078cd6a9dSDinh Nguyen }; 25178cd6a9dSDinh Nguyen 25278cd6a9dSDinh Nguyen sysmgr: sysmgr@ffd12000 { 25378cd6a9dSDinh Nguyen compatible = "altr,sys-mgr", "syscon"; 25478cd6a9dSDinh Nguyen reg = <0xffd12000 0x1000>; 25578cd6a9dSDinh Nguyen }; 25678cd6a9dSDinh Nguyen 25778cd6a9dSDinh Nguyen /* Local timer */ 25878cd6a9dSDinh Nguyen timer { 25978cd6a9dSDinh Nguyen compatible = "arm,armv8-timer"; 260f2a89d3bSMarc Zyngier interrupts = <1 13 0xf08>, 261f2a89d3bSMarc Zyngier <1 14 0xf08>, 262f2a89d3bSMarc Zyngier <1 11 0xf08>, 263f2a89d3bSMarc Zyngier <1 10 0xf08>; 26478cd6a9dSDinh Nguyen }; 26578cd6a9dSDinh Nguyen 26678cd6a9dSDinh Nguyen timer0: timer0@ffc03000 { 26778cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 26878cd6a9dSDinh Nguyen interrupts = <0 113 4>; 26978cd6a9dSDinh Nguyen reg = <0xffc03000 0x100>; 27078cd6a9dSDinh Nguyen }; 27178cd6a9dSDinh Nguyen 27278cd6a9dSDinh Nguyen timer1: timer1@ffc03100 { 27378cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 27478cd6a9dSDinh Nguyen interrupts = <0 114 4>; 27578cd6a9dSDinh Nguyen reg = <0xffc03100 0x100>; 27678cd6a9dSDinh Nguyen }; 27778cd6a9dSDinh Nguyen 27878cd6a9dSDinh Nguyen timer2: timer2@ffd00000 { 27978cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 28078cd6a9dSDinh Nguyen interrupts = <0 115 4>; 28178cd6a9dSDinh Nguyen reg = <0xffd00000 0x100>; 28278cd6a9dSDinh Nguyen }; 28378cd6a9dSDinh Nguyen 28478cd6a9dSDinh Nguyen timer3: timer3@ffd00100 { 28578cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 28678cd6a9dSDinh Nguyen interrupts = <0 116 4>; 28778cd6a9dSDinh Nguyen reg = <0xffd00100 0x100>; 28878cd6a9dSDinh Nguyen }; 28978cd6a9dSDinh Nguyen 29078cd6a9dSDinh Nguyen uart0: serial0@ffc02000 { 29178cd6a9dSDinh Nguyen compatible = "snps,dw-apb-uart"; 29278cd6a9dSDinh Nguyen reg = <0xffc02000 0x100>; 29378cd6a9dSDinh Nguyen interrupts = <0 108 4>; 29478cd6a9dSDinh Nguyen reg-shift = <2>; 29578cd6a9dSDinh Nguyen reg-io-width = <4>; 29678cd6a9dSDinh Nguyen status = "disabled"; 29778cd6a9dSDinh Nguyen }; 29878cd6a9dSDinh Nguyen 29978cd6a9dSDinh Nguyen uart1: serial1@ffc02100 { 30078cd6a9dSDinh Nguyen compatible = "snps,dw-apb-uart"; 30178cd6a9dSDinh Nguyen reg = <0xffc02100 0x100>; 30278cd6a9dSDinh Nguyen interrupts = <0 109 4>; 30378cd6a9dSDinh Nguyen reg-shift = <2>; 30478cd6a9dSDinh Nguyen reg-io-width = <4>; 30578cd6a9dSDinh Nguyen status = "disabled"; 30678cd6a9dSDinh Nguyen }; 30778cd6a9dSDinh Nguyen 30878cd6a9dSDinh Nguyen usbphy0: usbphy@0 { 30978cd6a9dSDinh Nguyen #phy-cells = <0>; 31078cd6a9dSDinh Nguyen compatible = "usb-nop-xceiv"; 31178cd6a9dSDinh Nguyen status = "okay"; 31278cd6a9dSDinh Nguyen }; 31378cd6a9dSDinh Nguyen 31478cd6a9dSDinh Nguyen usb0: usb@ffb00000 { 31578cd6a9dSDinh Nguyen compatible = "snps,dwc2"; 31678cd6a9dSDinh Nguyen reg = <0xffb00000 0x40000>; 31778cd6a9dSDinh Nguyen interrupts = <0 93 4>; 31878cd6a9dSDinh Nguyen phys = <&usbphy0>; 31978cd6a9dSDinh Nguyen phy-names = "usb2-phy"; 32078cd6a9dSDinh Nguyen status = "disabled"; 32178cd6a9dSDinh Nguyen }; 32278cd6a9dSDinh Nguyen 32378cd6a9dSDinh Nguyen usb1: usb@ffb40000 { 32478cd6a9dSDinh Nguyen compatible = "snps,dwc2"; 32578cd6a9dSDinh Nguyen reg = <0xffb40000 0x40000>; 32678cd6a9dSDinh Nguyen interrupts = <0 94 4>; 32778cd6a9dSDinh Nguyen phys = <&usbphy0>; 32878cd6a9dSDinh Nguyen phy-names = "usb2-phy"; 32978cd6a9dSDinh Nguyen status = "disabled"; 33078cd6a9dSDinh Nguyen }; 33178cd6a9dSDinh Nguyen 33278cd6a9dSDinh Nguyen watchdog0: watchdog@ffd00200 { 33378cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 33478cd6a9dSDinh Nguyen reg = <0xffd00200 0x100>; 33578cd6a9dSDinh Nguyen interrupts = <0 117 4>; 33678cd6a9dSDinh Nguyen status = "disabled"; 33778cd6a9dSDinh Nguyen }; 33878cd6a9dSDinh Nguyen 33978cd6a9dSDinh Nguyen watchdog1: watchdog@ffd00300 { 34078cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 34178cd6a9dSDinh Nguyen reg = <0xffd00300 0x100>; 34278cd6a9dSDinh Nguyen interrupts = <0 118 4>; 34378cd6a9dSDinh Nguyen status = "disabled"; 34478cd6a9dSDinh Nguyen }; 34578cd6a9dSDinh Nguyen 34678cd6a9dSDinh Nguyen watchdog2: watchdog@ffd00400 { 34778cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 34878cd6a9dSDinh Nguyen reg = <0xffd00400 0x100>; 34978cd6a9dSDinh Nguyen interrupts = <0 125 4>; 35078cd6a9dSDinh Nguyen status = "disabled"; 35178cd6a9dSDinh Nguyen }; 35278cd6a9dSDinh Nguyen 35378cd6a9dSDinh Nguyen watchdog3: watchdog@ffd00500 { 35478cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 35578cd6a9dSDinh Nguyen reg = <0xffd00500 0x100>; 35678cd6a9dSDinh Nguyen interrupts = <0 126 4>; 35778cd6a9dSDinh Nguyen status = "disabled"; 35878cd6a9dSDinh Nguyen }; 35978cd6a9dSDinh Nguyen }; 36078cd6a9dSDinh Nguyen}; 361