178cd6a9dSDinh Nguyen/* 278cd6a9dSDinh Nguyen * Copyright Altera Corporation (C) 2015. All rights reserved. 378cd6a9dSDinh Nguyen * 478cd6a9dSDinh Nguyen * This program is free software; you can redistribute it and/or modify 578cd6a9dSDinh Nguyen * it under the terms and conditions of the GNU General Public License, 678cd6a9dSDinh Nguyen * version 2, as published by the Free Software Foundation. 778cd6a9dSDinh Nguyen * 878cd6a9dSDinh Nguyen * This program is distributed in the hope it will be useful, but WITHOUT 978cd6a9dSDinh Nguyen * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1078cd6a9dSDinh Nguyen * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1178cd6a9dSDinh Nguyen * more details. 1278cd6a9dSDinh Nguyen * 1378cd6a9dSDinh Nguyen * You should have received a copy of the GNU General Public License along with 1478cd6a9dSDinh Nguyen * this program. If not, see <http://www.gnu.org/licenses/>. 1578cd6a9dSDinh Nguyen */ 1678cd6a9dSDinh Nguyen 1778cd6a9dSDinh Nguyen/dts-v1/; 18e519922eSDinh Nguyen#include <dt-bindings/reset/altr,rst-mgr-s10.h> 195a0e622eSAlan Tull#include <dt-bindings/gpio/gpio.h> 20d93101abSDinh Nguyen#include <dt-bindings/clock/stratix10-clock.h> 2178cd6a9dSDinh Nguyen 2278cd6a9dSDinh Nguyen/ { 2378cd6a9dSDinh Nguyen compatible = "altr,socfpga-stratix10"; 2478cd6a9dSDinh Nguyen #address-cells = <2>; 2578cd6a9dSDinh Nguyen #size-cells = <2>; 2678cd6a9dSDinh Nguyen 2778cd6a9dSDinh Nguyen cpus { 2878cd6a9dSDinh Nguyen #address-cells = <1>; 2978cd6a9dSDinh Nguyen #size-cells = <0>; 3078cd6a9dSDinh Nguyen 3178cd6a9dSDinh Nguyen cpu0: cpu@0 { 3278cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 3378cd6a9dSDinh Nguyen device_type = "cpu"; 3478cd6a9dSDinh Nguyen enable-method = "psci"; 3578cd6a9dSDinh Nguyen reg = <0x0>; 3678cd6a9dSDinh Nguyen }; 3778cd6a9dSDinh Nguyen 3878cd6a9dSDinh Nguyen cpu1: cpu@1 { 3978cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 4078cd6a9dSDinh Nguyen device_type = "cpu"; 4178cd6a9dSDinh Nguyen enable-method = "psci"; 4278cd6a9dSDinh Nguyen reg = <0x1>; 4378cd6a9dSDinh Nguyen }; 4478cd6a9dSDinh Nguyen 4578cd6a9dSDinh Nguyen cpu2: cpu@2 { 4678cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 4778cd6a9dSDinh Nguyen device_type = "cpu"; 4878cd6a9dSDinh Nguyen enable-method = "psci"; 4978cd6a9dSDinh Nguyen reg = <0x2>; 5078cd6a9dSDinh Nguyen }; 5178cd6a9dSDinh Nguyen 5278cd6a9dSDinh Nguyen cpu3: cpu@3 { 5378cd6a9dSDinh Nguyen compatible = "arm,cortex-a53", "arm,armv8"; 5478cd6a9dSDinh Nguyen device_type = "cpu"; 5578cd6a9dSDinh Nguyen enable-method = "psci"; 5678cd6a9dSDinh Nguyen reg = <0x3>; 5778cd6a9dSDinh Nguyen }; 5878cd6a9dSDinh Nguyen }; 5978cd6a9dSDinh Nguyen 6078cd6a9dSDinh Nguyen pmu { 6178cd6a9dSDinh Nguyen compatible = "arm,armv8-pmuv3"; 6278cd6a9dSDinh Nguyen interrupts = <0 120 8>, 6378cd6a9dSDinh Nguyen <0 121 8>, 6478cd6a9dSDinh Nguyen <0 122 8>, 6578cd6a9dSDinh Nguyen <0 123 8>; 6678cd6a9dSDinh Nguyen interrupt-affinity = <&cpu0>, 6778cd6a9dSDinh Nguyen <&cpu1>, 6878cd6a9dSDinh Nguyen <&cpu2>, 6978cd6a9dSDinh Nguyen <&cpu3>; 7069c4d8edSArnd Bergmann interrupt-parent = <&intc>; 7178cd6a9dSDinh Nguyen }; 7278cd6a9dSDinh Nguyen 7378cd6a9dSDinh Nguyen psci { 7478cd6a9dSDinh Nguyen compatible = "arm,psci-0.2"; 7578cd6a9dSDinh Nguyen method = "smc"; 7678cd6a9dSDinh Nguyen }; 7778cd6a9dSDinh Nguyen 7878cd6a9dSDinh Nguyen intc: intc@fffc1000 { 7978cd6a9dSDinh Nguyen compatible = "arm,gic-400", "arm,cortex-a15-gic"; 8078cd6a9dSDinh Nguyen #interrupt-cells = <3>; 8178cd6a9dSDinh Nguyen interrupt-controller; 82f973bfa0SDinh Nguyen reg = <0x0 0xfffc1000 0x0 0x1000>, 83f973bfa0SDinh Nguyen <0x0 0xfffc2000 0x0 0x2000>, 84f973bfa0SDinh Nguyen <0x0 0xfffc4000 0x0 0x2000>, 85f973bfa0SDinh Nguyen <0x0 0xfffc6000 0x0 0x2000>; 8678cd6a9dSDinh Nguyen }; 8778cd6a9dSDinh Nguyen 8878cd6a9dSDinh Nguyen soc { 8978cd6a9dSDinh Nguyen #address-cells = <1>; 9078cd6a9dSDinh Nguyen #size-cells = <1>; 9178cd6a9dSDinh Nguyen compatible = "simple-bus"; 9278cd6a9dSDinh Nguyen device_type = "soc"; 9378cd6a9dSDinh Nguyen interrupt-parent = <&intc>; 9478cd6a9dSDinh Nguyen ranges = <0 0 0 0xffffffff>; 9578cd6a9dSDinh Nguyen 96d93101abSDinh Nguyen clkmgr: clock-controller@ffd10000 { 97d93101abSDinh Nguyen compatible = "intel,stratix10-clkmgr"; 9878cd6a9dSDinh Nguyen reg = <0xffd10000 0x1000>; 99d93101abSDinh Nguyen #clock-cells = <1>; 100d93101abSDinh Nguyen }; 101d93101abSDinh Nguyen 102d93101abSDinh Nguyen clocks { 103d93101abSDinh Nguyen cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 104d93101abSDinh Nguyen #clock-cells = <0>; 105d93101abSDinh Nguyen compatible = "fixed-clock"; 106d93101abSDinh Nguyen }; 107d93101abSDinh Nguyen 108d93101abSDinh Nguyen cb_intosc_ls_clk: cb-intosc-ls-clk { 109d93101abSDinh Nguyen #clock-cells = <0>; 110d93101abSDinh Nguyen compatible = "fixed-clock"; 111d93101abSDinh Nguyen }; 112d93101abSDinh Nguyen 113d93101abSDinh Nguyen f2s_free_clk: f2s-free-clk { 114d93101abSDinh Nguyen #clock-cells = <0>; 115d93101abSDinh Nguyen compatible = "fixed-clock"; 116d93101abSDinh Nguyen }; 117d93101abSDinh Nguyen 118d93101abSDinh Nguyen osc1: osc1 { 119d93101abSDinh Nguyen #clock-cells = <0>; 120d93101abSDinh Nguyen compatible = "fixed-clock"; 121d93101abSDinh Nguyen }; 1220cb140d0SThor Thayer 1230cb140d0SThor Thayer qspi_clk: qspi-clk { 1240cb140d0SThor Thayer #clock-cells = <0>; 1250cb140d0SThor Thayer compatible = "fixed-clock"; 1260cb140d0SThor Thayer clock-frequency = <200000000>; 1270cb140d0SThor Thayer }; 12878cd6a9dSDinh Nguyen }; 12978cd6a9dSDinh Nguyen 13078cd6a9dSDinh Nguyen gmac0: ethernet@ff800000 { 13178cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 13278cd6a9dSDinh Nguyen reg = <0xff800000 0x2000>; 13378cd6a9dSDinh Nguyen interrupts = <0 90 4>; 13478cd6a9dSDinh Nguyen interrupt-names = "macirq"; 13578cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 13605690e8aSDinh Nguyen resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>; 13705690e8aSDinh Nguyen reset-names = "stmmaceth", "stmmaceth-ocp"; 138d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_EMAC0_CLK>; 139d93101abSDinh Nguyen clock-names = "stmmaceth"; 14078cd6a9dSDinh Nguyen status = "disabled"; 14178cd6a9dSDinh Nguyen }; 14278cd6a9dSDinh Nguyen 14378cd6a9dSDinh Nguyen gmac1: ethernet@ff802000 { 14478cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 14578cd6a9dSDinh Nguyen reg = <0xff802000 0x2000>; 14678cd6a9dSDinh Nguyen interrupts = <0 91 4>; 14778cd6a9dSDinh Nguyen interrupt-names = "macirq"; 14878cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 14905690e8aSDinh Nguyen resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>; 15005690e8aSDinh Nguyen reset-names = "stmmaceth", "stmmaceth-ocp"; 151d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_EMAC1_CLK>; 152d93101abSDinh Nguyen clock-names = "stmmaceth"; 15378cd6a9dSDinh Nguyen status = "disabled"; 15478cd6a9dSDinh Nguyen }; 15578cd6a9dSDinh Nguyen 15678cd6a9dSDinh Nguyen gmac2: ethernet@ff804000 { 15778cd6a9dSDinh Nguyen compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac"; 15878cd6a9dSDinh Nguyen reg = <0xff804000 0x2000>; 15978cd6a9dSDinh Nguyen interrupts = <0 92 4>; 16078cd6a9dSDinh Nguyen interrupt-names = "macirq"; 16178cd6a9dSDinh Nguyen mac-address = [00 00 00 00 00 00]; 16205690e8aSDinh Nguyen resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>; 16305690e8aSDinh Nguyen reset-names = "stmmaceth", "stmmaceth-ocp"; 164d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_EMAC2_CLK>; 165d93101abSDinh Nguyen clock-names = "stmmaceth"; 16678cd6a9dSDinh Nguyen status = "disabled"; 16778cd6a9dSDinh Nguyen }; 16878cd6a9dSDinh Nguyen 16978cd6a9dSDinh Nguyen gpio0: gpio@ffc03200 { 17078cd6a9dSDinh Nguyen #address-cells = <1>; 17178cd6a9dSDinh Nguyen #size-cells = <0>; 17278cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio"; 17378cd6a9dSDinh Nguyen reg = <0xffc03200 0x100>; 174788251faSDinh Nguyen resets = <&rst GPIO0_RESET>; 17578cd6a9dSDinh Nguyen status = "disabled"; 17678cd6a9dSDinh Nguyen 17778cd6a9dSDinh Nguyen porta: gpio-controller@0 { 17878cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio-port"; 17978cd6a9dSDinh Nguyen gpio-controller; 18078cd6a9dSDinh Nguyen #gpio-cells = <2>; 18178cd6a9dSDinh Nguyen snps,nr-gpios = <24>; 18278cd6a9dSDinh Nguyen reg = <0>; 18378cd6a9dSDinh Nguyen interrupt-controller; 18478cd6a9dSDinh Nguyen #interrupt-cells = <2>; 18578cd6a9dSDinh Nguyen interrupts = <0 110 4>; 18678cd6a9dSDinh Nguyen }; 18778cd6a9dSDinh Nguyen }; 18878cd6a9dSDinh Nguyen 18978cd6a9dSDinh Nguyen gpio1: gpio@ffc03300 { 19078cd6a9dSDinh Nguyen #address-cells = <1>; 19178cd6a9dSDinh Nguyen #size-cells = <0>; 19278cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio"; 19378cd6a9dSDinh Nguyen reg = <0xffc03300 0x100>; 194788251faSDinh Nguyen resets = <&rst GPIO1_RESET>; 19578cd6a9dSDinh Nguyen status = "disabled"; 19678cd6a9dSDinh Nguyen 19778cd6a9dSDinh Nguyen portb: gpio-controller@0 { 19878cd6a9dSDinh Nguyen compatible = "snps,dw-apb-gpio-port"; 19978cd6a9dSDinh Nguyen gpio-controller; 20078cd6a9dSDinh Nguyen #gpio-cells = <2>; 20178cd6a9dSDinh Nguyen snps,nr-gpios = <24>; 20278cd6a9dSDinh Nguyen reg = <0>; 20378cd6a9dSDinh Nguyen interrupt-controller; 20478cd6a9dSDinh Nguyen #interrupt-cells = <2>; 205a067fb42SDinh Nguyen interrupts = <0 111 4>; 20678cd6a9dSDinh Nguyen }; 20778cd6a9dSDinh Nguyen }; 20878cd6a9dSDinh Nguyen 20978cd6a9dSDinh Nguyen i2c0: i2c@ffc02800 { 21078cd6a9dSDinh Nguyen #address-cells = <1>; 21178cd6a9dSDinh Nguyen #size-cells = <0>; 21278cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 21378cd6a9dSDinh Nguyen reg = <0xffc02800 0x100>; 21478cd6a9dSDinh Nguyen interrupts = <0 103 4>; 215788251faSDinh Nguyen resets = <&rst I2C0_RESET>; 216eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 21778cd6a9dSDinh Nguyen status = "disabled"; 21878cd6a9dSDinh Nguyen }; 21978cd6a9dSDinh Nguyen 22078cd6a9dSDinh Nguyen i2c1: i2c@ffc02900 { 22178cd6a9dSDinh Nguyen #address-cells = <1>; 22278cd6a9dSDinh Nguyen #size-cells = <0>; 22378cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 22478cd6a9dSDinh Nguyen reg = <0xffc02900 0x100>; 22578cd6a9dSDinh Nguyen interrupts = <0 104 4>; 226788251faSDinh Nguyen resets = <&rst I2C1_RESET>; 227eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 22878cd6a9dSDinh Nguyen status = "disabled"; 22978cd6a9dSDinh Nguyen }; 23078cd6a9dSDinh Nguyen 23178cd6a9dSDinh Nguyen i2c2: i2c@ffc02a00 { 23278cd6a9dSDinh Nguyen #address-cells = <1>; 23378cd6a9dSDinh Nguyen #size-cells = <0>; 23478cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 23578cd6a9dSDinh Nguyen reg = <0xffc02a00 0x100>; 23678cd6a9dSDinh Nguyen interrupts = <0 105 4>; 237788251faSDinh Nguyen resets = <&rst I2C2_RESET>; 238eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 23978cd6a9dSDinh Nguyen status = "disabled"; 24078cd6a9dSDinh Nguyen }; 24178cd6a9dSDinh Nguyen 24278cd6a9dSDinh Nguyen i2c3: i2c@ffc02b00 { 24378cd6a9dSDinh Nguyen #address-cells = <1>; 24478cd6a9dSDinh Nguyen #size-cells = <0>; 24578cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 24678cd6a9dSDinh Nguyen reg = <0xffc02b00 0x100>; 24778cd6a9dSDinh Nguyen interrupts = <0 106 4>; 248788251faSDinh Nguyen resets = <&rst I2C3_RESET>; 249eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 25078cd6a9dSDinh Nguyen status = "disabled"; 25178cd6a9dSDinh Nguyen }; 25278cd6a9dSDinh Nguyen 25378cd6a9dSDinh Nguyen i2c4: i2c@ffc02c00 { 25478cd6a9dSDinh Nguyen #address-cells = <1>; 25578cd6a9dSDinh Nguyen #size-cells = <0>; 25678cd6a9dSDinh Nguyen compatible = "snps,designware-i2c"; 25778cd6a9dSDinh Nguyen reg = <0xffc02c00 0x100>; 25878cd6a9dSDinh Nguyen interrupts = <0 107 4>; 259788251faSDinh Nguyen resets = <&rst I2C4_RESET>; 260eebee19eSAlan Tull clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 26178cd6a9dSDinh Nguyen status = "disabled"; 26278cd6a9dSDinh Nguyen }; 26378cd6a9dSDinh Nguyen 26478cd6a9dSDinh Nguyen mmc: dwmmc0@ff808000 { 26578cd6a9dSDinh Nguyen #address-cells = <1>; 26678cd6a9dSDinh Nguyen #size-cells = <0>; 26778cd6a9dSDinh Nguyen compatible = "altr,socfpga-dw-mshc"; 26878cd6a9dSDinh Nguyen reg = <0xff808000 0x1000>; 26978cd6a9dSDinh Nguyen interrupts = <0 96 4>; 27078cd6a9dSDinh Nguyen fifo-depth = <0x400>; 271788251faSDinh Nguyen resets = <&rst SDMMC_RESET>; 272788251faSDinh Nguyen reset-names = "reset"; 273d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_MP_CLK>, 274d93101abSDinh Nguyen <&clkmgr STRATIX10_SDMMC_CLK>; 275d93101abSDinh Nguyen clock-names = "biu", "ciu"; 27678cd6a9dSDinh Nguyen status = "disabled"; 27778cd6a9dSDinh Nguyen }; 27878cd6a9dSDinh Nguyen 27978cd6a9dSDinh Nguyen ocram: sram@ffe00000 { 28078cd6a9dSDinh Nguyen compatible = "mmio-sram"; 28178cd6a9dSDinh Nguyen reg = <0xffe00000 0x100000>; 28278cd6a9dSDinh Nguyen }; 28378cd6a9dSDinh Nguyen 284ab50a444SGraham Moore pdma: pdma@ffda0000 { 285ab50a444SGraham Moore compatible = "arm,pl330", "arm,primecell"; 286ab50a444SGraham Moore reg = <0xffda0000 0x1000>; 287ab50a444SGraham Moore interrupts = <0 81 4>, 288ab50a444SGraham Moore <0 82 4>, 289ab50a444SGraham Moore <0 83 4>, 290ab50a444SGraham Moore <0 84 4>, 291ab50a444SGraham Moore <0 85 4>, 292ab50a444SGraham Moore <0 86 4>, 293ab50a444SGraham Moore <0 87 4>, 294ab50a444SGraham Moore <0 88 4>, 295ab50a444SGraham Moore <0 89 4>; 296ab50a444SGraham Moore #dma-cells = <1>; 297ab50a444SGraham Moore #dma-channels = <8>; 298ab50a444SGraham Moore #dma-requests = <32>; 299ab50a444SGraham Moore clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 300ab50a444SGraham Moore clock-names = "apb_pclk"; 301ab50a444SGraham Moore }; 302ab50a444SGraham Moore 30378cd6a9dSDinh Nguyen rst: rstmgr@ffd11000 { 30478cd6a9dSDinh Nguyen #reset-cells = <1>; 30578cd6a9dSDinh Nguyen compatible = "altr,rst-mgr"; 30678cd6a9dSDinh Nguyen reg = <0xffd11000 0x1000>; 3077691d626SDinh Nguyen altr,modrst-offset = <0x20>; 30878cd6a9dSDinh Nguyen }; 30978cd6a9dSDinh Nguyen 31078cd6a9dSDinh Nguyen spi0: spi@ffda4000 { 31178cd6a9dSDinh Nguyen compatible = "snps,dw-apb-ssi"; 31278cd6a9dSDinh Nguyen #address-cells = <1>; 31378cd6a9dSDinh Nguyen #size-cells = <0>; 31478cd6a9dSDinh Nguyen reg = <0xffda4000 0x1000>; 315889d1509SThor Thayer interrupts = <0 99 4>; 316889d1509SThor Thayer resets = <&rst SPIM0_RESET>; 317889d1509SThor Thayer reg-io-width = <4>; 3184595299cSThor Thayer num-cs = <4>; 31970455ac7SThor Thayer clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 32078cd6a9dSDinh Nguyen status = "disabled"; 32178cd6a9dSDinh Nguyen }; 32278cd6a9dSDinh Nguyen 32378cd6a9dSDinh Nguyen spi1: spi@ffda5000 { 32478cd6a9dSDinh Nguyen compatible = "snps,dw-apb-ssi"; 32578cd6a9dSDinh Nguyen #address-cells = <1>; 32678cd6a9dSDinh Nguyen #size-cells = <0>; 32778cd6a9dSDinh Nguyen reg = <0xffda5000 0x1000>; 328889d1509SThor Thayer interrupts = <0 100 4>; 329889d1509SThor Thayer resets = <&rst SPIM1_RESET>; 330889d1509SThor Thayer reg-io-width = <4>; 3314595299cSThor Thayer num-cs = <4>; 33270455ac7SThor Thayer clocks = <&clkmgr STRATIX10_L4_MAIN_CLK>; 33378cd6a9dSDinh Nguyen status = "disabled"; 33478cd6a9dSDinh Nguyen }; 33578cd6a9dSDinh Nguyen 33678cd6a9dSDinh Nguyen sysmgr: sysmgr@ffd12000 { 33778cd6a9dSDinh Nguyen compatible = "altr,sys-mgr", "syscon"; 33878cd6a9dSDinh Nguyen reg = <0xffd12000 0x1000>; 33978cd6a9dSDinh Nguyen }; 34078cd6a9dSDinh Nguyen 34178cd6a9dSDinh Nguyen /* Local timer */ 34278cd6a9dSDinh Nguyen timer { 34378cd6a9dSDinh Nguyen compatible = "arm,armv8-timer"; 344f2a89d3bSMarc Zyngier interrupts = <1 13 0xf08>, 345f2a89d3bSMarc Zyngier <1 14 0xf08>, 346f2a89d3bSMarc Zyngier <1 11 0xf08>, 347f2a89d3bSMarc Zyngier <1 10 0xf08>; 34878cd6a9dSDinh Nguyen }; 34978cd6a9dSDinh Nguyen 35078cd6a9dSDinh Nguyen timer0: timer0@ffc03000 { 35178cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 35278cd6a9dSDinh Nguyen interrupts = <0 113 4>; 35378cd6a9dSDinh Nguyen reg = <0xffc03000 0x100>; 354d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 355d93101abSDinh Nguyen clock-names = "timer"; 35678cd6a9dSDinh Nguyen }; 35778cd6a9dSDinh Nguyen 35878cd6a9dSDinh Nguyen timer1: timer1@ffc03100 { 35978cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 36078cd6a9dSDinh Nguyen interrupts = <0 114 4>; 36178cd6a9dSDinh Nguyen reg = <0xffc03100 0x100>; 362d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 363d93101abSDinh Nguyen clock-names = "timer"; 36478cd6a9dSDinh Nguyen }; 36578cd6a9dSDinh Nguyen 36678cd6a9dSDinh Nguyen timer2: timer2@ffd00000 { 36778cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 36878cd6a9dSDinh Nguyen interrupts = <0 115 4>; 36978cd6a9dSDinh Nguyen reg = <0xffd00000 0x100>; 370d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 371d93101abSDinh Nguyen clock-names = "timer"; 37278cd6a9dSDinh Nguyen }; 37378cd6a9dSDinh Nguyen 37478cd6a9dSDinh Nguyen timer3: timer3@ffd00100 { 37578cd6a9dSDinh Nguyen compatible = "snps,dw-apb-timer"; 37678cd6a9dSDinh Nguyen interrupts = <0 116 4>; 37778cd6a9dSDinh Nguyen reg = <0xffd00100 0x100>; 378d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 379d93101abSDinh Nguyen clock-names = "timer"; 38078cd6a9dSDinh Nguyen }; 38178cd6a9dSDinh Nguyen 38278cd6a9dSDinh Nguyen uart0: serial0@ffc02000 { 38378cd6a9dSDinh Nguyen compatible = "snps,dw-apb-uart"; 38478cd6a9dSDinh Nguyen reg = <0xffc02000 0x100>; 38578cd6a9dSDinh Nguyen interrupts = <0 108 4>; 38678cd6a9dSDinh Nguyen reg-shift = <2>; 38778cd6a9dSDinh Nguyen reg-io-width = <4>; 388788251faSDinh Nguyen resets = <&rst UART0_RESET>; 389d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 39078cd6a9dSDinh Nguyen status = "disabled"; 39178cd6a9dSDinh Nguyen }; 39278cd6a9dSDinh Nguyen 39378cd6a9dSDinh Nguyen uart1: serial1@ffc02100 { 39478cd6a9dSDinh Nguyen compatible = "snps,dw-apb-uart"; 39578cd6a9dSDinh Nguyen reg = <0xffc02100 0x100>; 39678cd6a9dSDinh Nguyen interrupts = <0 109 4>; 39778cd6a9dSDinh Nguyen reg-shift = <2>; 39878cd6a9dSDinh Nguyen reg-io-width = <4>; 399788251faSDinh Nguyen resets = <&rst UART1_RESET>; 400d93101abSDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SP_CLK>; 40178cd6a9dSDinh Nguyen status = "disabled"; 40278cd6a9dSDinh Nguyen }; 40378cd6a9dSDinh Nguyen 40478cd6a9dSDinh Nguyen usbphy0: usbphy@0 { 40578cd6a9dSDinh Nguyen #phy-cells = <0>; 40678cd6a9dSDinh Nguyen compatible = "usb-nop-xceiv"; 40778cd6a9dSDinh Nguyen status = "okay"; 40878cd6a9dSDinh Nguyen }; 40978cd6a9dSDinh Nguyen 41078cd6a9dSDinh Nguyen usb0: usb@ffb00000 { 41178cd6a9dSDinh Nguyen compatible = "snps,dwc2"; 41278cd6a9dSDinh Nguyen reg = <0xffb00000 0x40000>; 41378cd6a9dSDinh Nguyen interrupts = <0 93 4>; 41478cd6a9dSDinh Nguyen phys = <&usbphy0>; 41578cd6a9dSDinh Nguyen phy-names = "usb2-phy"; 41633af8ca0SDinh Nguyen resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 41733af8ca0SDinh Nguyen reset-names = "dwc2", "dwc2-ecc"; 41803761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_USB_CLK>; 41978cd6a9dSDinh Nguyen status = "disabled"; 42078cd6a9dSDinh Nguyen }; 42178cd6a9dSDinh Nguyen 42278cd6a9dSDinh Nguyen usb1: usb@ffb40000 { 42378cd6a9dSDinh Nguyen compatible = "snps,dwc2"; 42478cd6a9dSDinh Nguyen reg = <0xffb40000 0x40000>; 42578cd6a9dSDinh Nguyen interrupts = <0 94 4>; 42678cd6a9dSDinh Nguyen phys = <&usbphy0>; 42778cd6a9dSDinh Nguyen phy-names = "usb2-phy"; 42833af8ca0SDinh Nguyen resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>; 42933af8ca0SDinh Nguyen reset-names = "dwc2", "dwc2-ecc"; 43003761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_USB_CLK>; 43178cd6a9dSDinh Nguyen status = "disabled"; 43278cd6a9dSDinh Nguyen }; 43378cd6a9dSDinh Nguyen 43478cd6a9dSDinh Nguyen watchdog0: watchdog@ffd00200 { 43578cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 43678cd6a9dSDinh Nguyen reg = <0xffd00200 0x100>; 43778cd6a9dSDinh Nguyen interrupts = <0 117 4>; 438788251faSDinh Nguyen resets = <&rst WATCHDOG0_RESET>; 43903761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 44078cd6a9dSDinh Nguyen status = "disabled"; 44178cd6a9dSDinh Nguyen }; 44278cd6a9dSDinh Nguyen 44378cd6a9dSDinh Nguyen watchdog1: watchdog@ffd00300 { 44478cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 44578cd6a9dSDinh Nguyen reg = <0xffd00300 0x100>; 44678cd6a9dSDinh Nguyen interrupts = <0 118 4>; 447788251faSDinh Nguyen resets = <&rst WATCHDOG1_RESET>; 44803761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 44978cd6a9dSDinh Nguyen status = "disabled"; 45078cd6a9dSDinh Nguyen }; 45178cd6a9dSDinh Nguyen 45278cd6a9dSDinh Nguyen watchdog2: watchdog@ffd00400 { 45378cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 45478cd6a9dSDinh Nguyen reg = <0xffd00400 0x100>; 45578cd6a9dSDinh Nguyen interrupts = <0 125 4>; 456788251faSDinh Nguyen resets = <&rst WATCHDOG2_RESET>; 45703761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 45878cd6a9dSDinh Nguyen status = "disabled"; 45978cd6a9dSDinh Nguyen }; 46078cd6a9dSDinh Nguyen 46178cd6a9dSDinh Nguyen watchdog3: watchdog@ffd00500 { 46278cd6a9dSDinh Nguyen compatible = "snps,dw-wdt"; 46378cd6a9dSDinh Nguyen reg = <0xffd00500 0x100>; 46478cd6a9dSDinh Nguyen interrupts = <0 126 4>; 465788251faSDinh Nguyen resets = <&rst WATCHDOG3_RESET>; 46603761ab1SDinh Nguyen clocks = <&clkmgr STRATIX10_L4_SYS_FREE_CLK>; 46778cd6a9dSDinh Nguyen status = "disabled"; 46878cd6a9dSDinh Nguyen }; 46991fdd827SThor Thayer 470446fd7afSThor Thayer sdr: sdr@f8011100 { 471446fd7afSThor Thayer compatible = "altr,sdr-ctl", "syscon"; 472446fd7afSThor Thayer reg = <0xf8011100 0xc0>; 473446fd7afSThor Thayer }; 474446fd7afSThor Thayer 47591fdd827SThor Thayer eccmgr { 47691fdd827SThor Thayer compatible = "altr,socfpga-s10-ecc-manager"; 4773ce078ffSThor Thayer altr,sysmgr-syscon = <&sysmgr>; 4783ce078ffSThor Thayer #address-cells = <1>; 4793ce078ffSThor Thayer #size-cells = <1>; 48091fdd827SThor Thayer interrupts = <0 15 4>, <0 95 4>; 48191fdd827SThor Thayer interrupt-controller; 48291fdd827SThor Thayer #interrupt-cells = <2>; 4833ce078ffSThor Thayer ranges; 48491fdd827SThor Thayer 48591fdd827SThor Thayer sdramedac { 48691fdd827SThor Thayer compatible = "altr,sdram-edac-s10"; 487446fd7afSThor Thayer altr,sdr-syscon = <&sdr>; 48891fdd827SThor Thayer interrupts = <16 4>, <48 4>; 48991fdd827SThor Thayer }; 49091fdd827SThor Thayer }; 4910cb140d0SThor Thayer 4920cb140d0SThor Thayer qspi: spi@ff8d2000 { 4930cb140d0SThor Thayer compatible = "cdns,qspi-nor"; 4940cb140d0SThor Thayer #address-cells = <1>; 4950cb140d0SThor Thayer #size-cells = <0>; 4960cb140d0SThor Thayer reg = <0xff8d2000 0x100>, 4970cb140d0SThor Thayer <0xff900000 0x100000>; 4980cb140d0SThor Thayer interrupts = <0 3 4>; 4990cb140d0SThor Thayer cdns,fifo-depth = <128>; 5000cb140d0SThor Thayer cdns,fifo-width = <4>; 5010cb140d0SThor Thayer cdns,trigger-address = <0x00000000>; 5020cb140d0SThor Thayer clocks = <&qspi_clk>; 5030cb140d0SThor Thayer 5040cb140d0SThor Thayer status = "disabled"; 5050cb140d0SThor Thayer }; 50678cd6a9dSDinh Nguyen }; 50778cd6a9dSDinh Nguyen}; 508