1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2/* 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-h6-ccu.h> 8#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9#include <dt-bindings/clock/sun8i-de2.h> 10#include <dt-bindings/clock/sun8i-tcon-top.h> 11#include <dt-bindings/reset/sun50i-h6-ccu.h> 12#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 13#include <dt-bindings/reset/sun8i-de2.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a53"; 26 device_type = "cpu"; 27 reg = <0>; 28 enable-method = "psci"; 29 }; 30 31 cpu1: cpu@1 { 32 compatible = "arm,cortex-a53"; 33 device_type = "cpu"; 34 reg = <1>; 35 enable-method = "psci"; 36 }; 37 38 cpu2: cpu@2 { 39 compatible = "arm,cortex-a53"; 40 device_type = "cpu"; 41 reg = <2>; 42 enable-method = "psci"; 43 }; 44 45 cpu3: cpu@3 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 reg = <3>; 49 enable-method = "psci"; 50 }; 51 }; 52 53 de: display-engine { 54 compatible = "allwinner,sun50i-h6-display-engine"; 55 allwinner,pipelines = <&mixer0>; 56 status = "disabled"; 57 }; 58 59 osc24M: osc24M_clk { 60 #clock-cells = <0>; 61 compatible = "fixed-clock"; 62 clock-frequency = <24000000>; 63 clock-output-names = "osc24M"; 64 }; 65 66 ext_osc32k: ext_osc32k_clk { 67 #clock-cells = <0>; 68 compatible = "fixed-clock"; 69 clock-frequency = <32768>; 70 clock-output-names = "ext_osc32k"; 71 }; 72 73 psci { 74 compatible = "arm,psci-0.2"; 75 method = "smc"; 76 }; 77 78 timer { 79 compatible = "arm,armv8-timer"; 80 interrupts = <GIC_PPI 13 81 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 82 <GIC_PPI 14 83 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 84 <GIC_PPI 11 85 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 86 <GIC_PPI 10 87 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 88 }; 89 90 soc { 91 compatible = "simple-bus"; 92 #address-cells = <1>; 93 #size-cells = <1>; 94 ranges; 95 96 bus@1000000 { 97 compatible = "allwinner,sun50i-h6-de3", 98 "allwinner,sun50i-a64-de2"; 99 reg = <0x1000000 0x400000>; 100 allwinner,sram = <&de2_sram 1>; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 ranges = <0 0x1000000 0x400000>; 104 105 display_clocks: clock@0 { 106 compatible = "allwinner,sun50i-h6-de3-clk"; 107 reg = <0x0 0x10000>; 108 clocks = <&ccu CLK_DE>, 109 <&ccu CLK_BUS_DE>; 110 clock-names = "mod", 111 "bus"; 112 resets = <&ccu RST_BUS_DE>; 113 #clock-cells = <1>; 114 #reset-cells = <1>; 115 }; 116 117 mixer0: mixer@100000 { 118 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 119 reg = <0x100000 0x100000>; 120 clocks = <&display_clocks CLK_BUS_MIXER0>, 121 <&display_clocks CLK_MIXER0>; 122 clock-names = "bus", 123 "mod"; 124 resets = <&display_clocks RST_MIXER0>; 125 126 ports { 127 #address-cells = <1>; 128 #size-cells = <0>; 129 130 mixer0_out: port@1 { 131 reg = <1>; 132 133 mixer0_out_tcon_top_mixer0: endpoint { 134 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 135 }; 136 }; 137 }; 138 }; 139 }; 140 141 video-codec@1c0e000 { 142 compatible = "allwinner,sun50i-h6-video-engine"; 143 reg = <0x01c0e000 0x2000>; 144 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 145 <&ccu CLK_MBUS_VE>; 146 clock-names = "ahb", "mod", "ram"; 147 resets = <&ccu RST_BUS_VE>; 148 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 149 allwinner,sram = <&ve_sram 1>; 150 }; 151 152 gpu: gpu@1800000 { 153 compatible = "allwinner,sun50i-h6-mali", 154 "arm,mali-t720"; 155 reg = <0x01800000 0x4000>; 156 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 159 interrupt-names = "job", "mmu", "gpu"; 160 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 161 clock-names = "core", "bus"; 162 resets = <&ccu RST_BUS_GPU>; 163 status = "disabled"; 164 }; 165 166 crypto: crypto@1904000 { 167 compatible = "allwinner,sun50i-h6-crypto"; 168 reg = <0x01904000 0x1000>; 169 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 170 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; 171 clock-names = "bus", "mod", "ram"; 172 resets = <&ccu RST_BUS_CE>; 173 }; 174 175 syscon: syscon@3000000 { 176 compatible = "allwinner,sun50i-h6-system-control", 177 "allwinner,sun50i-a64-system-control"; 178 reg = <0x03000000 0x1000>; 179 #address-cells = <1>; 180 #size-cells = <1>; 181 ranges; 182 183 sram_c: sram@28000 { 184 compatible = "mmio-sram"; 185 reg = <0x00028000 0x1e000>; 186 #address-cells = <1>; 187 #size-cells = <1>; 188 ranges = <0 0x00028000 0x1e000>; 189 190 de2_sram: sram-section@0 { 191 compatible = "allwinner,sun50i-h6-sram-c", 192 "allwinner,sun50i-a64-sram-c"; 193 reg = <0x0000 0x1e000>; 194 }; 195 }; 196 197 sram_c1: sram@1a00000 { 198 compatible = "mmio-sram"; 199 reg = <0x01a00000 0x200000>; 200 #address-cells = <1>; 201 #size-cells = <1>; 202 ranges = <0 0x01a00000 0x200000>; 203 204 ve_sram: sram-section@0 { 205 compatible = "allwinner,sun50i-h6-sram-c1", 206 "allwinner,sun4i-a10-sram-c1"; 207 reg = <0x000000 0x200000>; 208 }; 209 }; 210 }; 211 212 ccu: clock@3001000 { 213 compatible = "allwinner,sun50i-h6-ccu"; 214 reg = <0x03001000 0x1000>; 215 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; 216 clock-names = "hosc", "losc", "iosc"; 217 #clock-cells = <1>; 218 #reset-cells = <1>; 219 }; 220 221 dma: dma-controller@3002000 { 222 compatible = "allwinner,sun50i-h6-dma"; 223 reg = <0x03002000 0x1000>; 224 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 226 clock-names = "bus", "mbus"; 227 dma-channels = <16>; 228 dma-requests = <46>; 229 resets = <&ccu RST_BUS_DMA>; 230 #dma-cells = <1>; 231 }; 232 233 sid: efuse@3006000 { 234 compatible = "allwinner,sun50i-h6-sid"; 235 reg = <0x03006000 0x400>; 236 }; 237 238 watchdog: watchdog@30090a0 { 239 compatible = "allwinner,sun50i-h6-wdt", 240 "allwinner,sun6i-a31-wdt"; 241 reg = <0x030090a0 0x20>; 242 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&osc24M>; 244 /* Broken on some H6 boards */ 245 status = "disabled"; 246 }; 247 248 pio: pinctrl@300b000 { 249 compatible = "allwinner,sun50i-h6-pinctrl"; 250 reg = <0x0300b000 0x400>; 251 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 252 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 253 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 254 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; 256 clock-names = "apb", "hosc", "losc"; 257 gpio-controller; 258 #gpio-cells = <3>; 259 interrupt-controller; 260 #interrupt-cells = <3>; 261 262 ext_rgmii_pins: rgmii-pins { 263 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 264 "PD5", "PD7", "PD8", "PD9", "PD10", 265 "PD11", "PD12", "PD13", "PD19", "PD20"; 266 function = "emac"; 267 drive-strength = <40>; 268 }; 269 270 hdmi_pins: hdmi-pins { 271 pins = "PH8", "PH9", "PH10"; 272 function = "hdmi"; 273 }; 274 275 i2c0_pins: i2c0-pins { 276 pins = "PD25", "PD26"; 277 function = "i2c0"; 278 }; 279 280 i2c1_pins: i2c1-pins { 281 pins = "PH5", "PH6"; 282 function = "i2c1"; 283 }; 284 285 i2c2_pins: i2c2-pins { 286 pins = "PD23", "PD24"; 287 function = "i2c2"; 288 }; 289 290 mmc0_pins: mmc0-pins { 291 pins = "PF0", "PF1", "PF2", "PF3", 292 "PF4", "PF5"; 293 function = "mmc0"; 294 drive-strength = <30>; 295 bias-pull-up; 296 }; 297 298 /omit-if-no-ref/ 299 mmc1_pins: mmc1-pins { 300 pins = "PG0", "PG1", "PG2", "PG3", 301 "PG4", "PG5"; 302 function = "mmc1"; 303 drive-strength = <30>; 304 bias-pull-up; 305 }; 306 307 mmc2_pins: mmc2-pins { 308 pins = "PC1", "PC4", "PC5", "PC6", 309 "PC7", "PC8", "PC9", "PC10", 310 "PC11", "PC12", "PC13", "PC14"; 311 function = "mmc2"; 312 drive-strength = <30>; 313 bias-pull-up; 314 }; 315 316 spdif_tx_pin: spdif-tx-pin { 317 pins = "PH7"; 318 function = "spdif"; 319 }; 320 321 uart0_ph_pins: uart0-ph-pins { 322 pins = "PH0", "PH1"; 323 function = "uart0"; 324 }; 325 326 uart1_pins: uart1-pins { 327 pins = "PG6", "PG7"; 328 function = "uart1"; 329 }; 330 331 uart1_rts_cts_pins: uart1-rts-cts-pins { 332 pins = "PG8", "PG9"; 333 function = "uart1"; 334 }; 335 }; 336 337 gic: interrupt-controller@3021000 { 338 compatible = "arm,gic-400"; 339 reg = <0x03021000 0x1000>, 340 <0x03022000 0x2000>, 341 <0x03024000 0x2000>, 342 <0x03026000 0x2000>; 343 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 344 interrupt-controller; 345 #interrupt-cells = <3>; 346 }; 347 348 mmc0: mmc@4020000 { 349 compatible = "allwinner,sun50i-h6-mmc", 350 "allwinner,sun50i-a64-mmc"; 351 reg = <0x04020000 0x1000>; 352 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 353 clock-names = "ahb", "mmc"; 354 resets = <&ccu RST_BUS_MMC0>; 355 reset-names = "ahb"; 356 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 357 pinctrl-names = "default"; 358 pinctrl-0 = <&mmc0_pins>; 359 status = "disabled"; 360 #address-cells = <1>; 361 #size-cells = <0>; 362 }; 363 364 mmc1: mmc@4021000 { 365 compatible = "allwinner,sun50i-h6-mmc", 366 "allwinner,sun50i-a64-mmc"; 367 reg = <0x04021000 0x1000>; 368 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 369 clock-names = "ahb", "mmc"; 370 resets = <&ccu RST_BUS_MMC1>; 371 reset-names = "ahb"; 372 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&mmc1_pins>; 375 status = "disabled"; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 }; 379 380 mmc2: mmc@4022000 { 381 compatible = "allwinner,sun50i-h6-emmc", 382 "allwinner,sun50i-a64-emmc"; 383 reg = <0x04022000 0x1000>; 384 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 385 clock-names = "ahb", "mmc"; 386 resets = <&ccu RST_BUS_MMC2>; 387 reset-names = "ahb"; 388 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 389 pinctrl-names = "default"; 390 pinctrl-0 = <&mmc2_pins>; 391 status = "disabled"; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 }; 395 396 uart0: serial@5000000 { 397 compatible = "snps,dw-apb-uart"; 398 reg = <0x05000000 0x400>; 399 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 400 reg-shift = <2>; 401 reg-io-width = <4>; 402 clocks = <&ccu CLK_BUS_UART0>; 403 resets = <&ccu RST_BUS_UART0>; 404 status = "disabled"; 405 }; 406 407 uart1: serial@5000400 { 408 compatible = "snps,dw-apb-uart"; 409 reg = <0x05000400 0x400>; 410 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 411 reg-shift = <2>; 412 reg-io-width = <4>; 413 clocks = <&ccu CLK_BUS_UART1>; 414 resets = <&ccu RST_BUS_UART1>; 415 status = "disabled"; 416 }; 417 418 uart2: serial@5000800 { 419 compatible = "snps,dw-apb-uart"; 420 reg = <0x05000800 0x400>; 421 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 422 reg-shift = <2>; 423 reg-io-width = <4>; 424 clocks = <&ccu CLK_BUS_UART2>; 425 resets = <&ccu RST_BUS_UART2>; 426 status = "disabled"; 427 }; 428 429 uart3: serial@5000c00 { 430 compatible = "snps,dw-apb-uart"; 431 reg = <0x05000c00 0x400>; 432 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 433 reg-shift = <2>; 434 reg-io-width = <4>; 435 clocks = <&ccu CLK_BUS_UART3>; 436 resets = <&ccu RST_BUS_UART3>; 437 status = "disabled"; 438 }; 439 440 i2c0: i2c@5002000 { 441 compatible = "allwinner,sun50i-h6-i2c", 442 "allwinner,sun6i-a31-i2c"; 443 reg = <0x05002000 0x400>; 444 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&ccu CLK_BUS_I2C0>; 446 resets = <&ccu RST_BUS_I2C0>; 447 pinctrl-names = "default"; 448 pinctrl-0 = <&i2c0_pins>; 449 status = "disabled"; 450 #address-cells = <1>; 451 #size-cells = <0>; 452 }; 453 454 i2c1: i2c@5002400 { 455 compatible = "allwinner,sun50i-h6-i2c", 456 "allwinner,sun6i-a31-i2c"; 457 reg = <0x05002400 0x400>; 458 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 459 clocks = <&ccu CLK_BUS_I2C1>; 460 resets = <&ccu RST_BUS_I2C1>; 461 pinctrl-names = "default"; 462 pinctrl-0 = <&i2c1_pins>; 463 status = "disabled"; 464 #address-cells = <1>; 465 #size-cells = <0>; 466 }; 467 468 i2c2: i2c@5002800 { 469 compatible = "allwinner,sun50i-h6-i2c", 470 "allwinner,sun6i-a31-i2c"; 471 reg = <0x05002800 0x400>; 472 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&ccu CLK_BUS_I2C2>; 474 resets = <&ccu RST_BUS_I2C2>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&i2c2_pins>; 477 status = "disabled"; 478 #address-cells = <1>; 479 #size-cells = <0>; 480 }; 481 482 emac: ethernet@5020000 { 483 compatible = "allwinner,sun50i-h6-emac", 484 "allwinner,sun50i-a64-emac"; 485 syscon = <&syscon>; 486 reg = <0x05020000 0x10000>; 487 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 488 interrupt-names = "macirq"; 489 resets = <&ccu RST_BUS_EMAC>; 490 reset-names = "stmmaceth"; 491 clocks = <&ccu CLK_BUS_EMAC>; 492 clock-names = "stmmaceth"; 493 status = "disabled"; 494 495 mdio: mdio { 496 compatible = "snps,dwmac-mdio"; 497 #address-cells = <1>; 498 #size-cells = <0>; 499 }; 500 }; 501 502 spdif: spdif@5093000 { 503 #sound-dai-cells = <0>; 504 compatible = "allwinner,sun50i-h6-spdif"; 505 reg = <0x05093000 0x400>; 506 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 508 clock-names = "apb", "spdif"; 509 resets = <&ccu RST_BUS_SPDIF>; 510 dmas = <&dma 2>; 511 dma-names = "tx"; 512 pinctrl-names = "default"; 513 pinctrl-0 = <&spdif_tx_pin>; 514 status = "disabled"; 515 }; 516 517 usb2otg: usb@5100000 { 518 compatible = "allwinner,sun50i-h6-musb", 519 "allwinner,sun8i-a33-musb"; 520 reg = <0x05100000 0x0400>; 521 clocks = <&ccu CLK_BUS_OTG>; 522 resets = <&ccu RST_BUS_OTG>; 523 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 524 interrupt-names = "mc"; 525 phys = <&usb2phy 0>; 526 phy-names = "usb"; 527 extcon = <&usb2phy 0>; 528 status = "disabled"; 529 }; 530 531 usb2phy: phy@5100400 { 532 compatible = "allwinner,sun50i-h6-usb-phy"; 533 reg = <0x05100400 0x24>, 534 <0x05101800 0x4>, 535 <0x05311800 0x4>; 536 reg-names = "phy_ctrl", 537 "pmu0", 538 "pmu3"; 539 clocks = <&ccu CLK_USB_PHY0>, 540 <&ccu CLK_USB_PHY3>; 541 clock-names = "usb0_phy", 542 "usb3_phy"; 543 resets = <&ccu RST_USB_PHY0>, 544 <&ccu RST_USB_PHY3>; 545 reset-names = "usb0_reset", 546 "usb3_reset"; 547 status = "disabled"; 548 #phy-cells = <1>; 549 }; 550 551 ehci0: usb@5101000 { 552 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 553 reg = <0x05101000 0x100>; 554 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 555 clocks = <&ccu CLK_BUS_OHCI0>, 556 <&ccu CLK_BUS_EHCI0>, 557 <&ccu CLK_USB_OHCI0>; 558 resets = <&ccu RST_BUS_OHCI0>, 559 <&ccu RST_BUS_EHCI0>; 560 status = "disabled"; 561 }; 562 563 ohci0: usb@5101400 { 564 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 565 reg = <0x05101400 0x100>; 566 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 567 clocks = <&ccu CLK_BUS_OHCI0>, 568 <&ccu CLK_USB_OHCI0>; 569 resets = <&ccu RST_BUS_OHCI0>; 570 status = "disabled"; 571 }; 572 573 dwc3: dwc3@5200000 { 574 compatible = "snps,dwc3"; 575 reg = <0x05200000 0x10000>; 576 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&ccu CLK_BUS_XHCI>, 578 <&ccu CLK_BUS_XHCI>, 579 <&rtc 0>; 580 clock-names = "ref", "bus_early", "suspend"; 581 resets = <&ccu RST_BUS_XHCI>; 582 /* 583 * The datasheet of the chip doesn't declare the 584 * peripheral function, and there's no boards known 585 * to have a USB Type-B port routed to the port. 586 * In addition, no one has tested the peripheral 587 * function yet. 588 * So set the dr_mode to "host" in the DTSI file. 589 */ 590 dr_mode = "host"; 591 phys = <&usb3phy>; 592 phy-names = "usb3-phy"; 593 status = "disabled"; 594 }; 595 596 usb3phy: phy@5210000 { 597 compatible = "allwinner,sun50i-h6-usb3-phy"; 598 reg = <0x5210000 0x10000>; 599 clocks = <&ccu CLK_USB_PHY1>; 600 resets = <&ccu RST_USB_PHY1>; 601 #phy-cells = <0>; 602 status = "disabled"; 603 }; 604 605 ehci3: usb@5311000 { 606 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 607 reg = <0x05311000 0x100>; 608 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&ccu CLK_BUS_OHCI3>, 610 <&ccu CLK_BUS_EHCI3>, 611 <&ccu CLK_USB_OHCI3>; 612 resets = <&ccu RST_BUS_OHCI3>, 613 <&ccu RST_BUS_EHCI3>; 614 phys = <&usb2phy 3>; 615 phy-names = "usb"; 616 status = "disabled"; 617 }; 618 619 ohci3: usb@5311400 { 620 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 621 reg = <0x05311400 0x100>; 622 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&ccu CLK_BUS_OHCI3>, 624 <&ccu CLK_USB_OHCI3>; 625 resets = <&ccu RST_BUS_OHCI3>; 626 phys = <&usb2phy 3>; 627 phy-names = "usb"; 628 status = "disabled"; 629 }; 630 631 hdmi: hdmi@6000000 { 632 compatible = "allwinner,sun50i-h6-dw-hdmi"; 633 reg = <0x06000000 0x10000>; 634 reg-io-width = <1>; 635 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 636 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 637 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 638 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 639 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 640 "hdcp-bus"; 641 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 642 reset-names = "ctrl", "hdcp"; 643 phys = <&hdmi_phy>; 644 phy-names = "phy"; 645 pinctrl-names = "default"; 646 pinctrl-0 = <&hdmi_pins>; 647 status = "disabled"; 648 649 ports { 650 #address-cells = <1>; 651 #size-cells = <0>; 652 653 hdmi_in: port@0 { 654 reg = <0>; 655 656 hdmi_in_tcon_top: endpoint { 657 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 658 }; 659 }; 660 661 hdmi_out: port@1 { 662 reg = <1>; 663 }; 664 }; 665 }; 666 667 hdmi_phy: hdmi-phy@6010000 { 668 compatible = "allwinner,sun50i-h6-hdmi-phy"; 669 reg = <0x06010000 0x10000>; 670 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 671 clock-names = "bus", "mod"; 672 resets = <&ccu RST_BUS_HDMI>; 673 reset-names = "phy"; 674 #phy-cells = <0>; 675 }; 676 677 tcon_top: tcon-top@6510000 { 678 compatible = "allwinner,sun50i-h6-tcon-top"; 679 reg = <0x06510000 0x1000>; 680 clocks = <&ccu CLK_BUS_TCON_TOP>, 681 <&ccu CLK_TCON_TV0>; 682 clock-names = "bus", 683 "tcon-tv0"; 684 clock-output-names = "tcon-top-tv0"; 685 resets = <&ccu RST_BUS_TCON_TOP>; 686 #clock-cells = <1>; 687 688 ports { 689 #address-cells = <1>; 690 #size-cells = <0>; 691 692 tcon_top_mixer0_in: port@0 { 693 #address-cells = <1>; 694 #size-cells = <0>; 695 reg = <0>; 696 697 tcon_top_mixer0_in_mixer0: endpoint@0 { 698 reg = <0>; 699 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 700 }; 701 }; 702 703 tcon_top_mixer0_out: port@1 { 704 #address-cells = <1>; 705 #size-cells = <0>; 706 reg = <1>; 707 708 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 709 reg = <2>; 710 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 711 }; 712 }; 713 714 tcon_top_hdmi_in: port@4 { 715 #address-cells = <1>; 716 #size-cells = <0>; 717 reg = <4>; 718 719 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 720 reg = <0>; 721 remote-endpoint = <&tcon_tv_out_tcon_top>; 722 }; 723 }; 724 725 tcon_top_hdmi_out: port@5 { 726 reg = <5>; 727 728 tcon_top_hdmi_out_hdmi: endpoint { 729 remote-endpoint = <&hdmi_in_tcon_top>; 730 }; 731 }; 732 }; 733 }; 734 735 tcon_tv: lcd-controller@6515000 { 736 compatible = "allwinner,sun50i-h6-tcon-tv", 737 "allwinner,sun8i-r40-tcon-tv"; 738 reg = <0x06515000 0x1000>; 739 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&ccu CLK_BUS_TCON_TV0>, 741 <&tcon_top CLK_TCON_TOP_TV0>; 742 clock-names = "ahb", 743 "tcon-ch1"; 744 resets = <&ccu RST_BUS_TCON_TV0>; 745 reset-names = "lcd"; 746 747 ports { 748 #address-cells = <1>; 749 #size-cells = <0>; 750 751 tcon_tv_in: port@0 { 752 reg = <0>; 753 754 tcon_tv_in_tcon_top_mixer0: endpoint { 755 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 756 }; 757 }; 758 759 tcon_tv_out: port@1 { 760 #address-cells = <1>; 761 #size-cells = <0>; 762 reg = <1>; 763 764 tcon_tv_out_tcon_top: endpoint@1 { 765 reg = <1>; 766 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 767 }; 768 }; 769 }; 770 }; 771 772 rtc: rtc@7000000 { 773 compatible = "allwinner,sun50i-h6-rtc"; 774 reg = <0x07000000 0x400>; 775 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 777 clock-output-names = "osc32k", "osc32k-out", "iosc"; 778 clocks = <&ext_osc32k>; 779 #clock-cells = <1>; 780 }; 781 782 r_ccu: clock@7010000 { 783 compatible = "allwinner,sun50i-h6-r-ccu"; 784 reg = <0x07010000 0x400>; 785 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 786 <&ccu CLK_PLL_PERIPH0>; 787 clock-names = "hosc", "losc", "iosc", "pll-periph"; 788 #clock-cells = <1>; 789 #reset-cells = <1>; 790 }; 791 792 r_watchdog: watchdog@7020400 { 793 compatible = "allwinner,sun50i-h6-wdt", 794 "allwinner,sun6i-a31-wdt"; 795 reg = <0x07020400 0x20>; 796 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&osc24M>; 798 }; 799 800 r_intc: interrupt-controller@7021000 { 801 compatible = "allwinner,sun50i-h6-r-intc", 802 "allwinner,sun6i-a31-r-intc"; 803 interrupt-controller; 804 #interrupt-cells = <2>; 805 reg = <0x07021000 0x400>; 806 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 807 }; 808 809 r_pio: pinctrl@7022000 { 810 compatible = "allwinner,sun50i-h6-r-pinctrl"; 811 reg = <0x07022000 0x400>; 812 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 814 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; 815 clock-names = "apb", "hosc", "losc"; 816 gpio-controller; 817 #gpio-cells = <3>; 818 interrupt-controller; 819 #interrupt-cells = <3>; 820 821 r_i2c_pins: r-i2c-pins { 822 pins = "PL0", "PL1"; 823 function = "s_i2c"; 824 }; 825 826 r_ir_rx_pin: r-ir-rx-pin { 827 pins = "PL9"; 828 function = "s_cir_rx"; 829 }; 830 }; 831 832 r_ir: ir@7040000 { 833 compatible = "allwinner,sun50i-h6-ir", 834 "allwinner,sun6i-a31-ir"; 835 reg = <0x07040000 0x400>; 836 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&r_ccu CLK_R_APB1_IR>, 838 <&r_ccu CLK_IR>; 839 clock-names = "apb", "ir"; 840 resets = <&r_ccu RST_R_APB1_IR>; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&r_ir_rx_pin>; 843 status = "disabled"; 844 }; 845 846 r_i2c: i2c@7081400 { 847 compatible = "allwinner,sun50i-h6-i2c", 848 "allwinner,sun6i-a31-i2c"; 849 reg = <0x07081400 0x400>; 850 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&r_ccu CLK_R_APB2_I2C>; 852 resets = <&r_ccu RST_R_APB2_I2C>; 853 pinctrl-names = "default"; 854 pinctrl-0 = <&r_i2c_pins>; 855 status = "disabled"; 856 #address-cells = <1>; 857 #size-cells = <0>; 858 }; 859 }; 860}; 861