1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun50i-h6-ccu.h> 6#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-tcon-top.h> 9#include <dt-bindings/reset/sun50i-h6-ccu.h> 10#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 }; 29 30 cpu1: cpu@1 { 31 compatible = "arm,cortex-a53"; 32 device_type = "cpu"; 33 reg = <1>; 34 enable-method = "psci"; 35 }; 36 37 cpu2: cpu@2 { 38 compatible = "arm,cortex-a53"; 39 device_type = "cpu"; 40 reg = <2>; 41 enable-method = "psci"; 42 }; 43 44 cpu3: cpu@3 { 45 compatible = "arm,cortex-a53"; 46 device_type = "cpu"; 47 reg = <3>; 48 enable-method = "psci"; 49 }; 50 }; 51 52 de: display-engine { 53 compatible = "allwinner,sun50i-h6-display-engine"; 54 allwinner,pipelines = <&mixer0>; 55 status = "disabled"; 56 }; 57 58 osc24M: osc24M_clk { 59 #clock-cells = <0>; 60 compatible = "fixed-clock"; 61 clock-frequency = <24000000>; 62 clock-output-names = "osc24M"; 63 }; 64 65 pmu { 66 compatible = "arm,cortex-a53-pmu"; 67 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 70 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 71 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 72 }; 73 74 psci { 75 compatible = "arm,psci-0.2"; 76 method = "smc"; 77 }; 78 79 timer { 80 compatible = "arm,armv8-timer"; 81 interrupts = <GIC_PPI 13 82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 83 <GIC_PPI 14 84 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 85 <GIC_PPI 11 86 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 87 <GIC_PPI 10 88 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 89 }; 90 91 soc { 92 compatible = "simple-bus"; 93 #address-cells = <1>; 94 #size-cells = <1>; 95 ranges; 96 97 bus@1000000 { 98 compatible = "allwinner,sun50i-h6-de3", 99 "allwinner,sun50i-a64-de2"; 100 reg = <0x1000000 0x400000>; 101 allwinner,sram = <&de2_sram 1>; 102 #address-cells = <1>; 103 #size-cells = <1>; 104 ranges = <0 0x1000000 0x400000>; 105 106 display_clocks: clock@0 { 107 compatible = "allwinner,sun50i-h6-de3-clk"; 108 reg = <0x0 0x10000>; 109 clocks = <&ccu CLK_DE>, 110 <&ccu CLK_BUS_DE>; 111 clock-names = "mod", 112 "bus"; 113 resets = <&ccu RST_BUS_DE>; 114 #clock-cells = <1>; 115 #reset-cells = <1>; 116 }; 117 118 mixer0: mixer@100000 { 119 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 120 reg = <0x100000 0x100000>; 121 clocks = <&display_clocks CLK_BUS_MIXER0>, 122 <&display_clocks CLK_MIXER0>; 123 clock-names = "bus", 124 "mod"; 125 resets = <&display_clocks RST_MIXER0>; 126 127 ports { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 mixer0_out: port@1 { 132 reg = <1>; 133 134 mixer0_out_tcon_top_mixer0: endpoint { 135 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 136 }; 137 }; 138 }; 139 }; 140 }; 141 142 video-codec@1c0e000 { 143 compatible = "allwinner,sun50i-h6-video-engine"; 144 reg = <0x01c0e000 0x2000>; 145 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 146 <&ccu CLK_MBUS_VE>; 147 clock-names = "ahb", "mod", "ram"; 148 resets = <&ccu RST_BUS_VE>; 149 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 150 allwinner,sram = <&ve_sram 1>; 151 }; 152 153 gpu: gpu@1800000 { 154 compatible = "allwinner,sun50i-h6-mali", 155 "arm,mali-t720"; 156 reg = <0x01800000 0x4000>; 157 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-names = "job", "mmu", "gpu"; 161 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 162 clock-names = "core", "bus"; 163 resets = <&ccu RST_BUS_GPU>; 164 status = "disabled"; 165 }; 166 167 crypto: crypto@1904000 { 168 compatible = "allwinner,sun50i-h6-crypto"; 169 reg = <0x01904000 0x1000>; 170 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 171 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; 172 clock-names = "bus", "mod", "ram"; 173 resets = <&ccu RST_BUS_CE>; 174 }; 175 176 syscon: syscon@3000000 { 177 compatible = "allwinner,sun50i-h6-system-control", 178 "allwinner,sun50i-a64-system-control"; 179 reg = <0x03000000 0x1000>; 180 #address-cells = <1>; 181 #size-cells = <1>; 182 ranges; 183 184 sram_c: sram@28000 { 185 compatible = "mmio-sram"; 186 reg = <0x00028000 0x1e000>; 187 #address-cells = <1>; 188 #size-cells = <1>; 189 ranges = <0 0x00028000 0x1e000>; 190 191 de2_sram: sram-section@0 { 192 compatible = "allwinner,sun50i-h6-sram-c", 193 "allwinner,sun50i-a64-sram-c"; 194 reg = <0x0000 0x1e000>; 195 }; 196 }; 197 198 sram_c1: sram@1a00000 { 199 compatible = "mmio-sram"; 200 reg = <0x01a00000 0x200000>; 201 #address-cells = <1>; 202 #size-cells = <1>; 203 ranges = <0 0x01a00000 0x200000>; 204 205 ve_sram: sram-section@0 { 206 compatible = "allwinner,sun50i-h6-sram-c1", 207 "allwinner,sun4i-a10-sram-c1"; 208 reg = <0x000000 0x200000>; 209 }; 210 }; 211 }; 212 213 ccu: clock@3001000 { 214 compatible = "allwinner,sun50i-h6-ccu"; 215 reg = <0x03001000 0x1000>; 216 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; 217 clock-names = "hosc", "losc", "iosc"; 218 #clock-cells = <1>; 219 #reset-cells = <1>; 220 }; 221 222 dma: dma-controller@3002000 { 223 compatible = "allwinner,sun50i-h6-dma"; 224 reg = <0x03002000 0x1000>; 225 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 227 clock-names = "bus", "mbus"; 228 dma-channels = <16>; 229 dma-requests = <46>; 230 resets = <&ccu RST_BUS_DMA>; 231 #dma-cells = <1>; 232 }; 233 234 sid: efuse@3006000 { 235 compatible = "allwinner,sun50i-h6-sid"; 236 reg = <0x03006000 0x400>; 237 #address-cells = <1>; 238 #size-cells = <1>; 239 240 ths_calibration: thermal-sensor-calibration@14 { 241 reg = <0x14 0x8>; 242 }; 243 }; 244 245 watchdog: watchdog@30090a0 { 246 compatible = "allwinner,sun50i-h6-wdt", 247 "allwinner,sun6i-a31-wdt"; 248 reg = <0x030090a0 0x20>; 249 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 250 clocks = <&osc24M>; 251 /* Broken on some H6 boards */ 252 status = "disabled"; 253 }; 254 255 pwm: pwm@300a000 { 256 compatible = "allwinner,sun50i-h6-pwm"; 257 reg = <0x0300a000 0x400>; 258 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; 259 clock-names = "mod", "bus"; 260 resets = <&ccu RST_BUS_PWM>; 261 #pwm-cells = <3>; 262 status = "disabled"; 263 }; 264 265 pio: pinctrl@300b000 { 266 compatible = "allwinner,sun50i-h6-pinctrl"; 267 reg = <0x0300b000 0x400>; 268 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 272 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; 273 clock-names = "apb", "hosc", "losc"; 274 gpio-controller; 275 #gpio-cells = <3>; 276 interrupt-controller; 277 #interrupt-cells = <3>; 278 279 ext_rgmii_pins: rgmii-pins { 280 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 281 "PD5", "PD7", "PD8", "PD9", "PD10", 282 "PD11", "PD12", "PD13", "PD19", "PD20"; 283 function = "emac"; 284 drive-strength = <40>; 285 }; 286 287 hdmi_pins: hdmi-pins { 288 pins = "PH8", "PH9", "PH10"; 289 function = "hdmi"; 290 }; 291 292 i2c0_pins: i2c0-pins { 293 pins = "PD25", "PD26"; 294 function = "i2c0"; 295 }; 296 297 i2c1_pins: i2c1-pins { 298 pins = "PH5", "PH6"; 299 function = "i2c1"; 300 }; 301 302 i2c2_pins: i2c2-pins { 303 pins = "PD23", "PD24"; 304 function = "i2c2"; 305 }; 306 307 mmc0_pins: mmc0-pins { 308 pins = "PF0", "PF1", "PF2", "PF3", 309 "PF4", "PF5"; 310 function = "mmc0"; 311 drive-strength = <30>; 312 bias-pull-up; 313 }; 314 315 /omit-if-no-ref/ 316 mmc1_pins: mmc1-pins { 317 pins = "PG0", "PG1", "PG2", "PG3", 318 "PG4", "PG5"; 319 function = "mmc1"; 320 drive-strength = <30>; 321 bias-pull-up; 322 }; 323 324 mmc2_pins: mmc2-pins { 325 pins = "PC1", "PC4", "PC5", "PC6", 326 "PC7", "PC8", "PC9", "PC10", 327 "PC11", "PC12", "PC13", "PC14"; 328 function = "mmc2"; 329 drive-strength = <30>; 330 bias-pull-up; 331 }; 332 333 /omit-if-no-ref/ 334 spi0_pins: spi0-pins { 335 pins = "PC0", "PC2", "PC3"; 336 function = "spi0"; 337 }; 338 339 /* pin shared with MMC2-CMD (eMMC) */ 340 /omit-if-no-ref/ 341 spi0_cs_pin: spi0-cs-pin { 342 pins = "PC5"; 343 function = "spi0"; 344 }; 345 346 /omit-if-no-ref/ 347 spi1_pins: spi1-pins { 348 pins = "PH4", "PH5", "PH6"; 349 function = "spi1"; 350 }; 351 352 /omit-if-no-ref/ 353 spi1_cs_pin: spi1-cs-pin { 354 pins = "PH3"; 355 function = "spi1"; 356 }; 357 358 spdif_tx_pin: spdif-tx-pin { 359 pins = "PH7"; 360 function = "spdif"; 361 }; 362 363 uart0_ph_pins: uart0-ph-pins { 364 pins = "PH0", "PH1"; 365 function = "uart0"; 366 }; 367 368 uart1_pins: uart1-pins { 369 pins = "PG6", "PG7"; 370 function = "uart1"; 371 }; 372 373 uart1_rts_cts_pins: uart1-rts-cts-pins { 374 pins = "PG8", "PG9"; 375 function = "uart1"; 376 }; 377 }; 378 379 gic: interrupt-controller@3021000 { 380 compatible = "arm,gic-400"; 381 reg = <0x03021000 0x1000>, 382 <0x03022000 0x2000>, 383 <0x03024000 0x2000>, 384 <0x03026000 0x2000>; 385 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 386 interrupt-controller; 387 #interrupt-cells = <3>; 388 }; 389 390 mmc0: mmc@4020000 { 391 compatible = "allwinner,sun50i-h6-mmc", 392 "allwinner,sun50i-a64-mmc"; 393 reg = <0x04020000 0x1000>; 394 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 395 clock-names = "ahb", "mmc"; 396 resets = <&ccu RST_BUS_MMC0>; 397 reset-names = "ahb"; 398 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 399 pinctrl-names = "default"; 400 pinctrl-0 = <&mmc0_pins>; 401 status = "disabled"; 402 #address-cells = <1>; 403 #size-cells = <0>; 404 }; 405 406 mmc1: mmc@4021000 { 407 compatible = "allwinner,sun50i-h6-mmc", 408 "allwinner,sun50i-a64-mmc"; 409 reg = <0x04021000 0x1000>; 410 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 411 clock-names = "ahb", "mmc"; 412 resets = <&ccu RST_BUS_MMC1>; 413 reset-names = "ahb"; 414 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 415 pinctrl-names = "default"; 416 pinctrl-0 = <&mmc1_pins>; 417 status = "disabled"; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 }; 421 422 mmc2: mmc@4022000 { 423 compatible = "allwinner,sun50i-h6-emmc", 424 "allwinner,sun50i-a64-emmc"; 425 reg = <0x04022000 0x1000>; 426 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 427 clock-names = "ahb", "mmc"; 428 resets = <&ccu RST_BUS_MMC2>; 429 reset-names = "ahb"; 430 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 431 pinctrl-names = "default"; 432 pinctrl-0 = <&mmc2_pins>; 433 status = "disabled"; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 }; 437 438 uart0: serial@5000000 { 439 compatible = "snps,dw-apb-uart"; 440 reg = <0x05000000 0x400>; 441 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 442 reg-shift = <2>; 443 reg-io-width = <4>; 444 clocks = <&ccu CLK_BUS_UART0>; 445 resets = <&ccu RST_BUS_UART0>; 446 status = "disabled"; 447 }; 448 449 uart1: serial@5000400 { 450 compatible = "snps,dw-apb-uart"; 451 reg = <0x05000400 0x400>; 452 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 453 reg-shift = <2>; 454 reg-io-width = <4>; 455 clocks = <&ccu CLK_BUS_UART1>; 456 resets = <&ccu RST_BUS_UART1>; 457 status = "disabled"; 458 }; 459 460 uart2: serial@5000800 { 461 compatible = "snps,dw-apb-uart"; 462 reg = <0x05000800 0x400>; 463 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 464 reg-shift = <2>; 465 reg-io-width = <4>; 466 clocks = <&ccu CLK_BUS_UART2>; 467 resets = <&ccu RST_BUS_UART2>; 468 status = "disabled"; 469 }; 470 471 uart3: serial@5000c00 { 472 compatible = "snps,dw-apb-uart"; 473 reg = <0x05000c00 0x400>; 474 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 475 reg-shift = <2>; 476 reg-io-width = <4>; 477 clocks = <&ccu CLK_BUS_UART3>; 478 resets = <&ccu RST_BUS_UART3>; 479 status = "disabled"; 480 }; 481 482 i2c0: i2c@5002000 { 483 compatible = "allwinner,sun50i-h6-i2c", 484 "allwinner,sun6i-a31-i2c"; 485 reg = <0x05002000 0x400>; 486 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 487 clocks = <&ccu CLK_BUS_I2C0>; 488 resets = <&ccu RST_BUS_I2C0>; 489 pinctrl-names = "default"; 490 pinctrl-0 = <&i2c0_pins>; 491 status = "disabled"; 492 #address-cells = <1>; 493 #size-cells = <0>; 494 }; 495 496 i2c1: i2c@5002400 { 497 compatible = "allwinner,sun50i-h6-i2c", 498 "allwinner,sun6i-a31-i2c"; 499 reg = <0x05002400 0x400>; 500 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&ccu CLK_BUS_I2C1>; 502 resets = <&ccu RST_BUS_I2C1>; 503 pinctrl-names = "default"; 504 pinctrl-0 = <&i2c1_pins>; 505 status = "disabled"; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 }; 509 510 i2c2: i2c@5002800 { 511 compatible = "allwinner,sun50i-h6-i2c", 512 "allwinner,sun6i-a31-i2c"; 513 reg = <0x05002800 0x400>; 514 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 515 clocks = <&ccu CLK_BUS_I2C2>; 516 resets = <&ccu RST_BUS_I2C2>; 517 pinctrl-names = "default"; 518 pinctrl-0 = <&i2c2_pins>; 519 status = "disabled"; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 }; 523 524 spi0: spi@5010000 { 525 compatible = "allwinner,sun50i-h6-spi", 526 "allwinner,sun8i-h3-spi"; 527 reg = <0x05010000 0x1000>; 528 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 530 clock-names = "ahb", "mod"; 531 dmas = <&dma 22>, <&dma 22>; 532 dma-names = "rx", "tx"; 533 resets = <&ccu RST_BUS_SPI0>; 534 status = "disabled"; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 }; 538 539 spi1: spi@5011000 { 540 compatible = "allwinner,sun50i-h6-spi", 541 "allwinner,sun8i-h3-spi"; 542 reg = <0x05011000 0x1000>; 543 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 545 clock-names = "ahb", "mod"; 546 dmas = <&dma 23>, <&dma 23>; 547 dma-names = "rx", "tx"; 548 resets = <&ccu RST_BUS_SPI1>; 549 status = "disabled"; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 }; 553 554 emac: ethernet@5020000 { 555 compatible = "allwinner,sun50i-h6-emac", 556 "allwinner,sun50i-a64-emac"; 557 syscon = <&syscon>; 558 reg = <0x05020000 0x10000>; 559 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 560 interrupt-names = "macirq"; 561 resets = <&ccu RST_BUS_EMAC>; 562 reset-names = "stmmaceth"; 563 clocks = <&ccu CLK_BUS_EMAC>; 564 clock-names = "stmmaceth"; 565 status = "disabled"; 566 567 mdio: mdio { 568 compatible = "snps,dwmac-mdio"; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 }; 572 }; 573 574 spdif: spdif@5093000 { 575 #sound-dai-cells = <0>; 576 compatible = "allwinner,sun50i-h6-spdif"; 577 reg = <0x05093000 0x400>; 578 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 579 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 580 clock-names = "apb", "spdif"; 581 resets = <&ccu RST_BUS_SPDIF>; 582 dmas = <&dma 2>; 583 dma-names = "tx"; 584 pinctrl-names = "default"; 585 pinctrl-0 = <&spdif_tx_pin>; 586 status = "disabled"; 587 }; 588 589 usb2otg: usb@5100000 { 590 compatible = "allwinner,sun50i-h6-musb", 591 "allwinner,sun8i-a33-musb"; 592 reg = <0x05100000 0x0400>; 593 clocks = <&ccu CLK_BUS_OTG>; 594 resets = <&ccu RST_BUS_OTG>; 595 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 596 interrupt-names = "mc"; 597 phys = <&usb2phy 0>; 598 phy-names = "usb"; 599 extcon = <&usb2phy 0>; 600 status = "disabled"; 601 }; 602 603 usb2phy: phy@5100400 { 604 compatible = "allwinner,sun50i-h6-usb-phy"; 605 reg = <0x05100400 0x24>, 606 <0x05101800 0x4>, 607 <0x05311800 0x4>; 608 reg-names = "phy_ctrl", 609 "pmu0", 610 "pmu3"; 611 clocks = <&ccu CLK_USB_PHY0>, 612 <&ccu CLK_USB_PHY3>; 613 clock-names = "usb0_phy", 614 "usb3_phy"; 615 resets = <&ccu RST_USB_PHY0>, 616 <&ccu RST_USB_PHY3>; 617 reset-names = "usb0_reset", 618 "usb3_reset"; 619 status = "disabled"; 620 #phy-cells = <1>; 621 }; 622 623 ehci0: usb@5101000 { 624 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 625 reg = <0x05101000 0x100>; 626 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&ccu CLK_BUS_OHCI0>, 628 <&ccu CLK_BUS_EHCI0>, 629 <&ccu CLK_USB_OHCI0>; 630 resets = <&ccu RST_BUS_OHCI0>, 631 <&ccu RST_BUS_EHCI0>; 632 status = "disabled"; 633 }; 634 635 ohci0: usb@5101400 { 636 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 637 reg = <0x05101400 0x100>; 638 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 639 clocks = <&ccu CLK_BUS_OHCI0>, 640 <&ccu CLK_USB_OHCI0>; 641 resets = <&ccu RST_BUS_OHCI0>; 642 status = "disabled"; 643 }; 644 645 dwc3: dwc3@5200000 { 646 compatible = "snps,dwc3"; 647 reg = <0x05200000 0x10000>; 648 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 649 clocks = <&ccu CLK_BUS_XHCI>, 650 <&ccu CLK_BUS_XHCI>, 651 <&rtc 0>; 652 clock-names = "ref", "bus_early", "suspend"; 653 resets = <&ccu RST_BUS_XHCI>; 654 /* 655 * The datasheet of the chip doesn't declare the 656 * peripheral function, and there's no boards known 657 * to have a USB Type-B port routed to the port. 658 * In addition, no one has tested the peripheral 659 * function yet. 660 * So set the dr_mode to "host" in the DTSI file. 661 */ 662 dr_mode = "host"; 663 phys = <&usb3phy>; 664 phy-names = "usb3-phy"; 665 status = "disabled"; 666 }; 667 668 usb3phy: phy@5210000 { 669 compatible = "allwinner,sun50i-h6-usb3-phy"; 670 reg = <0x5210000 0x10000>; 671 clocks = <&ccu CLK_USB_PHY1>; 672 resets = <&ccu RST_USB_PHY1>; 673 #phy-cells = <0>; 674 status = "disabled"; 675 }; 676 677 ehci3: usb@5311000 { 678 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 679 reg = <0x05311000 0x100>; 680 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&ccu CLK_BUS_OHCI3>, 682 <&ccu CLK_BUS_EHCI3>, 683 <&ccu CLK_USB_OHCI3>; 684 resets = <&ccu RST_BUS_OHCI3>, 685 <&ccu RST_BUS_EHCI3>; 686 phys = <&usb2phy 3>; 687 phy-names = "usb"; 688 status = "disabled"; 689 }; 690 691 ohci3: usb@5311400 { 692 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 693 reg = <0x05311400 0x100>; 694 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&ccu CLK_BUS_OHCI3>, 696 <&ccu CLK_USB_OHCI3>; 697 resets = <&ccu RST_BUS_OHCI3>; 698 phys = <&usb2phy 3>; 699 phy-names = "usb"; 700 status = "disabled"; 701 }; 702 703 hdmi: hdmi@6000000 { 704 compatible = "allwinner,sun50i-h6-dw-hdmi"; 705 reg = <0x06000000 0x10000>; 706 reg-io-width = <1>; 707 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 709 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 710 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 711 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 712 "hdcp-bus"; 713 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 714 reset-names = "ctrl", "hdcp"; 715 phys = <&hdmi_phy>; 716 phy-names = "phy"; 717 pinctrl-names = "default"; 718 pinctrl-0 = <&hdmi_pins>; 719 status = "disabled"; 720 721 ports { 722 #address-cells = <1>; 723 #size-cells = <0>; 724 725 hdmi_in: port@0 { 726 reg = <0>; 727 728 hdmi_in_tcon_top: endpoint { 729 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 730 }; 731 }; 732 733 hdmi_out: port@1 { 734 reg = <1>; 735 }; 736 }; 737 }; 738 739 hdmi_phy: hdmi-phy@6010000 { 740 compatible = "allwinner,sun50i-h6-hdmi-phy"; 741 reg = <0x06010000 0x10000>; 742 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 743 clock-names = "bus", "mod"; 744 resets = <&ccu RST_BUS_HDMI>; 745 reset-names = "phy"; 746 #phy-cells = <0>; 747 }; 748 749 tcon_top: tcon-top@6510000 { 750 compatible = "allwinner,sun50i-h6-tcon-top"; 751 reg = <0x06510000 0x1000>; 752 clocks = <&ccu CLK_BUS_TCON_TOP>, 753 <&ccu CLK_TCON_TV0>; 754 clock-names = "bus", 755 "tcon-tv0"; 756 clock-output-names = "tcon-top-tv0"; 757 resets = <&ccu RST_BUS_TCON_TOP>; 758 #clock-cells = <1>; 759 760 ports { 761 #address-cells = <1>; 762 #size-cells = <0>; 763 764 tcon_top_mixer0_in: port@0 { 765 #address-cells = <1>; 766 #size-cells = <0>; 767 reg = <0>; 768 769 tcon_top_mixer0_in_mixer0: endpoint@0 { 770 reg = <0>; 771 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 772 }; 773 }; 774 775 tcon_top_mixer0_out: port@1 { 776 #address-cells = <1>; 777 #size-cells = <0>; 778 reg = <1>; 779 780 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 781 reg = <2>; 782 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 783 }; 784 }; 785 786 tcon_top_hdmi_in: port@4 { 787 #address-cells = <1>; 788 #size-cells = <0>; 789 reg = <4>; 790 791 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 792 reg = <0>; 793 remote-endpoint = <&tcon_tv_out_tcon_top>; 794 }; 795 }; 796 797 tcon_top_hdmi_out: port@5 { 798 reg = <5>; 799 800 tcon_top_hdmi_out_hdmi: endpoint { 801 remote-endpoint = <&hdmi_in_tcon_top>; 802 }; 803 }; 804 }; 805 }; 806 807 tcon_tv: lcd-controller@6515000 { 808 compatible = "allwinner,sun50i-h6-tcon-tv", 809 "allwinner,sun8i-r40-tcon-tv"; 810 reg = <0x06515000 0x1000>; 811 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 812 clocks = <&ccu CLK_BUS_TCON_TV0>, 813 <&tcon_top CLK_TCON_TOP_TV0>; 814 clock-names = "ahb", 815 "tcon-ch1"; 816 resets = <&ccu RST_BUS_TCON_TV0>; 817 reset-names = "lcd"; 818 819 ports { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 823 tcon_tv_in: port@0 { 824 reg = <0>; 825 826 tcon_tv_in_tcon_top_mixer0: endpoint { 827 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 828 }; 829 }; 830 831 tcon_tv_out: port@1 { 832 #address-cells = <1>; 833 #size-cells = <0>; 834 reg = <1>; 835 836 tcon_tv_out_tcon_top: endpoint@1 { 837 reg = <1>; 838 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 839 }; 840 }; 841 }; 842 }; 843 844 rtc: rtc@7000000 { 845 compatible = "allwinner,sun50i-h6-rtc"; 846 reg = <0x07000000 0x400>; 847 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 849 clock-output-names = "osc32k", "osc32k-out", "iosc"; 850 #clock-cells = <1>; 851 }; 852 853 r_ccu: clock@7010000 { 854 compatible = "allwinner,sun50i-h6-r-ccu"; 855 reg = <0x07010000 0x400>; 856 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 857 <&ccu CLK_PLL_PERIPH0>; 858 clock-names = "hosc", "losc", "iosc", "pll-periph"; 859 #clock-cells = <1>; 860 #reset-cells = <1>; 861 }; 862 863 r_watchdog: watchdog@7020400 { 864 compatible = "allwinner,sun50i-h6-wdt", 865 "allwinner,sun6i-a31-wdt"; 866 reg = <0x07020400 0x20>; 867 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 868 clocks = <&osc24M>; 869 }; 870 871 r_intc: interrupt-controller@7021000 { 872 compatible = "allwinner,sun50i-h6-r-intc", 873 "allwinner,sun6i-a31-r-intc"; 874 interrupt-controller; 875 #interrupt-cells = <2>; 876 reg = <0x07021000 0x400>; 877 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 878 }; 879 880 r_pio: pinctrl@7022000 { 881 compatible = "allwinner,sun50i-h6-r-pinctrl"; 882 reg = <0x07022000 0x400>; 883 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; 886 clock-names = "apb", "hosc", "losc"; 887 gpio-controller; 888 #gpio-cells = <3>; 889 interrupt-controller; 890 #interrupt-cells = <3>; 891 892 r_i2c_pins: r-i2c-pins { 893 pins = "PL0", "PL1"; 894 function = "s_i2c"; 895 }; 896 897 r_ir_rx_pin: r-ir-rx-pin { 898 pins = "PL9"; 899 function = "s_cir_rx"; 900 }; 901 }; 902 903 r_ir: ir@7040000 { 904 compatible = "allwinner,sun50i-h6-ir", 905 "allwinner,sun6i-a31-ir"; 906 reg = <0x07040000 0x400>; 907 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 908 clocks = <&r_ccu CLK_R_APB1_IR>, 909 <&r_ccu CLK_IR>; 910 clock-names = "apb", "ir"; 911 resets = <&r_ccu RST_R_APB1_IR>; 912 pinctrl-names = "default"; 913 pinctrl-0 = <&r_ir_rx_pin>; 914 status = "disabled"; 915 }; 916 917 r_i2c: i2c@7081400 { 918 compatible = "allwinner,sun50i-h6-i2c", 919 "allwinner,sun6i-a31-i2c"; 920 reg = <0x07081400 0x400>; 921 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&r_ccu CLK_R_APB2_I2C>; 923 resets = <&r_ccu RST_R_APB2_I2C>; 924 pinctrl-names = "default"; 925 pinctrl-0 = <&r_i2c_pins>; 926 status = "disabled"; 927 #address-cells = <1>; 928 #size-cells = <0>; 929 }; 930 931 ths: thermal-sensor@5070400 { 932 compatible = "allwinner,sun50i-h6-ths"; 933 reg = <0x05070400 0x100>; 934 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&ccu CLK_BUS_THS>; 936 clock-names = "bus"; 937 resets = <&ccu RST_BUS_THS>; 938 nvmem-cells = <&ths_calibration>; 939 nvmem-cell-names = "calibration"; 940 #thermal-sensor-cells = <1>; 941 }; 942 }; 943 944 thermal-zones { 945 cpu-thermal { 946 polling-delay-passive = <0>; 947 polling-delay = <0>; 948 thermal-sensors = <&ths 0>; 949 }; 950 951 gpu-thermal { 952 polling-delay-passive = <0>; 953 polling-delay = <0>; 954 thermal-sensors = <&ths 1>; 955 }; 956 }; 957}; 958