1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2/* 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-h6-ccu.h> 8#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9#include <dt-bindings/clock/sun8i-de2.h> 10#include <dt-bindings/clock/sun8i-tcon-top.h> 11#include <dt-bindings/reset/sun50i-h6-ccu.h> 12#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 13#include <dt-bindings/reset/sun8i-de2.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a53", "arm,armv8"; 26 device_type = "cpu"; 27 reg = <0>; 28 enable-method = "psci"; 29 }; 30 31 cpu1: cpu@1 { 32 compatible = "arm,cortex-a53", "arm,armv8"; 33 device_type = "cpu"; 34 reg = <1>; 35 enable-method = "psci"; 36 }; 37 38 cpu2: cpu@2 { 39 compatible = "arm,cortex-a53", "arm,armv8"; 40 device_type = "cpu"; 41 reg = <2>; 42 enable-method = "psci"; 43 }; 44 45 cpu3: cpu@3 { 46 compatible = "arm,cortex-a53", "arm,armv8"; 47 device_type = "cpu"; 48 reg = <3>; 49 enable-method = "psci"; 50 }; 51 }; 52 53 de: display-engine { 54 compatible = "allwinner,sun50i-h6-display-engine"; 55 allwinner,pipelines = <&mixer0>; 56 status = "disabled"; 57 }; 58 59 iosc: internal-osc-clk { 60 #clock-cells = <0>; 61 compatible = "fixed-clock"; 62 clock-frequency = <16000000>; 63 clock-accuracy = <300000000>; 64 clock-output-names = "iosc"; 65 }; 66 67 osc24M: osc24M_clk { 68 #clock-cells = <0>; 69 compatible = "fixed-clock"; 70 clock-frequency = <24000000>; 71 clock-output-names = "osc24M"; 72 }; 73 74 osc32k: osc32k_clk { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <32768>; 78 clock-output-names = "osc32k"; 79 }; 80 81 psci { 82 compatible = "arm,psci-0.2"; 83 method = "smc"; 84 }; 85 86 timer { 87 compatible = "arm,armv8-timer"; 88 interrupts = <GIC_PPI 13 89 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 90 <GIC_PPI 14 91 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 92 <GIC_PPI 11 93 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 94 <GIC_PPI 10 95 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 96 }; 97 98 soc { 99 compatible = "simple-bus"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges; 103 104 display-engine@1000000 { 105 compatible = "allwinner,sun50i-h6-de3", 106 "allwinner,sun50i-a64-de2"; 107 reg = <0x1000000 0x400000>; 108 allwinner,sram = <&de2_sram 1>; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0 0x1000000 0x400000>; 112 113 display_clocks: clock@0 { 114 compatible = "allwinner,sun50i-h6-de3-clk"; 115 reg = <0x0 0x10000>; 116 clocks = <&ccu CLK_DE>, 117 <&ccu CLK_BUS_DE>; 118 clock-names = "mod", 119 "bus"; 120 resets = <&ccu RST_BUS_DE>; 121 #clock-cells = <1>; 122 #reset-cells = <1>; 123 }; 124 125 mixer0: mixer@100000 { 126 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 127 reg = <0x100000 0x100000>; 128 clocks = <&display_clocks CLK_BUS_MIXER0>, 129 <&display_clocks CLK_MIXER0>; 130 clock-names = "bus", 131 "mod"; 132 resets = <&display_clocks RST_MIXER0>; 133 134 ports { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 mixer0_out: port@1 { 139 reg = <1>; 140 141 mixer0_out_tcon_top_mixer0: endpoint { 142 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 143 }; 144 }; 145 }; 146 }; 147 }; 148 149 syscon: syscon@3000000 { 150 compatible = "allwinner,sun50i-h6-system-control", 151 "allwinner,sun50i-a64-system-control"; 152 reg = <0x03000000 0x1000>; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges; 156 157 sram_c: sram@28000 { 158 compatible = "mmio-sram"; 159 reg = <0x00028000 0x1e000>; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 ranges = <0 0x00028000 0x1e000>; 163 164 de2_sram: sram-section@0 { 165 compatible = "allwinner,sun50i-h6-sram-c", 166 "allwinner,sun50i-a64-sram-c"; 167 reg = <0x0000 0x1e000>; 168 }; 169 }; 170 }; 171 172 ccu: clock@3001000 { 173 compatible = "allwinner,sun50i-h6-ccu"; 174 reg = <0x03001000 0x1000>; 175 clocks = <&osc24M>, <&osc32k>, <&iosc>; 176 clock-names = "hosc", "losc", "iosc"; 177 #clock-cells = <1>; 178 #reset-cells = <1>; 179 }; 180 181 gic: interrupt-controller@3021000 { 182 compatible = "arm,gic-400"; 183 reg = <0x03021000 0x1000>, 184 <0x03022000 0x2000>, 185 <0x03024000 0x2000>, 186 <0x03026000 0x2000>; 187 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 188 interrupt-controller; 189 #interrupt-cells = <3>; 190 }; 191 192 pio: pinctrl@300b000 { 193 compatible = "allwinner,sun50i-h6-pinctrl"; 194 reg = <0x0300b000 0x400>; 195 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; 200 clock-names = "apb", "hosc", "losc"; 201 gpio-controller; 202 #gpio-cells = <3>; 203 interrupt-controller; 204 #interrupt-cells = <3>; 205 206 ext_rgmii_pins: rgmii_pins { 207 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 208 "PD5", "PD7", "PD8", "PD9", "PD10", 209 "PD11", "PD12", "PD13", "PD19", "PD20"; 210 function = "emac"; 211 drive-strength = <40>; 212 }; 213 214 hdmi_pins: hdmi-pins { 215 pins = "PH8", "PH9", "PH10"; 216 function = "hdmi"; 217 }; 218 219 mmc0_pins: mmc0-pins { 220 pins = "PF0", "PF1", "PF2", "PF3", 221 "PF4", "PF5"; 222 function = "mmc0"; 223 drive-strength = <30>; 224 bias-pull-up; 225 }; 226 227 mmc2_pins: mmc2-pins { 228 pins = "PC1", "PC4", "PC5", "PC6", 229 "PC7", "PC8", "PC9", "PC10", 230 "PC11", "PC12", "PC13", "PC14"; 231 function = "mmc2"; 232 drive-strength = <30>; 233 bias-pull-up; 234 }; 235 236 uart0_ph_pins: uart0-ph { 237 pins = "PH0", "PH1"; 238 function = "uart0"; 239 }; 240 }; 241 242 mmc0: mmc@4020000 { 243 compatible = "allwinner,sun50i-h6-mmc", 244 "allwinner,sun50i-a64-mmc"; 245 reg = <0x04020000 0x1000>; 246 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 247 clock-names = "ahb", "mmc"; 248 resets = <&ccu RST_BUS_MMC0>; 249 reset-names = "ahb"; 250 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 251 status = "disabled"; 252 #address-cells = <1>; 253 #size-cells = <0>; 254 }; 255 256 mmc1: mmc@4021000 { 257 compatible = "allwinner,sun50i-h6-mmc", 258 "allwinner,sun50i-a64-mmc"; 259 reg = <0x04021000 0x1000>; 260 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 261 clock-names = "ahb", "mmc"; 262 resets = <&ccu RST_BUS_MMC1>; 263 reset-names = "ahb"; 264 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 265 status = "disabled"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 }; 269 270 mmc2: mmc@4022000 { 271 compatible = "allwinner,sun50i-h6-emmc", 272 "allwinner,sun50i-a64-emmc"; 273 reg = <0x04022000 0x1000>; 274 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 275 clock-names = "ahb", "mmc"; 276 resets = <&ccu RST_BUS_MMC2>; 277 reset-names = "ahb"; 278 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 279 status = "disabled"; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 }; 283 284 uart0: serial@5000000 { 285 compatible = "snps,dw-apb-uart"; 286 reg = <0x05000000 0x400>; 287 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 288 reg-shift = <2>; 289 reg-io-width = <4>; 290 clocks = <&ccu CLK_BUS_UART0>; 291 resets = <&ccu RST_BUS_UART0>; 292 status = "disabled"; 293 }; 294 295 uart1: serial@5000400 { 296 compatible = "snps,dw-apb-uart"; 297 reg = <0x05000400 0x400>; 298 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 299 reg-shift = <2>; 300 reg-io-width = <4>; 301 clocks = <&ccu CLK_BUS_UART1>; 302 resets = <&ccu RST_BUS_UART1>; 303 status = "disabled"; 304 }; 305 306 uart2: serial@5000800 { 307 compatible = "snps,dw-apb-uart"; 308 reg = <0x05000800 0x400>; 309 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 310 reg-shift = <2>; 311 reg-io-width = <4>; 312 clocks = <&ccu CLK_BUS_UART2>; 313 resets = <&ccu RST_BUS_UART2>; 314 status = "disabled"; 315 }; 316 317 uart3: serial@5000c00 { 318 compatible = "snps,dw-apb-uart"; 319 reg = <0x05000c00 0x400>; 320 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 321 reg-shift = <2>; 322 reg-io-width = <4>; 323 clocks = <&ccu CLK_BUS_UART3>; 324 resets = <&ccu RST_BUS_UART3>; 325 status = "disabled"; 326 }; 327 328 emac: ethernet@5020000 { 329 compatible = "allwinner,sun50i-h6-emac", 330 "allwinner,sun50i-a64-emac"; 331 syscon = <&syscon>; 332 reg = <0x05020000 0x10000>; 333 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 334 interrupt-names = "macirq"; 335 resets = <&ccu RST_BUS_EMAC>; 336 reset-names = "stmmaceth"; 337 clocks = <&ccu CLK_BUS_EMAC>; 338 clock-names = "stmmaceth"; 339 status = "disabled"; 340 341 mdio: mdio { 342 compatible = "snps,dwmac-mdio"; 343 #address-cells = <1>; 344 #size-cells = <0>; 345 }; 346 }; 347 348 usb2otg: usb@5100000 { 349 compatible = "allwinner,sun50i-h6-musb", 350 "allwinner,sun8i-a33-musb"; 351 reg = <0x05100000 0x0400>; 352 clocks = <&ccu CLK_BUS_OTG>; 353 resets = <&ccu RST_BUS_OTG>; 354 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 355 interrupt-names = "mc"; 356 phys = <&usb2phy 0>; 357 phy-names = "usb"; 358 extcon = <&usb2phy 0>; 359 status = "disabled"; 360 }; 361 362 usb2phy: phy@5100400 { 363 compatible = "allwinner,sun50i-h6-usb-phy"; 364 reg = <0x05100400 0x24>, 365 <0x05101800 0x4>, 366 <0x05311800 0x4>; 367 reg-names = "phy_ctrl", 368 "pmu0", 369 "pmu3"; 370 clocks = <&ccu CLK_USB_PHY0>, 371 <&ccu CLK_USB_PHY3>; 372 clock-names = "usb0_phy", 373 "usb3_phy"; 374 resets = <&ccu RST_USB_PHY0>, 375 <&ccu RST_USB_PHY3>; 376 reset-names = "usb0_reset", 377 "usb3_reset"; 378 status = "disabled"; 379 #phy-cells = <1>; 380 }; 381 382 ehci0: usb@5101000 { 383 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 384 reg = <0x05101000 0x100>; 385 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 386 clocks = <&ccu CLK_BUS_OHCI0>, 387 <&ccu CLK_BUS_EHCI0>, 388 <&ccu CLK_USB_OHCI0>; 389 resets = <&ccu RST_BUS_OHCI0>, 390 <&ccu RST_BUS_EHCI0>; 391 status = "disabled"; 392 }; 393 394 ohci0: usb@5101400 { 395 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 396 reg = <0x05101400 0x100>; 397 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 398 clocks = <&ccu CLK_BUS_OHCI0>, 399 <&ccu CLK_USB_OHCI0>; 400 resets = <&ccu RST_BUS_OHCI0>; 401 status = "disabled"; 402 }; 403 404 ehci3: usb@5311000 { 405 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 406 reg = <0x05311000 0x100>; 407 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 408 clocks = <&ccu CLK_BUS_OHCI3>, 409 <&ccu CLK_BUS_EHCI3>, 410 <&ccu CLK_USB_OHCI3>; 411 resets = <&ccu RST_BUS_OHCI3>, 412 <&ccu RST_BUS_EHCI3>; 413 phys = <&usb2phy 3>; 414 phy-names = "usb"; 415 status = "disabled"; 416 }; 417 418 ohci3: usb@5311400 { 419 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 420 reg = <0x05311400 0x100>; 421 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&ccu CLK_BUS_OHCI3>, 423 <&ccu CLK_USB_OHCI3>; 424 resets = <&ccu RST_BUS_OHCI3>; 425 phys = <&usb2phy 3>; 426 phy-names = "usb"; 427 status = "disabled"; 428 }; 429 430 hdmi: hdmi@6000000 { 431 compatible = "allwinner,sun50i-h6-dw-hdmi"; 432 reg = <0x06000000 0x10000>; 433 reg-io-width = <1>; 434 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 436 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 437 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 438 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 439 "hdcp-bus"; 440 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 441 reset-names = "ctrl", "hdcp"; 442 phys = <&hdmi_phy>; 443 phy-names = "hdmi-phy"; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&hdmi_pins>; 446 status = "disabled"; 447 448 ports { 449 #address-cells = <1>; 450 #size-cells = <0>; 451 452 hdmi_in: port@0 { 453 reg = <0>; 454 455 hdmi_in_tcon_top: endpoint { 456 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 457 }; 458 }; 459 460 hdmi_out: port@1 { 461 reg = <1>; 462 }; 463 }; 464 }; 465 466 hdmi_phy: hdmi-phy@6010000 { 467 compatible = "allwinner,sun50i-h6-hdmi-phy"; 468 reg = <0x06010000 0x10000>; 469 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 470 clock-names = "bus", "mod"; 471 resets = <&ccu RST_BUS_HDMI>; 472 reset-names = "phy"; 473 #phy-cells = <0>; 474 }; 475 476 tcon_top: tcon-top@6510000 { 477 compatible = "allwinner,sun50i-h6-tcon-top"; 478 reg = <0x06510000 0x1000>; 479 clocks = <&ccu CLK_BUS_TCON_TOP>, 480 <&ccu CLK_TCON_TV0>; 481 clock-names = "bus", 482 "tcon-tv0"; 483 clock-output-names = "tcon-top-tv0"; 484 resets = <&ccu RST_BUS_TCON_TOP>; 485 reset-names = "rst"; 486 #clock-cells = <1>; 487 488 ports { 489 #address-cells = <1>; 490 #size-cells = <0>; 491 492 tcon_top_mixer0_in: port@0 { 493 #address-cells = <1>; 494 #size-cells = <0>; 495 reg = <0>; 496 497 tcon_top_mixer0_in_mixer0: endpoint@0 { 498 reg = <0>; 499 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 500 }; 501 }; 502 503 tcon_top_mixer0_out: port@1 { 504 #address-cells = <1>; 505 #size-cells = <0>; 506 reg = <1>; 507 508 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 509 reg = <2>; 510 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 511 }; 512 }; 513 514 tcon_top_hdmi_in: port@4 { 515 #address-cells = <1>; 516 #size-cells = <0>; 517 reg = <4>; 518 519 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 520 reg = <0>; 521 remote-endpoint = <&tcon_tv_out_tcon_top>; 522 }; 523 }; 524 525 tcon_top_hdmi_out: port@5 { 526 reg = <5>; 527 528 tcon_top_hdmi_out_hdmi: endpoint { 529 remote-endpoint = <&hdmi_in_tcon_top>; 530 }; 531 }; 532 }; 533 }; 534 535 tcon_tv: lcd-controller@6515000 { 536 compatible = "allwinner,sun50i-h6-tcon-tv", 537 "allwinner,sun8i-r40-tcon-tv"; 538 reg = <0x06515000 0x1000>; 539 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&ccu CLK_BUS_TCON_TV0>, 541 <&tcon_top CLK_TCON_TOP_TV0>; 542 clock-names = "ahb", 543 "tcon-ch1"; 544 resets = <&ccu RST_BUS_TCON_TV0>; 545 reset-names = "lcd"; 546 547 ports { 548 #address-cells = <1>; 549 #size-cells = <0>; 550 551 tcon_tv_in: port@0 { 552 reg = <0>; 553 554 tcon_tv_in_tcon_top_mixer0: endpoint { 555 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 556 }; 557 }; 558 559 tcon_tv_out: port@1 { 560 #address-cells = <1>; 561 #size-cells = <0>; 562 reg = <1>; 563 564 tcon_tv_out_tcon_top: endpoint@1 { 565 reg = <1>; 566 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 567 }; 568 }; 569 }; 570 }; 571 572 r_ccu: clock@7010000 { 573 compatible = "allwinner,sun50i-h6-r-ccu"; 574 reg = <0x07010000 0x400>; 575 clocks = <&osc24M>, <&osc32k>, <&iosc>, 576 <&ccu CLK_PLL_PERIPH0>; 577 clock-names = "hosc", "losc", "iosc", "pll-periph"; 578 #clock-cells = <1>; 579 #reset-cells = <1>; 580 }; 581 582 r_intc: interrupt-controller@7021000 { 583 compatible = "allwinner,sun50i-h6-r-intc", 584 "allwinner,sun6i-a31-r-intc"; 585 interrupt-controller; 586 #interrupt-cells = <2>; 587 reg = <0x07021000 0x400>; 588 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 589 }; 590 591 r_pio: pinctrl@7022000 { 592 compatible = "allwinner,sun50i-h6-r-pinctrl"; 593 reg = <0x07022000 0x400>; 594 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 596 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; 597 clock-names = "apb", "hosc", "losc"; 598 gpio-controller; 599 #gpio-cells = <3>; 600 interrupt-controller; 601 #interrupt-cells = <3>; 602 603 r_i2c_pins: r-i2c { 604 pins = "PL0", "PL1"; 605 function = "s_i2c"; 606 }; 607 }; 608 609 r_i2c: i2c@7081400 { 610 compatible = "allwinner,sun6i-a31-i2c"; 611 reg = <0x07081400 0x400>; 612 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&r_ccu CLK_R_APB2_I2C>; 614 resets = <&r_ccu RST_R_APB2_I2C>; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&r_i2c_pins>; 617 status = "disabled"; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 }; 621 }; 622}; 623