1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun50i-h6-ccu.h> 6#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 7#include <dt-bindings/clock/sun6i-rtc.h> 8#include <dt-bindings/clock/sun8i-de2.h> 9#include <dt-bindings/clock/sun8i-tcon-top.h> 10#include <dt-bindings/reset/sun50i-h6-ccu.h> 11#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 12#include <dt-bindings/reset/sun8i-de2.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a53"; 26 device_type = "cpu"; 27 reg = <0>; 28 enable-method = "psci"; 29 clocks = <&ccu CLK_CPUX>; 30 clock-latency-ns = <244144>; /* 8 32k periods */ 31 #cooling-cells = <2>; 32 }; 33 34 cpu1: cpu@1 { 35 compatible = "arm,cortex-a53"; 36 device_type = "cpu"; 37 reg = <1>; 38 enable-method = "psci"; 39 clocks = <&ccu CLK_CPUX>; 40 clock-latency-ns = <244144>; /* 8 32k periods */ 41 #cooling-cells = <2>; 42 }; 43 44 cpu2: cpu@2 { 45 compatible = "arm,cortex-a53"; 46 device_type = "cpu"; 47 reg = <2>; 48 enable-method = "psci"; 49 clocks = <&ccu CLK_CPUX>; 50 clock-latency-ns = <244144>; /* 8 32k periods */ 51 #cooling-cells = <2>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 reg = <3>; 58 enable-method = "psci"; 59 clocks = <&ccu CLK_CPUX>; 60 clock-latency-ns = <244144>; /* 8 32k periods */ 61 #cooling-cells = <2>; 62 }; 63 }; 64 65 de: display-engine { 66 compatible = "allwinner,sun50i-h6-display-engine"; 67 allwinner,pipelines = <&mixer0>; 68 status = "disabled"; 69 }; 70 71 osc24M: osc24M_clk { 72 #clock-cells = <0>; 73 compatible = "fixed-clock"; 74 clock-frequency = <24000000>; 75 clock-output-names = "osc24M"; 76 }; 77 78 pmu { 79 compatible = "arm,cortex-a53-pmu"; 80 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 83 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 84 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 85 }; 86 87 psci { 88 compatible = "arm,psci-0.2"; 89 method = "smc"; 90 }; 91 92 timer { 93 compatible = "arm,armv8-timer"; 94 arm,no-tick-in-suspend; 95 interrupts = <GIC_PPI 13 96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 97 <GIC_PPI 14 98 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 99 <GIC_PPI 11 100 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 101 <GIC_PPI 10 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 103 }; 104 105 soc { 106 compatible = "simple-bus"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges; 110 111 bus@1000000 { 112 compatible = "allwinner,sun50i-h6-de3", 113 "allwinner,sun50i-a64-de2"; 114 reg = <0x1000000 0x400000>; 115 allwinner,sram = <&de2_sram 1>; 116 #address-cells = <1>; 117 #size-cells = <1>; 118 ranges = <0 0x1000000 0x400000>; 119 120 display_clocks: clock@0 { 121 compatible = "allwinner,sun50i-h6-de3-clk"; 122 reg = <0x0 0x10000>; 123 clocks = <&ccu CLK_BUS_DE>, 124 <&ccu CLK_DE>; 125 clock-names = "bus", 126 "mod"; 127 resets = <&ccu RST_BUS_DE>; 128 #clock-cells = <1>; 129 #reset-cells = <1>; 130 }; 131 132 mixer0: mixer@100000 { 133 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 134 reg = <0x100000 0x100000>; 135 clocks = <&display_clocks CLK_BUS_MIXER0>, 136 <&display_clocks CLK_MIXER0>; 137 clock-names = "bus", 138 "mod"; 139 resets = <&display_clocks RST_MIXER0>; 140 iommus = <&iommu 0>; 141 142 ports { 143 #address-cells = <1>; 144 #size-cells = <0>; 145 146 mixer0_out: port@1 { 147 reg = <1>; 148 149 mixer0_out_tcon_top_mixer0: endpoint { 150 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 151 }; 152 }; 153 }; 154 }; 155 }; 156 157 video-codec-g2@1c00000 { 158 compatible = "allwinner,sun50i-h6-vpu-g2"; 159 reg = <0x01c00000 0x1000>; 160 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 161 clocks = <&ccu CLK_BUS_VP9>, <&ccu CLK_VP9>; 162 clock-names = "bus", "mod"; 163 resets = <&ccu RST_BUS_VP9>; 164 }; 165 166 video-codec@1c0e000 { 167 compatible = "allwinner,sun50i-h6-video-engine"; 168 reg = <0x01c0e000 0x2000>; 169 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 170 <&ccu CLK_MBUS_VE>; 171 clock-names = "ahb", "mod", "ram"; 172 resets = <&ccu RST_BUS_VE>; 173 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 174 allwinner,sram = <&ve_sram 1>; 175 iommus = <&iommu 3>; 176 }; 177 178 gpu: gpu@1800000 { 179 compatible = "allwinner,sun50i-h6-mali", 180 "arm,mali-t720"; 181 reg = <0x01800000 0x4000>; 182 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 185 interrupt-names = "job", "mmu", "gpu"; 186 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 187 clock-names = "core", "bus"; 188 resets = <&ccu RST_BUS_GPU>; 189 #cooling-cells = <2>; 190 status = "disabled"; 191 }; 192 193 crypto: crypto@1904000 { 194 compatible = "allwinner,sun50i-h6-crypto"; 195 reg = <0x01904000 0x1000>; 196 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 197 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; 198 clock-names = "bus", "mod", "ram"; 199 resets = <&ccu RST_BUS_CE>; 200 }; 201 202 syscon: syscon@3000000 { 203 compatible = "allwinner,sun50i-h6-system-control", 204 "allwinner,sun50i-a64-system-control"; 205 reg = <0x03000000 0x1000>; 206 #address-cells = <1>; 207 #size-cells = <1>; 208 ranges; 209 210 sram_c: sram@28000 { 211 compatible = "mmio-sram"; 212 reg = <0x00028000 0x1e000>; 213 #address-cells = <1>; 214 #size-cells = <1>; 215 ranges = <0 0x00028000 0x1e000>; 216 217 de2_sram: sram-section@0 { 218 compatible = "allwinner,sun50i-h6-sram-c", 219 "allwinner,sun50i-a64-sram-c"; 220 reg = <0x0000 0x1e000>; 221 }; 222 }; 223 224 sram_c1: sram@1a00000 { 225 compatible = "mmio-sram"; 226 reg = <0x01a00000 0x200000>; 227 #address-cells = <1>; 228 #size-cells = <1>; 229 ranges = <0 0x01a00000 0x200000>; 230 231 ve_sram: sram-section@0 { 232 compatible = "allwinner,sun50i-h6-sram-c1", 233 "allwinner,sun4i-a10-sram-c1"; 234 reg = <0x000000 0x200000>; 235 }; 236 }; 237 }; 238 239 ccu: clock@3001000 { 240 compatible = "allwinner,sun50i-h6-ccu"; 241 reg = <0x03001000 0x1000>; 242 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>; 243 clock-names = "hosc", "losc", "iosc"; 244 #clock-cells = <1>; 245 #reset-cells = <1>; 246 }; 247 248 dma: dma-controller@3002000 { 249 compatible = "allwinner,sun50i-h6-dma"; 250 reg = <0x03002000 0x1000>; 251 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 252 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 253 clock-names = "bus", "mbus"; 254 dma-channels = <16>; 255 dma-requests = <46>; 256 resets = <&ccu RST_BUS_DMA>; 257 #dma-cells = <1>; 258 }; 259 260 msgbox: mailbox@3003000 { 261 compatible = "allwinner,sun50i-h6-msgbox", 262 "allwinner,sun6i-a31-msgbox"; 263 reg = <0x03003000 0x1000>; 264 clocks = <&ccu CLK_BUS_MSGBOX>; 265 resets = <&ccu RST_BUS_MSGBOX>; 266 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 267 #mbox-cells = <1>; 268 }; 269 270 sid: efuse@3006000 { 271 compatible = "allwinner,sun50i-h6-sid"; 272 reg = <0x03006000 0x400>; 273 #address-cells = <1>; 274 #size-cells = <1>; 275 276 ths_calibration: thermal-sensor-calibration@14 { 277 reg = <0x14 0x8>; 278 }; 279 280 cpu_speed_grade: cpu-speed-grade@1c { 281 reg = <0x1c 0x4>; 282 }; 283 }; 284 285 timer@3009000 { 286 compatible = "allwinner,sun50i-h6-timer", 287 "allwinner,sun8i-a23-timer"; 288 reg = <0x03009000 0xa0>; 289 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&osc24M>; 292 }; 293 294 watchdog: watchdog@30090a0 { 295 compatible = "allwinner,sun50i-h6-wdt", 296 "allwinner,sun6i-a31-wdt"; 297 reg = <0x030090a0 0x20>; 298 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&osc24M>; 300 /* Broken on some H6 boards */ 301 status = "disabled"; 302 }; 303 304 pwm: pwm@300a000 { 305 compatible = "allwinner,sun50i-h6-pwm"; 306 reg = <0x0300a000 0x400>; 307 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; 308 clock-names = "mod", "bus"; 309 resets = <&ccu RST_BUS_PWM>; 310 #pwm-cells = <3>; 311 status = "disabled"; 312 }; 313 314 pio: pinctrl@300b000 { 315 compatible = "allwinner,sun50i-h6-pinctrl"; 316 reg = <0x0300b000 0x400>; 317 interrupt-parent = <&r_intc>; 318 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 319 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 320 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 321 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; 323 clock-names = "apb", "hosc", "losc"; 324 gpio-controller; 325 #gpio-cells = <3>; 326 interrupt-controller; 327 #interrupt-cells = <3>; 328 329 ext_rgmii_pins: rgmii-pins { 330 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 331 "PD5", "PD7", "PD8", "PD9", "PD10", 332 "PD11", "PD12", "PD13", "PD19", "PD20"; 333 function = "emac"; 334 drive-strength = <40>; 335 }; 336 337 hdmi_pins: hdmi-pins { 338 pins = "PH8", "PH9", "PH10"; 339 function = "hdmi"; 340 }; 341 342 i2c0_pins: i2c0-pins { 343 pins = "PD25", "PD26"; 344 function = "i2c0"; 345 }; 346 347 i2c1_pins: i2c1-pins { 348 pins = "PH5", "PH6"; 349 function = "i2c1"; 350 }; 351 352 i2c2_pins: i2c2-pins { 353 pins = "PD23", "PD24"; 354 function = "i2c2"; 355 }; 356 357 mmc0_pins: mmc0-pins { 358 pins = "PF0", "PF1", "PF2", "PF3", 359 "PF4", "PF5"; 360 function = "mmc0"; 361 drive-strength = <30>; 362 bias-pull-up; 363 }; 364 365 /omit-if-no-ref/ 366 mmc1_pins: mmc1-pins { 367 pins = "PG0", "PG1", "PG2", "PG3", 368 "PG4", "PG5"; 369 function = "mmc1"; 370 drive-strength = <30>; 371 bias-pull-up; 372 }; 373 374 mmc2_pins: mmc2-pins { 375 pins = "PC1", "PC4", "PC5", "PC6", 376 "PC7", "PC8", "PC9", "PC10", 377 "PC11", "PC12", "PC13", "PC14"; 378 function = "mmc2"; 379 drive-strength = <30>; 380 bias-pull-up; 381 }; 382 383 /omit-if-no-ref/ 384 spi0_pins: spi0-pins { 385 pins = "PC0", "PC2", "PC3"; 386 function = "spi0"; 387 }; 388 389 /* pin shared with MMC2-CMD (eMMC) */ 390 /omit-if-no-ref/ 391 spi0_cs_pin: spi0-cs-pin { 392 pins = "PC5"; 393 function = "spi0"; 394 }; 395 396 /omit-if-no-ref/ 397 spi1_pins: spi1-pins { 398 pins = "PH4", "PH5", "PH6"; 399 function = "spi1"; 400 }; 401 402 /omit-if-no-ref/ 403 spi1_cs_pin: spi1-cs-pin { 404 pins = "PH3"; 405 function = "spi1"; 406 }; 407 408 spdif_tx_pin: spdif-tx-pin { 409 pins = "PH7"; 410 function = "spdif"; 411 }; 412 413 uart0_ph_pins: uart0-ph-pins { 414 pins = "PH0", "PH1"; 415 function = "uart0"; 416 }; 417 418 uart1_pins: uart1-pins { 419 pins = "PG6", "PG7"; 420 function = "uart1"; 421 }; 422 423 uart1_rts_cts_pins: uart1-rts-cts-pins { 424 pins = "PG8", "PG9"; 425 function = "uart1"; 426 }; 427 }; 428 429 gic: interrupt-controller@3021000 { 430 compatible = "arm,gic-400"; 431 reg = <0x03021000 0x1000>, 432 <0x03022000 0x2000>, 433 <0x03024000 0x2000>, 434 <0x03026000 0x2000>; 435 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 436 interrupt-controller; 437 #interrupt-cells = <3>; 438 }; 439 440 iommu: iommu@30f0000 { 441 compatible = "allwinner,sun50i-h6-iommu"; 442 reg = <0x030f0000 0x10000>; 443 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&ccu CLK_BUS_IOMMU>; 445 resets = <&ccu RST_BUS_IOMMU>; 446 #iommu-cells = <1>; 447 }; 448 449 mmc0: mmc@4020000 { 450 compatible = "allwinner,sun50i-h6-mmc", 451 "allwinner,sun50i-a64-mmc"; 452 reg = <0x04020000 0x1000>; 453 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 454 clock-names = "ahb", "mmc"; 455 resets = <&ccu RST_BUS_MMC0>; 456 reset-names = "ahb"; 457 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&mmc0_pins>; 460 max-frequency = <150000000>; 461 status = "disabled"; 462 #address-cells = <1>; 463 #size-cells = <0>; 464 }; 465 466 mmc1: mmc@4021000 { 467 compatible = "allwinner,sun50i-h6-mmc", 468 "allwinner,sun50i-a64-mmc"; 469 reg = <0x04021000 0x1000>; 470 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 471 clock-names = "ahb", "mmc"; 472 resets = <&ccu RST_BUS_MMC1>; 473 reset-names = "ahb"; 474 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 475 pinctrl-names = "default"; 476 pinctrl-0 = <&mmc1_pins>; 477 max-frequency = <150000000>; 478 status = "disabled"; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 }; 482 483 mmc2: mmc@4022000 { 484 compatible = "allwinner,sun50i-h6-emmc", 485 "allwinner,sun50i-a64-emmc"; 486 reg = <0x04022000 0x1000>; 487 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 488 clock-names = "ahb", "mmc"; 489 resets = <&ccu RST_BUS_MMC2>; 490 reset-names = "ahb"; 491 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 492 pinctrl-names = "default"; 493 pinctrl-0 = <&mmc2_pins>; 494 max-frequency = <150000000>; 495 status = "disabled"; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 }; 499 500 uart0: serial@5000000 { 501 compatible = "snps,dw-apb-uart"; 502 reg = <0x05000000 0x400>; 503 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 504 reg-shift = <2>; 505 reg-io-width = <4>; 506 clocks = <&ccu CLK_BUS_UART0>; 507 resets = <&ccu RST_BUS_UART0>; 508 status = "disabled"; 509 }; 510 511 uart1: serial@5000400 { 512 compatible = "snps,dw-apb-uart"; 513 reg = <0x05000400 0x400>; 514 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 515 reg-shift = <2>; 516 reg-io-width = <4>; 517 clocks = <&ccu CLK_BUS_UART1>; 518 resets = <&ccu RST_BUS_UART1>; 519 status = "disabled"; 520 }; 521 522 uart2: serial@5000800 { 523 compatible = "snps,dw-apb-uart"; 524 reg = <0x05000800 0x400>; 525 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 526 reg-shift = <2>; 527 reg-io-width = <4>; 528 clocks = <&ccu CLK_BUS_UART2>; 529 resets = <&ccu RST_BUS_UART2>; 530 status = "disabled"; 531 }; 532 533 uart3: serial@5000c00 { 534 compatible = "snps,dw-apb-uart"; 535 reg = <0x05000c00 0x400>; 536 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 537 reg-shift = <2>; 538 reg-io-width = <4>; 539 clocks = <&ccu CLK_BUS_UART3>; 540 resets = <&ccu RST_BUS_UART3>; 541 status = "disabled"; 542 }; 543 544 i2c0: i2c@5002000 { 545 compatible = "allwinner,sun50i-h6-i2c", 546 "allwinner,sun6i-a31-i2c"; 547 reg = <0x05002000 0x400>; 548 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 549 clocks = <&ccu CLK_BUS_I2C0>; 550 resets = <&ccu RST_BUS_I2C0>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&i2c0_pins>; 553 status = "disabled"; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 }; 557 558 i2c1: i2c@5002400 { 559 compatible = "allwinner,sun50i-h6-i2c", 560 "allwinner,sun6i-a31-i2c"; 561 reg = <0x05002400 0x400>; 562 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 563 clocks = <&ccu CLK_BUS_I2C1>; 564 resets = <&ccu RST_BUS_I2C1>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&i2c1_pins>; 567 status = "disabled"; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 }; 571 572 i2c2: i2c@5002800 { 573 compatible = "allwinner,sun50i-h6-i2c", 574 "allwinner,sun6i-a31-i2c"; 575 reg = <0x05002800 0x400>; 576 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 577 clocks = <&ccu CLK_BUS_I2C2>; 578 resets = <&ccu RST_BUS_I2C2>; 579 pinctrl-names = "default"; 580 pinctrl-0 = <&i2c2_pins>; 581 status = "disabled"; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 }; 585 586 spi0: spi@5010000 { 587 compatible = "allwinner,sun50i-h6-spi", 588 "allwinner,sun8i-h3-spi"; 589 reg = <0x05010000 0x1000>; 590 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 592 clock-names = "ahb", "mod"; 593 dmas = <&dma 22>, <&dma 22>; 594 dma-names = "rx", "tx"; 595 resets = <&ccu RST_BUS_SPI0>; 596 status = "disabled"; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 }; 600 601 spi1: spi@5011000 { 602 compatible = "allwinner,sun50i-h6-spi", 603 "allwinner,sun8i-h3-spi"; 604 reg = <0x05011000 0x1000>; 605 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 607 clock-names = "ahb", "mod"; 608 dmas = <&dma 23>, <&dma 23>; 609 dma-names = "rx", "tx"; 610 resets = <&ccu RST_BUS_SPI1>; 611 status = "disabled"; 612 #address-cells = <1>; 613 #size-cells = <0>; 614 }; 615 616 emac: ethernet@5020000 { 617 compatible = "allwinner,sun50i-h6-emac", 618 "allwinner,sun50i-a64-emac"; 619 syscon = <&syscon>; 620 reg = <0x05020000 0x10000>; 621 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 622 interrupt-names = "macirq"; 623 resets = <&ccu RST_BUS_EMAC>; 624 reset-names = "stmmaceth"; 625 clocks = <&ccu CLK_BUS_EMAC>; 626 clock-names = "stmmaceth"; 627 status = "disabled"; 628 629 mdio: mdio { 630 compatible = "snps,dwmac-mdio"; 631 #address-cells = <1>; 632 #size-cells = <0>; 633 }; 634 }; 635 636 i2s1: i2s@5091000 { 637 #sound-dai-cells = <0>; 638 compatible = "allwinner,sun50i-h6-i2s"; 639 reg = <0x05091000 0x1000>; 640 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 642 clock-names = "apb", "mod"; 643 dmas = <&dma 4>, <&dma 4>; 644 resets = <&ccu RST_BUS_I2S1>; 645 dma-names = "rx", "tx"; 646 status = "disabled"; 647 }; 648 649 spdif: spdif@5093000 { 650 #sound-dai-cells = <0>; 651 compatible = "allwinner,sun50i-h6-spdif"; 652 reg = <0x05093000 0x400>; 653 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 655 clock-names = "apb", "spdif"; 656 resets = <&ccu RST_BUS_SPDIF>; 657 dmas = <&dma 2>; 658 dma-names = "tx"; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&spdif_tx_pin>; 661 status = "disabled"; 662 }; 663 664 usb2otg: usb@5100000 { 665 compatible = "allwinner,sun50i-h6-musb", 666 "allwinner,sun8i-a33-musb"; 667 reg = <0x05100000 0x0400>; 668 clocks = <&ccu CLK_BUS_OTG>; 669 resets = <&ccu RST_BUS_OTG>; 670 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 671 interrupt-names = "mc"; 672 phys = <&usb2phy 0>; 673 phy-names = "usb"; 674 extcon = <&usb2phy 0>; 675 status = "disabled"; 676 }; 677 678 usb2phy: phy@5100400 { 679 compatible = "allwinner,sun50i-h6-usb-phy"; 680 reg = <0x05100400 0x24>, 681 <0x05101800 0x4>, 682 <0x05311800 0x4>; 683 reg-names = "phy_ctrl", 684 "pmu0", 685 "pmu3"; 686 clocks = <&ccu CLK_USB_PHY0>, 687 <&ccu CLK_USB_PHY3>; 688 clock-names = "usb0_phy", 689 "usb3_phy"; 690 resets = <&ccu RST_USB_PHY0>, 691 <&ccu RST_USB_PHY3>; 692 reset-names = "usb0_reset", 693 "usb3_reset"; 694 status = "disabled"; 695 #phy-cells = <1>; 696 }; 697 698 ehci0: usb@5101000 { 699 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 700 reg = <0x05101000 0x100>; 701 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&ccu CLK_BUS_OHCI0>, 703 <&ccu CLK_BUS_EHCI0>, 704 <&ccu CLK_USB_OHCI0>; 705 resets = <&ccu RST_BUS_OHCI0>, 706 <&ccu RST_BUS_EHCI0>; 707 phys = <&usb2phy 0>; 708 phy-names = "usb"; 709 status = "disabled"; 710 }; 711 712 ohci0: usb@5101400 { 713 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 714 reg = <0x05101400 0x100>; 715 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&ccu CLK_BUS_OHCI0>, 717 <&ccu CLK_USB_OHCI0>; 718 resets = <&ccu RST_BUS_OHCI0>; 719 phys = <&usb2phy 0>; 720 phy-names = "usb"; 721 status = "disabled"; 722 }; 723 724 dwc3: usb@5200000 { 725 compatible = "snps,dwc3"; 726 reg = <0x05200000 0x10000>; 727 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&ccu CLK_BUS_XHCI>, 729 <&ccu CLK_BUS_XHCI>, 730 <&rtc CLK_OSC32K>; 731 clock-names = "ref", "bus_early", "suspend"; 732 resets = <&ccu RST_BUS_XHCI>; 733 /* 734 * The datasheet of the chip doesn't declare the 735 * peripheral function, and there's no boards known 736 * to have a USB Type-B port routed to the port. 737 * In addition, no one has tested the peripheral 738 * function yet. 739 * So set the dr_mode to "host" in the DTSI file. 740 */ 741 dr_mode = "host"; 742 phys = <&usb3phy>; 743 phy-names = "usb3-phy"; 744 status = "disabled"; 745 }; 746 747 usb3phy: phy@5210000 { 748 compatible = "allwinner,sun50i-h6-usb3-phy"; 749 reg = <0x5210000 0x10000>; 750 clocks = <&ccu CLK_USB_PHY1>; 751 resets = <&ccu RST_USB_PHY1>; 752 #phy-cells = <0>; 753 status = "disabled"; 754 }; 755 756 ehci3: usb@5311000 { 757 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 758 reg = <0x05311000 0x100>; 759 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&ccu CLK_BUS_OHCI3>, 761 <&ccu CLK_BUS_EHCI3>, 762 <&ccu CLK_USB_OHCI3>; 763 resets = <&ccu RST_BUS_OHCI3>, 764 <&ccu RST_BUS_EHCI3>; 765 phys = <&usb2phy 3>; 766 phy-names = "usb"; 767 status = "disabled"; 768 }; 769 770 ohci3: usb@5311400 { 771 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 772 reg = <0x05311400 0x100>; 773 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 774 clocks = <&ccu CLK_BUS_OHCI3>, 775 <&ccu CLK_USB_OHCI3>; 776 resets = <&ccu RST_BUS_OHCI3>; 777 phys = <&usb2phy 3>; 778 phy-names = "usb"; 779 status = "disabled"; 780 }; 781 782 hdmi: hdmi@6000000 { 783 compatible = "allwinner,sun50i-h6-dw-hdmi"; 784 reg = <0x06000000 0x10000>; 785 reg-io-width = <1>; 786 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 787 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 788 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 789 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 790 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 791 "hdcp-bus"; 792 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 793 reset-names = "ctrl", "hdcp"; 794 phys = <&hdmi_phy>; 795 phy-names = "phy"; 796 pinctrl-names = "default"; 797 pinctrl-0 = <&hdmi_pins>; 798 status = "disabled"; 799 800 ports { 801 #address-cells = <1>; 802 #size-cells = <0>; 803 804 hdmi_in: port@0 { 805 reg = <0>; 806 807 hdmi_in_tcon_top: endpoint { 808 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 809 }; 810 }; 811 812 hdmi_out: port@1 { 813 reg = <1>; 814 }; 815 }; 816 }; 817 818 hdmi_phy: hdmi-phy@6010000 { 819 compatible = "allwinner,sun50i-h6-hdmi-phy"; 820 reg = <0x06010000 0x10000>; 821 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 822 clock-names = "bus", "mod"; 823 resets = <&ccu RST_BUS_HDMI>; 824 reset-names = "phy"; 825 #phy-cells = <0>; 826 }; 827 828 tcon_top: tcon-top@6510000 { 829 compatible = "allwinner,sun50i-h6-tcon-top"; 830 reg = <0x06510000 0x1000>; 831 clocks = <&ccu CLK_BUS_TCON_TOP>, 832 <&ccu CLK_TCON_TV0>; 833 clock-names = "bus", 834 "tcon-tv0"; 835 clock-output-names = "tcon-top-tv0"; 836 resets = <&ccu RST_BUS_TCON_TOP>; 837 #clock-cells = <1>; 838 839 ports { 840 #address-cells = <1>; 841 #size-cells = <0>; 842 843 tcon_top_mixer0_in: port@0 { 844 #address-cells = <1>; 845 #size-cells = <0>; 846 reg = <0>; 847 848 tcon_top_mixer0_in_mixer0: endpoint@0 { 849 reg = <0>; 850 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 851 }; 852 }; 853 854 tcon_top_mixer0_out: port@1 { 855 #address-cells = <1>; 856 #size-cells = <0>; 857 reg = <1>; 858 859 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 860 reg = <2>; 861 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 862 }; 863 }; 864 865 tcon_top_hdmi_in: port@4 { 866 #address-cells = <1>; 867 #size-cells = <0>; 868 reg = <4>; 869 870 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 871 reg = <0>; 872 remote-endpoint = <&tcon_tv_out_tcon_top>; 873 }; 874 }; 875 876 tcon_top_hdmi_out: port@5 { 877 reg = <5>; 878 879 tcon_top_hdmi_out_hdmi: endpoint { 880 remote-endpoint = <&hdmi_in_tcon_top>; 881 }; 882 }; 883 }; 884 }; 885 886 tcon_tv: lcd-controller@6515000 { 887 compatible = "allwinner,sun50i-h6-tcon-tv", 888 "allwinner,sun8i-r40-tcon-tv"; 889 reg = <0x06515000 0x1000>; 890 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&ccu CLK_BUS_TCON_TV0>, 892 <&tcon_top CLK_TCON_TOP_TV0>; 893 clock-names = "ahb", 894 "tcon-ch1"; 895 resets = <&ccu RST_BUS_TCON_TV0>; 896 reset-names = "lcd"; 897 898 ports { 899 #address-cells = <1>; 900 #size-cells = <0>; 901 902 tcon_tv_in: port@0 { 903 reg = <0>; 904 905 tcon_tv_in_tcon_top_mixer0: endpoint { 906 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 907 }; 908 }; 909 910 tcon_tv_out: port@1 { 911 #address-cells = <1>; 912 #size-cells = <0>; 913 reg = <1>; 914 915 tcon_tv_out_tcon_top: endpoint@1 { 916 reg = <1>; 917 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 918 }; 919 }; 920 }; 921 }; 922 923 rtc: rtc@7000000 { 924 compatible = "allwinner,sun50i-h6-rtc"; 925 reg = <0x07000000 0x400>; 926 interrupt-parent = <&r_intc>; 927 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 929 clock-output-names = "osc32k", "osc32k-out", "iosc"; 930 #clock-cells = <1>; 931 }; 932 933 r_ccu: clock@7010000 { 934 compatible = "allwinner,sun50i-h6-r-ccu"; 935 reg = <0x07010000 0x400>; 936 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>, 937 <&ccu CLK_PLL_PERIPH0>; 938 clock-names = "hosc", "losc", "iosc", "pll-periph"; 939 #clock-cells = <1>; 940 #reset-cells = <1>; 941 }; 942 943 r_watchdog: watchdog@7020400 { 944 compatible = "allwinner,sun50i-h6-wdt", 945 "allwinner,sun6i-a31-wdt"; 946 reg = <0x07020400 0x20>; 947 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 948 clocks = <&osc24M>; 949 }; 950 951 r_intc: interrupt-controller@7021000 { 952 compatible = "allwinner,sun50i-h6-r-intc"; 953 interrupt-controller; 954 #interrupt-cells = <3>; 955 reg = <0x07021000 0x400>; 956 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 957 }; 958 959 r_pio: pinctrl@7022000 { 960 compatible = "allwinner,sun50i-h6-r-pinctrl"; 961 reg = <0x07022000 0x400>; 962 interrupt-parent = <&r_intc>; 963 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, 966 <&rtc CLK_OSC32K>; 967 clock-names = "apb", "hosc", "losc"; 968 gpio-controller; 969 #gpio-cells = <3>; 970 interrupt-controller; 971 #interrupt-cells = <3>; 972 973 r_i2c_pins: r-i2c-pins { 974 pins = "PL0", "PL1"; 975 function = "s_i2c"; 976 }; 977 978 r_ir_rx_pin: r-ir-rx-pin { 979 pins = "PL9"; 980 function = "s_cir_rx"; 981 }; 982 983 r_rsb_pins: r-rsb-pins { 984 pins = "PL0", "PL1"; 985 function = "s_rsb"; 986 }; 987 }; 988 989 r_ir: ir@7040000 { 990 compatible = "allwinner,sun50i-h6-ir", 991 "allwinner,sun6i-a31-ir"; 992 reg = <0x07040000 0x400>; 993 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&r_ccu CLK_R_APB1_IR>, 995 <&r_ccu CLK_IR>; 996 clock-names = "apb", "ir"; 997 resets = <&r_ccu RST_R_APB1_IR>; 998 pinctrl-names = "default"; 999 pinctrl-0 = <&r_ir_rx_pin>; 1000 status = "disabled"; 1001 }; 1002 1003 r_i2c: i2c@7081400 { 1004 compatible = "allwinner,sun50i-h6-i2c", 1005 "allwinner,sun6i-a31-i2c"; 1006 reg = <0x07081400 0x400>; 1007 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1008 clocks = <&r_ccu CLK_R_APB2_I2C>; 1009 resets = <&r_ccu RST_R_APB2_I2C>; 1010 pinctrl-names = "default"; 1011 pinctrl-0 = <&r_i2c_pins>; 1012 status = "disabled"; 1013 #address-cells = <1>; 1014 #size-cells = <0>; 1015 }; 1016 1017 r_rsb: rsb@7083000 { 1018 compatible = "allwinner,sun8i-a23-rsb"; 1019 reg = <0x07083000 0x400>; 1020 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&r_ccu CLK_R_APB2_RSB>; 1022 clock-frequency = <3000000>; 1023 resets = <&r_ccu RST_R_APB2_RSB>; 1024 pinctrl-names = "default"; 1025 pinctrl-0 = <&r_rsb_pins>; 1026 status = "disabled"; 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 }; 1030 1031 ths: thermal-sensor@5070400 { 1032 compatible = "allwinner,sun50i-h6-ths"; 1033 reg = <0x05070400 0x100>; 1034 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&ccu CLK_BUS_THS>; 1036 clock-names = "bus"; 1037 resets = <&ccu RST_BUS_THS>; 1038 nvmem-cells = <&ths_calibration>; 1039 nvmem-cell-names = "calibration"; 1040 #thermal-sensor-cells = <1>; 1041 }; 1042 }; 1043 1044 thermal-zones { 1045 cpu-thermal { 1046 polling-delay-passive = <0>; 1047 polling-delay = <0>; 1048 thermal-sensors = <&ths 0>; 1049 1050 trips { 1051 cpu_alert: cpu-alert { 1052 temperature = <85000>; 1053 hysteresis = <2000>; 1054 type = "passive"; 1055 }; 1056 1057 cpu-crit { 1058 temperature = <100000>; 1059 hysteresis = <0>; 1060 type = "critical"; 1061 }; 1062 }; 1063 1064 cooling-maps { 1065 map0 { 1066 trip = <&cpu_alert>; 1067 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1068 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1069 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1070 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1071 }; 1072 }; 1073 }; 1074 1075 gpu-thermal { 1076 polling-delay-passive = <1000>; 1077 polling-delay = <2000>; 1078 thermal-sensors = <&ths 1>; 1079 1080 trips { 1081 gpu_alert0: gpu-alert-0 { 1082 temperature = <95000>; 1083 hysteresis = <2000>; 1084 type = "passive"; 1085 }; 1086 1087 gpu_alert1: gpu-alert-1 { 1088 temperature = <100000>; 1089 hysteresis = <2000>; 1090 type = "passive"; 1091 }; 1092 1093 gpu_alert2: gpu-alert-2 { 1094 temperature = <105000>; 1095 hysteresis = <2000>; 1096 type = "passive"; 1097 }; 1098 1099 gpu-crit { 1100 temperature = <115000>; 1101 hysteresis = <0>; 1102 type = "critical"; 1103 }; 1104 }; 1105 1106 cooling-maps { 1107 // Forbid the GPU to go over 756MHz 1108 map0 { 1109 trip = <&gpu_alert0>; 1110 cooling-device = <&gpu 1 THERMAL_NO_LIMIT>; 1111 }; 1112 1113 // Forbid the GPU to go over 624MHz 1114 map1 { 1115 trip = <&gpu_alert1>; 1116 cooling-device = <&gpu 2 THERMAL_NO_LIMIT>; 1117 }; 1118 1119 // Forbid the GPU to go over 576MHz 1120 map2 { 1121 trip = <&gpu_alert2>; 1122 cooling-device = <&gpu 3 THERMAL_NO_LIMIT>; 1123 }; 1124 }; 1125 }; 1126 }; 1127}; 1128