1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun50i-h6-ccu.h> 6#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-tcon-top.h> 9#include <dt-bindings/reset/sun50i-h6-ccu.h> 10#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 clocks = <&ccu CLK_CPUX>; 29 clock-latency-ns = <244144>; /* 8 32k periods */ 30 #cooling-cells = <2>; 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 reg = <1>; 37 enable-method = "psci"; 38 clocks = <&ccu CLK_CPUX>; 39 clock-latency-ns = <244144>; /* 8 32k periods */ 40 #cooling-cells = <2>; 41 }; 42 43 cpu2: cpu@2 { 44 compatible = "arm,cortex-a53"; 45 device_type = "cpu"; 46 reg = <2>; 47 enable-method = "psci"; 48 clocks = <&ccu CLK_CPUX>; 49 clock-latency-ns = <244144>; /* 8 32k periods */ 50 #cooling-cells = <2>; 51 }; 52 53 cpu3: cpu@3 { 54 compatible = "arm,cortex-a53"; 55 device_type = "cpu"; 56 reg = <3>; 57 enable-method = "psci"; 58 clocks = <&ccu CLK_CPUX>; 59 clock-latency-ns = <244144>; /* 8 32k periods */ 60 #cooling-cells = <2>; 61 }; 62 }; 63 64 de: display-engine { 65 compatible = "allwinner,sun50i-h6-display-engine"; 66 allwinner,pipelines = <&mixer0>; 67 status = "disabled"; 68 }; 69 70 osc24M: osc24M_clk { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <24000000>; 74 clock-output-names = "osc24M"; 75 }; 76 77 pmu { 78 compatible = "arm,cortex-a53-pmu"; 79 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 84 }; 85 86 psci { 87 compatible = "arm,psci-0.2"; 88 method = "smc"; 89 }; 90 91 timer { 92 compatible = "arm,armv8-timer"; 93 arm,no-tick-in-suspend; 94 interrupts = <GIC_PPI 13 95 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 96 <GIC_PPI 14 97 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 11 99 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 100 <GIC_PPI 10 101 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 102 }; 103 104 soc { 105 compatible = "simple-bus"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges; 109 110 bus@1000000 { 111 compatible = "allwinner,sun50i-h6-de3", 112 "allwinner,sun50i-a64-de2"; 113 reg = <0x1000000 0x400000>; 114 allwinner,sram = <&de2_sram 1>; 115 #address-cells = <1>; 116 #size-cells = <1>; 117 ranges = <0 0x1000000 0x400000>; 118 119 display_clocks: clock@0 { 120 compatible = "allwinner,sun50i-h6-de3-clk"; 121 reg = <0x0 0x10000>; 122 clocks = <&ccu CLK_DE>, 123 <&ccu CLK_BUS_DE>; 124 clock-names = "mod", 125 "bus"; 126 resets = <&ccu RST_BUS_DE>; 127 #clock-cells = <1>; 128 #reset-cells = <1>; 129 }; 130 131 mixer0: mixer@100000 { 132 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 133 reg = <0x100000 0x100000>; 134 clocks = <&display_clocks CLK_BUS_MIXER0>, 135 <&display_clocks CLK_MIXER0>; 136 clock-names = "bus", 137 "mod"; 138 resets = <&display_clocks RST_MIXER0>; 139 iommus = <&iommu 0>; 140 141 ports { 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 mixer0_out: port@1 { 146 reg = <1>; 147 148 mixer0_out_tcon_top_mixer0: endpoint { 149 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 150 }; 151 }; 152 }; 153 }; 154 }; 155 156 video-codec@1c0e000 { 157 compatible = "allwinner,sun50i-h6-video-engine"; 158 reg = <0x01c0e000 0x2000>; 159 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 160 <&ccu CLK_MBUS_VE>; 161 clock-names = "ahb", "mod", "ram"; 162 resets = <&ccu RST_BUS_VE>; 163 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 164 allwinner,sram = <&ve_sram 1>; 165 iommus = <&iommu 3>; 166 }; 167 168 gpu: gpu@1800000 { 169 compatible = "allwinner,sun50i-h6-mali", 170 "arm,mali-t720"; 171 reg = <0x01800000 0x4000>; 172 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 175 interrupt-names = "job", "mmu", "gpu"; 176 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 177 clock-names = "core", "bus"; 178 resets = <&ccu RST_BUS_GPU>; 179 status = "disabled"; 180 }; 181 182 crypto: crypto@1904000 { 183 compatible = "allwinner,sun50i-h6-crypto"; 184 reg = <0x01904000 0x1000>; 185 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; 187 clock-names = "bus", "mod", "ram"; 188 resets = <&ccu RST_BUS_CE>; 189 }; 190 191 syscon: syscon@3000000 { 192 compatible = "allwinner,sun50i-h6-system-control", 193 "allwinner,sun50i-a64-system-control"; 194 reg = <0x03000000 0x1000>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 ranges; 198 199 sram_c: sram@28000 { 200 compatible = "mmio-sram"; 201 reg = <0x00028000 0x1e000>; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 ranges = <0 0x00028000 0x1e000>; 205 206 de2_sram: sram-section@0 { 207 compatible = "allwinner,sun50i-h6-sram-c", 208 "allwinner,sun50i-a64-sram-c"; 209 reg = <0x0000 0x1e000>; 210 }; 211 }; 212 213 sram_c1: sram@1a00000 { 214 compatible = "mmio-sram"; 215 reg = <0x01a00000 0x200000>; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges = <0 0x01a00000 0x200000>; 219 220 ve_sram: sram-section@0 { 221 compatible = "allwinner,sun50i-h6-sram-c1", 222 "allwinner,sun4i-a10-sram-c1"; 223 reg = <0x000000 0x200000>; 224 }; 225 }; 226 }; 227 228 ccu: clock@3001000 { 229 compatible = "allwinner,sun50i-h6-ccu"; 230 reg = <0x03001000 0x1000>; 231 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; 232 clock-names = "hosc", "losc", "iosc"; 233 #clock-cells = <1>; 234 #reset-cells = <1>; 235 }; 236 237 dma: dma-controller@3002000 { 238 compatible = "allwinner,sun50i-h6-dma"; 239 reg = <0x03002000 0x1000>; 240 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 242 clock-names = "bus", "mbus"; 243 dma-channels = <16>; 244 dma-requests = <46>; 245 resets = <&ccu RST_BUS_DMA>; 246 #dma-cells = <1>; 247 }; 248 249 msgbox: mailbox@3003000 { 250 compatible = "allwinner,sun50i-h6-msgbox", 251 "allwinner,sun6i-a31-msgbox"; 252 reg = <0x03003000 0x1000>; 253 clocks = <&ccu CLK_BUS_MSGBOX>; 254 resets = <&ccu RST_BUS_MSGBOX>; 255 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 256 #mbox-cells = <1>; 257 }; 258 259 sid: efuse@3006000 { 260 compatible = "allwinner,sun50i-h6-sid"; 261 reg = <0x03006000 0x400>; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 265 ths_calibration: thermal-sensor-calibration@14 { 266 reg = <0x14 0x8>; 267 }; 268 269 cpu_speed_grade: cpu-speed-grade@1c { 270 reg = <0x1c 0x4>; 271 }; 272 }; 273 274 watchdog: watchdog@30090a0 { 275 compatible = "allwinner,sun50i-h6-wdt", 276 "allwinner,sun6i-a31-wdt"; 277 reg = <0x030090a0 0x20>; 278 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&osc24M>; 280 /* Broken on some H6 boards */ 281 status = "disabled"; 282 }; 283 284 pwm: pwm@300a000 { 285 compatible = "allwinner,sun50i-h6-pwm"; 286 reg = <0x0300a000 0x400>; 287 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; 288 clock-names = "mod", "bus"; 289 resets = <&ccu RST_BUS_PWM>; 290 #pwm-cells = <3>; 291 status = "disabled"; 292 }; 293 294 pio: pinctrl@300b000 { 295 compatible = "allwinner,sun50i-h6-pinctrl"; 296 reg = <0x0300b000 0x400>; 297 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; 302 clock-names = "apb", "hosc", "losc"; 303 gpio-controller; 304 #gpio-cells = <3>; 305 interrupt-controller; 306 #interrupt-cells = <3>; 307 308 ext_rgmii_pins: rgmii-pins { 309 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 310 "PD5", "PD7", "PD8", "PD9", "PD10", 311 "PD11", "PD12", "PD13", "PD19", "PD20"; 312 function = "emac"; 313 drive-strength = <40>; 314 }; 315 316 hdmi_pins: hdmi-pins { 317 pins = "PH8", "PH9", "PH10"; 318 function = "hdmi"; 319 }; 320 321 i2c0_pins: i2c0-pins { 322 pins = "PD25", "PD26"; 323 function = "i2c0"; 324 }; 325 326 i2c1_pins: i2c1-pins { 327 pins = "PH5", "PH6"; 328 function = "i2c1"; 329 }; 330 331 i2c2_pins: i2c2-pins { 332 pins = "PD23", "PD24"; 333 function = "i2c2"; 334 }; 335 336 mmc0_pins: mmc0-pins { 337 pins = "PF0", "PF1", "PF2", "PF3", 338 "PF4", "PF5"; 339 function = "mmc0"; 340 drive-strength = <30>; 341 bias-pull-up; 342 }; 343 344 /omit-if-no-ref/ 345 mmc1_pins: mmc1-pins { 346 pins = "PG0", "PG1", "PG2", "PG3", 347 "PG4", "PG5"; 348 function = "mmc1"; 349 drive-strength = <30>; 350 bias-pull-up; 351 }; 352 353 mmc2_pins: mmc2-pins { 354 pins = "PC1", "PC4", "PC5", "PC6", 355 "PC7", "PC8", "PC9", "PC10", 356 "PC11", "PC12", "PC13", "PC14"; 357 function = "mmc2"; 358 drive-strength = <30>; 359 bias-pull-up; 360 }; 361 362 /omit-if-no-ref/ 363 spi0_pins: spi0-pins { 364 pins = "PC0", "PC2", "PC3"; 365 function = "spi0"; 366 }; 367 368 /* pin shared with MMC2-CMD (eMMC) */ 369 /omit-if-no-ref/ 370 spi0_cs_pin: spi0-cs-pin { 371 pins = "PC5"; 372 function = "spi0"; 373 }; 374 375 /omit-if-no-ref/ 376 spi1_pins: spi1-pins { 377 pins = "PH4", "PH5", "PH6"; 378 function = "spi1"; 379 }; 380 381 /omit-if-no-ref/ 382 spi1_cs_pin: spi1-cs-pin { 383 pins = "PH3"; 384 function = "spi1"; 385 }; 386 387 spdif_tx_pin: spdif-tx-pin { 388 pins = "PH7"; 389 function = "spdif"; 390 }; 391 392 uart0_ph_pins: uart0-ph-pins { 393 pins = "PH0", "PH1"; 394 function = "uart0"; 395 }; 396 397 uart1_pins: uart1-pins { 398 pins = "PG6", "PG7"; 399 function = "uart1"; 400 }; 401 402 uart1_rts_cts_pins: uart1-rts-cts-pins { 403 pins = "PG8", "PG9"; 404 function = "uart1"; 405 }; 406 }; 407 408 gic: interrupt-controller@3021000 { 409 compatible = "arm,gic-400"; 410 reg = <0x03021000 0x1000>, 411 <0x03022000 0x2000>, 412 <0x03024000 0x2000>, 413 <0x03026000 0x2000>; 414 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 415 interrupt-controller; 416 #interrupt-cells = <3>; 417 }; 418 419 iommu: iommu@30f0000 { 420 compatible = "allwinner,sun50i-h6-iommu"; 421 reg = <0x030f0000 0x10000>; 422 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 423 clocks = <&ccu CLK_BUS_IOMMU>; 424 resets = <&ccu RST_BUS_IOMMU>; 425 #iommu-cells = <1>; 426 }; 427 428 mmc0: mmc@4020000 { 429 compatible = "allwinner,sun50i-h6-mmc", 430 "allwinner,sun50i-a64-mmc"; 431 reg = <0x04020000 0x1000>; 432 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 433 clock-names = "ahb", "mmc"; 434 resets = <&ccu RST_BUS_MMC0>; 435 reset-names = "ahb"; 436 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 437 pinctrl-names = "default"; 438 pinctrl-0 = <&mmc0_pins>; 439 max-frequency = <150000000>; 440 status = "disabled"; 441 #address-cells = <1>; 442 #size-cells = <0>; 443 }; 444 445 mmc1: mmc@4021000 { 446 compatible = "allwinner,sun50i-h6-mmc", 447 "allwinner,sun50i-a64-mmc"; 448 reg = <0x04021000 0x1000>; 449 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 450 clock-names = "ahb", "mmc"; 451 resets = <&ccu RST_BUS_MMC1>; 452 reset-names = "ahb"; 453 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 454 pinctrl-names = "default"; 455 pinctrl-0 = <&mmc1_pins>; 456 max-frequency = <150000000>; 457 status = "disabled"; 458 #address-cells = <1>; 459 #size-cells = <0>; 460 }; 461 462 mmc2: mmc@4022000 { 463 compatible = "allwinner,sun50i-h6-emmc", 464 "allwinner,sun50i-a64-emmc"; 465 reg = <0x04022000 0x1000>; 466 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 467 clock-names = "ahb", "mmc"; 468 resets = <&ccu RST_BUS_MMC2>; 469 reset-names = "ahb"; 470 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 471 pinctrl-names = "default"; 472 pinctrl-0 = <&mmc2_pins>; 473 max-frequency = <150000000>; 474 status = "disabled"; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 }; 478 479 uart0: serial@5000000 { 480 compatible = "snps,dw-apb-uart"; 481 reg = <0x05000000 0x400>; 482 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 483 reg-shift = <2>; 484 reg-io-width = <4>; 485 clocks = <&ccu CLK_BUS_UART0>; 486 resets = <&ccu RST_BUS_UART0>; 487 status = "disabled"; 488 }; 489 490 uart1: serial@5000400 { 491 compatible = "snps,dw-apb-uart"; 492 reg = <0x05000400 0x400>; 493 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 494 reg-shift = <2>; 495 reg-io-width = <4>; 496 clocks = <&ccu CLK_BUS_UART1>; 497 resets = <&ccu RST_BUS_UART1>; 498 status = "disabled"; 499 }; 500 501 uart2: serial@5000800 { 502 compatible = "snps,dw-apb-uart"; 503 reg = <0x05000800 0x400>; 504 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 505 reg-shift = <2>; 506 reg-io-width = <4>; 507 clocks = <&ccu CLK_BUS_UART2>; 508 resets = <&ccu RST_BUS_UART2>; 509 status = "disabled"; 510 }; 511 512 uart3: serial@5000c00 { 513 compatible = "snps,dw-apb-uart"; 514 reg = <0x05000c00 0x400>; 515 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 516 reg-shift = <2>; 517 reg-io-width = <4>; 518 clocks = <&ccu CLK_BUS_UART3>; 519 resets = <&ccu RST_BUS_UART3>; 520 status = "disabled"; 521 }; 522 523 i2c0: i2c@5002000 { 524 compatible = "allwinner,sun50i-h6-i2c", 525 "allwinner,sun6i-a31-i2c"; 526 reg = <0x05002000 0x400>; 527 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 528 clocks = <&ccu CLK_BUS_I2C0>; 529 resets = <&ccu RST_BUS_I2C0>; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&i2c0_pins>; 532 status = "disabled"; 533 #address-cells = <1>; 534 #size-cells = <0>; 535 }; 536 537 i2c1: i2c@5002400 { 538 compatible = "allwinner,sun50i-h6-i2c", 539 "allwinner,sun6i-a31-i2c"; 540 reg = <0x05002400 0x400>; 541 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 542 clocks = <&ccu CLK_BUS_I2C1>; 543 resets = <&ccu RST_BUS_I2C1>; 544 pinctrl-names = "default"; 545 pinctrl-0 = <&i2c1_pins>; 546 status = "disabled"; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 }; 550 551 i2c2: i2c@5002800 { 552 compatible = "allwinner,sun50i-h6-i2c", 553 "allwinner,sun6i-a31-i2c"; 554 reg = <0x05002800 0x400>; 555 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 556 clocks = <&ccu CLK_BUS_I2C2>; 557 resets = <&ccu RST_BUS_I2C2>; 558 pinctrl-names = "default"; 559 pinctrl-0 = <&i2c2_pins>; 560 status = "disabled"; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 }; 564 565 spi0: spi@5010000 { 566 compatible = "allwinner,sun50i-h6-spi", 567 "allwinner,sun8i-h3-spi"; 568 reg = <0x05010000 0x1000>; 569 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 571 clock-names = "ahb", "mod"; 572 dmas = <&dma 22>, <&dma 22>; 573 dma-names = "rx", "tx"; 574 resets = <&ccu RST_BUS_SPI0>; 575 status = "disabled"; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 }; 579 580 spi1: spi@5011000 { 581 compatible = "allwinner,sun50i-h6-spi", 582 "allwinner,sun8i-h3-spi"; 583 reg = <0x05011000 0x1000>; 584 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 585 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 586 clock-names = "ahb", "mod"; 587 dmas = <&dma 23>, <&dma 23>; 588 dma-names = "rx", "tx"; 589 resets = <&ccu RST_BUS_SPI1>; 590 status = "disabled"; 591 #address-cells = <1>; 592 #size-cells = <0>; 593 }; 594 595 emac: ethernet@5020000 { 596 compatible = "allwinner,sun50i-h6-emac", 597 "allwinner,sun50i-a64-emac"; 598 syscon = <&syscon>; 599 reg = <0x05020000 0x10000>; 600 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 601 interrupt-names = "macirq"; 602 resets = <&ccu RST_BUS_EMAC>; 603 reset-names = "stmmaceth"; 604 clocks = <&ccu CLK_BUS_EMAC>; 605 clock-names = "stmmaceth"; 606 status = "disabled"; 607 608 mdio: mdio { 609 compatible = "snps,dwmac-mdio"; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 }; 613 }; 614 615 i2s1: i2s@5091000 { 616 #sound-dai-cells = <0>; 617 compatible = "allwinner,sun50i-h6-i2s"; 618 reg = <0x05091000 0x1000>; 619 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 621 clock-names = "apb", "mod"; 622 dmas = <&dma 4>, <&dma 4>; 623 resets = <&ccu RST_BUS_I2S1>; 624 dma-names = "rx", "tx"; 625 status = "disabled"; 626 }; 627 628 spdif: spdif@5093000 { 629 #sound-dai-cells = <0>; 630 compatible = "allwinner,sun50i-h6-spdif"; 631 reg = <0x05093000 0x400>; 632 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 633 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 634 clock-names = "apb", "spdif"; 635 resets = <&ccu RST_BUS_SPDIF>; 636 dmas = <&dma 2>; 637 dma-names = "tx"; 638 pinctrl-names = "default"; 639 pinctrl-0 = <&spdif_tx_pin>; 640 status = "disabled"; 641 }; 642 643 usb2otg: usb@5100000 { 644 compatible = "allwinner,sun50i-h6-musb", 645 "allwinner,sun8i-a33-musb"; 646 reg = <0x05100000 0x0400>; 647 clocks = <&ccu CLK_BUS_OTG>; 648 resets = <&ccu RST_BUS_OTG>; 649 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 650 interrupt-names = "mc"; 651 phys = <&usb2phy 0>; 652 phy-names = "usb"; 653 extcon = <&usb2phy 0>; 654 status = "disabled"; 655 }; 656 657 usb2phy: phy@5100400 { 658 compatible = "allwinner,sun50i-h6-usb-phy"; 659 reg = <0x05100400 0x24>, 660 <0x05101800 0x4>, 661 <0x05311800 0x4>; 662 reg-names = "phy_ctrl", 663 "pmu0", 664 "pmu3"; 665 clocks = <&ccu CLK_USB_PHY0>, 666 <&ccu CLK_USB_PHY3>; 667 clock-names = "usb0_phy", 668 "usb3_phy"; 669 resets = <&ccu RST_USB_PHY0>, 670 <&ccu RST_USB_PHY3>; 671 reset-names = "usb0_reset", 672 "usb3_reset"; 673 status = "disabled"; 674 #phy-cells = <1>; 675 }; 676 677 ehci0: usb@5101000 { 678 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 679 reg = <0x05101000 0x100>; 680 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 681 clocks = <&ccu CLK_BUS_OHCI0>, 682 <&ccu CLK_BUS_EHCI0>, 683 <&ccu CLK_USB_OHCI0>; 684 resets = <&ccu RST_BUS_OHCI0>, 685 <&ccu RST_BUS_EHCI0>; 686 phys = <&usb2phy 0>; 687 phy-names = "usb"; 688 status = "disabled"; 689 }; 690 691 ohci0: usb@5101400 { 692 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 693 reg = <0x05101400 0x100>; 694 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 695 clocks = <&ccu CLK_BUS_OHCI0>, 696 <&ccu CLK_USB_OHCI0>; 697 resets = <&ccu RST_BUS_OHCI0>; 698 phys = <&usb2phy 0>; 699 phy-names = "usb"; 700 status = "disabled"; 701 }; 702 703 dwc3: usb@5200000 { 704 compatible = "snps,dwc3"; 705 reg = <0x05200000 0x10000>; 706 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&ccu CLK_BUS_XHCI>, 708 <&ccu CLK_BUS_XHCI>, 709 <&rtc 0>; 710 clock-names = "ref", "bus_early", "suspend"; 711 resets = <&ccu RST_BUS_XHCI>; 712 /* 713 * The datasheet of the chip doesn't declare the 714 * peripheral function, and there's no boards known 715 * to have a USB Type-B port routed to the port. 716 * In addition, no one has tested the peripheral 717 * function yet. 718 * So set the dr_mode to "host" in the DTSI file. 719 */ 720 dr_mode = "host"; 721 phys = <&usb3phy>; 722 phy-names = "usb3-phy"; 723 status = "disabled"; 724 }; 725 726 usb3phy: phy@5210000 { 727 compatible = "allwinner,sun50i-h6-usb3-phy"; 728 reg = <0x5210000 0x10000>; 729 clocks = <&ccu CLK_USB_PHY1>; 730 resets = <&ccu RST_USB_PHY1>; 731 #phy-cells = <0>; 732 status = "disabled"; 733 }; 734 735 ehci3: usb@5311000 { 736 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 737 reg = <0x05311000 0x100>; 738 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&ccu CLK_BUS_OHCI3>, 740 <&ccu CLK_BUS_EHCI3>, 741 <&ccu CLK_USB_OHCI3>; 742 resets = <&ccu RST_BUS_OHCI3>, 743 <&ccu RST_BUS_EHCI3>; 744 phys = <&usb2phy 3>; 745 phy-names = "usb"; 746 status = "disabled"; 747 }; 748 749 ohci3: usb@5311400 { 750 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 751 reg = <0x05311400 0x100>; 752 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&ccu CLK_BUS_OHCI3>, 754 <&ccu CLK_USB_OHCI3>; 755 resets = <&ccu RST_BUS_OHCI3>; 756 phys = <&usb2phy 3>; 757 phy-names = "usb"; 758 status = "disabled"; 759 }; 760 761 hdmi: hdmi@6000000 { 762 compatible = "allwinner,sun50i-h6-dw-hdmi"; 763 reg = <0x06000000 0x10000>; 764 reg-io-width = <1>; 765 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 767 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 768 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 769 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 770 "hdcp-bus"; 771 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 772 reset-names = "ctrl", "hdcp"; 773 phys = <&hdmi_phy>; 774 phy-names = "phy"; 775 pinctrl-names = "default"; 776 pinctrl-0 = <&hdmi_pins>; 777 status = "disabled"; 778 779 ports { 780 #address-cells = <1>; 781 #size-cells = <0>; 782 783 hdmi_in: port@0 { 784 reg = <0>; 785 786 hdmi_in_tcon_top: endpoint { 787 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 788 }; 789 }; 790 791 hdmi_out: port@1 { 792 reg = <1>; 793 }; 794 }; 795 }; 796 797 hdmi_phy: hdmi-phy@6010000 { 798 compatible = "allwinner,sun50i-h6-hdmi-phy"; 799 reg = <0x06010000 0x10000>; 800 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 801 clock-names = "bus", "mod"; 802 resets = <&ccu RST_BUS_HDMI>; 803 reset-names = "phy"; 804 #phy-cells = <0>; 805 }; 806 807 tcon_top: tcon-top@6510000 { 808 compatible = "allwinner,sun50i-h6-tcon-top"; 809 reg = <0x06510000 0x1000>; 810 clocks = <&ccu CLK_BUS_TCON_TOP>, 811 <&ccu CLK_TCON_TV0>; 812 clock-names = "bus", 813 "tcon-tv0"; 814 clock-output-names = "tcon-top-tv0"; 815 resets = <&ccu RST_BUS_TCON_TOP>; 816 #clock-cells = <1>; 817 818 ports { 819 #address-cells = <1>; 820 #size-cells = <0>; 821 822 tcon_top_mixer0_in: port@0 { 823 #address-cells = <1>; 824 #size-cells = <0>; 825 reg = <0>; 826 827 tcon_top_mixer0_in_mixer0: endpoint@0 { 828 reg = <0>; 829 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 830 }; 831 }; 832 833 tcon_top_mixer0_out: port@1 { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 reg = <1>; 837 838 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 839 reg = <2>; 840 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 841 }; 842 }; 843 844 tcon_top_hdmi_in: port@4 { 845 #address-cells = <1>; 846 #size-cells = <0>; 847 reg = <4>; 848 849 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 850 reg = <0>; 851 remote-endpoint = <&tcon_tv_out_tcon_top>; 852 }; 853 }; 854 855 tcon_top_hdmi_out: port@5 { 856 reg = <5>; 857 858 tcon_top_hdmi_out_hdmi: endpoint { 859 remote-endpoint = <&hdmi_in_tcon_top>; 860 }; 861 }; 862 }; 863 }; 864 865 tcon_tv: lcd-controller@6515000 { 866 compatible = "allwinner,sun50i-h6-tcon-tv", 867 "allwinner,sun8i-r40-tcon-tv"; 868 reg = <0x06515000 0x1000>; 869 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 870 clocks = <&ccu CLK_BUS_TCON_TV0>, 871 <&tcon_top CLK_TCON_TOP_TV0>; 872 clock-names = "ahb", 873 "tcon-ch1"; 874 resets = <&ccu RST_BUS_TCON_TV0>; 875 reset-names = "lcd"; 876 877 ports { 878 #address-cells = <1>; 879 #size-cells = <0>; 880 881 tcon_tv_in: port@0 { 882 reg = <0>; 883 884 tcon_tv_in_tcon_top_mixer0: endpoint { 885 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 886 }; 887 }; 888 889 tcon_tv_out: port@1 { 890 #address-cells = <1>; 891 #size-cells = <0>; 892 reg = <1>; 893 894 tcon_tv_out_tcon_top: endpoint@1 { 895 reg = <1>; 896 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 897 }; 898 }; 899 }; 900 }; 901 902 rtc: rtc@7000000 { 903 compatible = "allwinner,sun50i-h6-rtc"; 904 reg = <0x07000000 0x400>; 905 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 907 clock-output-names = "osc32k", "osc32k-out", "iosc"; 908 #clock-cells = <1>; 909 }; 910 911 r_ccu: clock@7010000 { 912 compatible = "allwinner,sun50i-h6-r-ccu"; 913 reg = <0x07010000 0x400>; 914 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 915 <&ccu CLK_PLL_PERIPH0>; 916 clock-names = "hosc", "losc", "iosc", "pll-periph"; 917 #clock-cells = <1>; 918 #reset-cells = <1>; 919 }; 920 921 r_watchdog: watchdog@7020400 { 922 compatible = "allwinner,sun50i-h6-wdt", 923 "allwinner,sun6i-a31-wdt"; 924 reg = <0x07020400 0x20>; 925 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 926 clocks = <&osc24M>; 927 }; 928 929 r_intc: interrupt-controller@7021000 { 930 compatible = "allwinner,sun50i-h6-r-intc", 931 "allwinner,sun6i-a31-r-intc"; 932 interrupt-controller; 933 #interrupt-cells = <2>; 934 reg = <0x07021000 0x400>; 935 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 936 }; 937 938 r_pio: pinctrl@7022000 { 939 compatible = "allwinner,sun50i-h6-r-pinctrl"; 940 reg = <0x07022000 0x400>; 941 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 943 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; 944 clock-names = "apb", "hosc", "losc"; 945 gpio-controller; 946 #gpio-cells = <3>; 947 interrupt-controller; 948 #interrupt-cells = <3>; 949 950 r_i2c_pins: r-i2c-pins { 951 pins = "PL0", "PL1"; 952 function = "s_i2c"; 953 }; 954 955 r_ir_rx_pin: r-ir-rx-pin { 956 pins = "PL9"; 957 function = "s_cir_rx"; 958 }; 959 960 r_rsb_pins: r-rsb-pins { 961 pins = "PL0", "PL1"; 962 function = "s_rsb"; 963 }; 964 }; 965 966 r_ir: ir@7040000 { 967 compatible = "allwinner,sun50i-h6-ir", 968 "allwinner,sun6i-a31-ir"; 969 reg = <0x07040000 0x400>; 970 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 971 clocks = <&r_ccu CLK_R_APB1_IR>, 972 <&r_ccu CLK_IR>; 973 clock-names = "apb", "ir"; 974 resets = <&r_ccu RST_R_APB1_IR>; 975 pinctrl-names = "default"; 976 pinctrl-0 = <&r_ir_rx_pin>; 977 status = "disabled"; 978 }; 979 980 r_i2c: i2c@7081400 { 981 compatible = "allwinner,sun50i-h6-i2c", 982 "allwinner,sun6i-a31-i2c"; 983 reg = <0x07081400 0x400>; 984 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 985 clocks = <&r_ccu CLK_R_APB2_I2C>; 986 resets = <&r_ccu RST_R_APB2_I2C>; 987 pinctrl-names = "default"; 988 pinctrl-0 = <&r_i2c_pins>; 989 status = "disabled"; 990 #address-cells = <1>; 991 #size-cells = <0>; 992 }; 993 994 r_rsb: rsb@7083000 { 995 compatible = "allwinner,sun8i-a23-rsb"; 996 reg = <0x07083000 0x400>; 997 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 998 clocks = <&r_ccu 13>; 999 clock-frequency = <3000000>; 1000 resets = <&r_ccu 7>; 1001 pinctrl-names = "default"; 1002 pinctrl-0 = <&r_rsb_pins>; 1003 status = "disabled"; 1004 #address-cells = <1>; 1005 #size-cells = <0>; 1006 }; 1007 1008 ths: thermal-sensor@5070400 { 1009 compatible = "allwinner,sun50i-h6-ths"; 1010 reg = <0x05070400 0x100>; 1011 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1012 clocks = <&ccu CLK_BUS_THS>; 1013 clock-names = "bus"; 1014 resets = <&ccu RST_BUS_THS>; 1015 nvmem-cells = <&ths_calibration>; 1016 nvmem-cell-names = "calibration"; 1017 #thermal-sensor-cells = <1>; 1018 }; 1019 }; 1020 1021 thermal-zones { 1022 cpu-thermal { 1023 polling-delay-passive = <0>; 1024 polling-delay = <0>; 1025 thermal-sensors = <&ths 0>; 1026 1027 trips { 1028 cpu_alert: cpu-alert { 1029 temperature = <85000>; 1030 hysteresis = <2000>; 1031 type = "passive"; 1032 }; 1033 1034 cpu-crit { 1035 temperature = <100000>; 1036 hysteresis = <0>; 1037 type = "critical"; 1038 }; 1039 }; 1040 1041 cooling-maps { 1042 map0 { 1043 trip = <&cpu_alert>; 1044 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1045 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1046 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1047 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1048 }; 1049 }; 1050 }; 1051 1052 gpu-thermal { 1053 polling-delay-passive = <0>; 1054 polling-delay = <0>; 1055 thermal-sensors = <&ths 1>; 1056 }; 1057 }; 1058}; 1059