1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun50i-h6-ccu.h> 6#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-tcon-top.h> 9#include <dt-bindings/reset/sun50i-h6-ccu.h> 10#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 clocks = <&ccu CLK_CPUX>; 29 clock-latency-ns = <244144>; /* 8 32k periods */ 30 #cooling-cells = <2>; 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 reg = <1>; 37 enable-method = "psci"; 38 clocks = <&ccu CLK_CPUX>; 39 clock-latency-ns = <244144>; /* 8 32k periods */ 40 #cooling-cells = <2>; 41 }; 42 43 cpu2: cpu@2 { 44 compatible = "arm,cortex-a53"; 45 device_type = "cpu"; 46 reg = <2>; 47 enable-method = "psci"; 48 clocks = <&ccu CLK_CPUX>; 49 clock-latency-ns = <244144>; /* 8 32k periods */ 50 #cooling-cells = <2>; 51 }; 52 53 cpu3: cpu@3 { 54 compatible = "arm,cortex-a53"; 55 device_type = "cpu"; 56 reg = <3>; 57 enable-method = "psci"; 58 clocks = <&ccu CLK_CPUX>; 59 clock-latency-ns = <244144>; /* 8 32k periods */ 60 #cooling-cells = <2>; 61 }; 62 }; 63 64 de: display-engine { 65 compatible = "allwinner,sun50i-h6-display-engine"; 66 allwinner,pipelines = <&mixer0>; 67 status = "disabled"; 68 }; 69 70 osc24M: osc24M_clk { 71 #clock-cells = <0>; 72 compatible = "fixed-clock"; 73 clock-frequency = <24000000>; 74 clock-output-names = "osc24M"; 75 }; 76 77 pmu { 78 compatible = "arm,cortex-a53-pmu"; 79 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 80 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 84 }; 85 86 psci { 87 compatible = "arm,psci-0.2"; 88 method = "smc"; 89 }; 90 91 timer { 92 compatible = "arm,armv8-timer"; 93 arm,no-tick-in-suspend; 94 interrupts = <GIC_PPI 13 95 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 96 <GIC_PPI 14 97 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 98 <GIC_PPI 11 99 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 100 <GIC_PPI 10 101 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 102 }; 103 104 soc { 105 compatible = "simple-bus"; 106 #address-cells = <1>; 107 #size-cells = <1>; 108 ranges; 109 110 bus@1000000 { 111 compatible = "allwinner,sun50i-h6-de3", 112 "allwinner,sun50i-a64-de2"; 113 reg = <0x1000000 0x400000>; 114 allwinner,sram = <&de2_sram 1>; 115 #address-cells = <1>; 116 #size-cells = <1>; 117 ranges = <0 0x1000000 0x400000>; 118 119 display_clocks: clock@0 { 120 compatible = "allwinner,sun50i-h6-de3-clk"; 121 reg = <0x0 0x10000>; 122 clocks = <&ccu CLK_DE>, 123 <&ccu CLK_BUS_DE>; 124 clock-names = "mod", 125 "bus"; 126 resets = <&ccu RST_BUS_DE>; 127 #clock-cells = <1>; 128 #reset-cells = <1>; 129 }; 130 131 mixer0: mixer@100000 { 132 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 133 reg = <0x100000 0x100000>; 134 clocks = <&display_clocks CLK_BUS_MIXER0>, 135 <&display_clocks CLK_MIXER0>; 136 clock-names = "bus", 137 "mod"; 138 resets = <&display_clocks RST_MIXER0>; 139 iommus = <&iommu 0>; 140 141 ports { 142 #address-cells = <1>; 143 #size-cells = <0>; 144 145 mixer0_out: port@1 { 146 reg = <1>; 147 148 mixer0_out_tcon_top_mixer0: endpoint { 149 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 150 }; 151 }; 152 }; 153 }; 154 }; 155 156 video-codec@1c0e000 { 157 compatible = "allwinner,sun50i-h6-video-engine"; 158 reg = <0x01c0e000 0x2000>; 159 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 160 <&ccu CLK_MBUS_VE>; 161 clock-names = "ahb", "mod", "ram"; 162 resets = <&ccu RST_BUS_VE>; 163 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 164 allwinner,sram = <&ve_sram 1>; 165 iommus = <&iommu 3>; 166 }; 167 168 gpu: gpu@1800000 { 169 compatible = "allwinner,sun50i-h6-mali", 170 "arm,mali-t720"; 171 reg = <0x01800000 0x4000>; 172 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 173 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 175 interrupt-names = "job", "mmu", "gpu"; 176 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 177 clock-names = "core", "bus"; 178 resets = <&ccu RST_BUS_GPU>; 179 status = "disabled"; 180 }; 181 182 crypto: crypto@1904000 { 183 compatible = "allwinner,sun50i-h6-crypto"; 184 reg = <0x01904000 0x1000>; 185 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 186 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; 187 clock-names = "bus", "mod", "ram"; 188 resets = <&ccu RST_BUS_CE>; 189 }; 190 191 syscon: syscon@3000000 { 192 compatible = "allwinner,sun50i-h6-system-control", 193 "allwinner,sun50i-a64-system-control"; 194 reg = <0x03000000 0x1000>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 ranges; 198 199 sram_c: sram@28000 { 200 compatible = "mmio-sram"; 201 reg = <0x00028000 0x1e000>; 202 #address-cells = <1>; 203 #size-cells = <1>; 204 ranges = <0 0x00028000 0x1e000>; 205 206 de2_sram: sram-section@0 { 207 compatible = "allwinner,sun50i-h6-sram-c", 208 "allwinner,sun50i-a64-sram-c"; 209 reg = <0x0000 0x1e000>; 210 }; 211 }; 212 213 sram_c1: sram@1a00000 { 214 compatible = "mmio-sram"; 215 reg = <0x01a00000 0x200000>; 216 #address-cells = <1>; 217 #size-cells = <1>; 218 ranges = <0 0x01a00000 0x200000>; 219 220 ve_sram: sram-section@0 { 221 compatible = "allwinner,sun50i-h6-sram-c1", 222 "allwinner,sun4i-a10-sram-c1"; 223 reg = <0x000000 0x200000>; 224 }; 225 }; 226 }; 227 228 ccu: clock@3001000 { 229 compatible = "allwinner,sun50i-h6-ccu"; 230 reg = <0x03001000 0x1000>; 231 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; 232 clock-names = "hosc", "losc", "iosc"; 233 #clock-cells = <1>; 234 #reset-cells = <1>; 235 }; 236 237 dma: dma-controller@3002000 { 238 compatible = "allwinner,sun50i-h6-dma"; 239 reg = <0x03002000 0x1000>; 240 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 241 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 242 clock-names = "bus", "mbus"; 243 dma-channels = <16>; 244 dma-requests = <46>; 245 resets = <&ccu RST_BUS_DMA>; 246 #dma-cells = <1>; 247 }; 248 249 msgbox: mailbox@3003000 { 250 compatible = "allwinner,sun50i-h6-msgbox", 251 "allwinner,sun6i-a31-msgbox"; 252 reg = <0x03003000 0x1000>; 253 clocks = <&ccu CLK_BUS_MSGBOX>; 254 resets = <&ccu RST_BUS_MSGBOX>; 255 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 256 #mbox-cells = <1>; 257 }; 258 259 sid: efuse@3006000 { 260 compatible = "allwinner,sun50i-h6-sid"; 261 reg = <0x03006000 0x400>; 262 #address-cells = <1>; 263 #size-cells = <1>; 264 265 ths_calibration: thermal-sensor-calibration@14 { 266 reg = <0x14 0x8>; 267 }; 268 269 cpu_speed_grade: cpu-speed-grade@1c { 270 reg = <0x1c 0x4>; 271 }; 272 }; 273 274 watchdog: watchdog@30090a0 { 275 compatible = "allwinner,sun50i-h6-wdt", 276 "allwinner,sun6i-a31-wdt"; 277 reg = <0x030090a0 0x20>; 278 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&osc24M>; 280 /* Broken on some H6 boards */ 281 status = "disabled"; 282 }; 283 284 pwm: pwm@300a000 { 285 compatible = "allwinner,sun50i-h6-pwm"; 286 reg = <0x0300a000 0x400>; 287 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; 288 clock-names = "mod", "bus"; 289 resets = <&ccu RST_BUS_PWM>; 290 #pwm-cells = <3>; 291 status = "disabled"; 292 }; 293 294 pio: pinctrl@300b000 { 295 compatible = "allwinner,sun50i-h6-pinctrl"; 296 reg = <0x0300b000 0x400>; 297 interrupt-parent = <&r_intc>; 298 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; 303 clock-names = "apb", "hosc", "losc"; 304 gpio-controller; 305 #gpio-cells = <3>; 306 interrupt-controller; 307 #interrupt-cells = <3>; 308 309 ext_rgmii_pins: rgmii-pins { 310 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 311 "PD5", "PD7", "PD8", "PD9", "PD10", 312 "PD11", "PD12", "PD13", "PD19", "PD20"; 313 function = "emac"; 314 drive-strength = <40>; 315 }; 316 317 hdmi_pins: hdmi-pins { 318 pins = "PH8", "PH9", "PH10"; 319 function = "hdmi"; 320 }; 321 322 i2c0_pins: i2c0-pins { 323 pins = "PD25", "PD26"; 324 function = "i2c0"; 325 }; 326 327 i2c1_pins: i2c1-pins { 328 pins = "PH5", "PH6"; 329 function = "i2c1"; 330 }; 331 332 i2c2_pins: i2c2-pins { 333 pins = "PD23", "PD24"; 334 function = "i2c2"; 335 }; 336 337 mmc0_pins: mmc0-pins { 338 pins = "PF0", "PF1", "PF2", "PF3", 339 "PF4", "PF5"; 340 function = "mmc0"; 341 drive-strength = <30>; 342 bias-pull-up; 343 }; 344 345 /omit-if-no-ref/ 346 mmc1_pins: mmc1-pins { 347 pins = "PG0", "PG1", "PG2", "PG3", 348 "PG4", "PG5"; 349 function = "mmc1"; 350 drive-strength = <30>; 351 bias-pull-up; 352 }; 353 354 mmc2_pins: mmc2-pins { 355 pins = "PC1", "PC4", "PC5", "PC6", 356 "PC7", "PC8", "PC9", "PC10", 357 "PC11", "PC12", "PC13", "PC14"; 358 function = "mmc2"; 359 drive-strength = <30>; 360 bias-pull-up; 361 }; 362 363 /omit-if-no-ref/ 364 spi0_pins: spi0-pins { 365 pins = "PC0", "PC2", "PC3"; 366 function = "spi0"; 367 }; 368 369 /* pin shared with MMC2-CMD (eMMC) */ 370 /omit-if-no-ref/ 371 spi0_cs_pin: spi0-cs-pin { 372 pins = "PC5"; 373 function = "spi0"; 374 }; 375 376 /omit-if-no-ref/ 377 spi1_pins: spi1-pins { 378 pins = "PH4", "PH5", "PH6"; 379 function = "spi1"; 380 }; 381 382 /omit-if-no-ref/ 383 spi1_cs_pin: spi1-cs-pin { 384 pins = "PH3"; 385 function = "spi1"; 386 }; 387 388 spdif_tx_pin: spdif-tx-pin { 389 pins = "PH7"; 390 function = "spdif"; 391 }; 392 393 uart0_ph_pins: uart0-ph-pins { 394 pins = "PH0", "PH1"; 395 function = "uart0"; 396 }; 397 398 uart1_pins: uart1-pins { 399 pins = "PG6", "PG7"; 400 function = "uart1"; 401 }; 402 403 uart1_rts_cts_pins: uart1-rts-cts-pins { 404 pins = "PG8", "PG9"; 405 function = "uart1"; 406 }; 407 }; 408 409 gic: interrupt-controller@3021000 { 410 compatible = "arm,gic-400"; 411 reg = <0x03021000 0x1000>, 412 <0x03022000 0x2000>, 413 <0x03024000 0x2000>, 414 <0x03026000 0x2000>; 415 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 416 interrupt-controller; 417 #interrupt-cells = <3>; 418 }; 419 420 iommu: iommu@30f0000 { 421 compatible = "allwinner,sun50i-h6-iommu"; 422 reg = <0x030f0000 0x10000>; 423 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 424 clocks = <&ccu CLK_BUS_IOMMU>; 425 resets = <&ccu RST_BUS_IOMMU>; 426 #iommu-cells = <1>; 427 }; 428 429 mmc0: mmc@4020000 { 430 compatible = "allwinner,sun50i-h6-mmc", 431 "allwinner,sun50i-a64-mmc"; 432 reg = <0x04020000 0x1000>; 433 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 434 clock-names = "ahb", "mmc"; 435 resets = <&ccu RST_BUS_MMC0>; 436 reset-names = "ahb"; 437 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&mmc0_pins>; 440 max-frequency = <150000000>; 441 status = "disabled"; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 }; 445 446 mmc1: mmc@4021000 { 447 compatible = "allwinner,sun50i-h6-mmc", 448 "allwinner,sun50i-a64-mmc"; 449 reg = <0x04021000 0x1000>; 450 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 451 clock-names = "ahb", "mmc"; 452 resets = <&ccu RST_BUS_MMC1>; 453 reset-names = "ahb"; 454 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&mmc1_pins>; 457 max-frequency = <150000000>; 458 status = "disabled"; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 }; 462 463 mmc2: mmc@4022000 { 464 compatible = "allwinner,sun50i-h6-emmc", 465 "allwinner,sun50i-a64-emmc"; 466 reg = <0x04022000 0x1000>; 467 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 468 clock-names = "ahb", "mmc"; 469 resets = <&ccu RST_BUS_MMC2>; 470 reset-names = "ahb"; 471 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&mmc2_pins>; 474 max-frequency = <150000000>; 475 status = "disabled"; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 }; 479 480 uart0: serial@5000000 { 481 compatible = "snps,dw-apb-uart"; 482 reg = <0x05000000 0x400>; 483 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 484 reg-shift = <2>; 485 reg-io-width = <4>; 486 clocks = <&ccu CLK_BUS_UART0>; 487 resets = <&ccu RST_BUS_UART0>; 488 status = "disabled"; 489 }; 490 491 uart1: serial@5000400 { 492 compatible = "snps,dw-apb-uart"; 493 reg = <0x05000400 0x400>; 494 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 495 reg-shift = <2>; 496 reg-io-width = <4>; 497 clocks = <&ccu CLK_BUS_UART1>; 498 resets = <&ccu RST_BUS_UART1>; 499 status = "disabled"; 500 }; 501 502 uart2: serial@5000800 { 503 compatible = "snps,dw-apb-uart"; 504 reg = <0x05000800 0x400>; 505 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 506 reg-shift = <2>; 507 reg-io-width = <4>; 508 clocks = <&ccu CLK_BUS_UART2>; 509 resets = <&ccu RST_BUS_UART2>; 510 status = "disabled"; 511 }; 512 513 uart3: serial@5000c00 { 514 compatible = "snps,dw-apb-uart"; 515 reg = <0x05000c00 0x400>; 516 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 517 reg-shift = <2>; 518 reg-io-width = <4>; 519 clocks = <&ccu CLK_BUS_UART3>; 520 resets = <&ccu RST_BUS_UART3>; 521 status = "disabled"; 522 }; 523 524 i2c0: i2c@5002000 { 525 compatible = "allwinner,sun50i-h6-i2c", 526 "allwinner,sun6i-a31-i2c"; 527 reg = <0x05002000 0x400>; 528 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 529 clocks = <&ccu CLK_BUS_I2C0>; 530 resets = <&ccu RST_BUS_I2C0>; 531 pinctrl-names = "default"; 532 pinctrl-0 = <&i2c0_pins>; 533 status = "disabled"; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 }; 537 538 i2c1: i2c@5002400 { 539 compatible = "allwinner,sun50i-h6-i2c", 540 "allwinner,sun6i-a31-i2c"; 541 reg = <0x05002400 0x400>; 542 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&ccu CLK_BUS_I2C1>; 544 resets = <&ccu RST_BUS_I2C1>; 545 pinctrl-names = "default"; 546 pinctrl-0 = <&i2c1_pins>; 547 status = "disabled"; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 }; 551 552 i2c2: i2c@5002800 { 553 compatible = "allwinner,sun50i-h6-i2c", 554 "allwinner,sun6i-a31-i2c"; 555 reg = <0x05002800 0x400>; 556 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&ccu CLK_BUS_I2C2>; 558 resets = <&ccu RST_BUS_I2C2>; 559 pinctrl-names = "default"; 560 pinctrl-0 = <&i2c2_pins>; 561 status = "disabled"; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 }; 565 566 spi0: spi@5010000 { 567 compatible = "allwinner,sun50i-h6-spi", 568 "allwinner,sun8i-h3-spi"; 569 reg = <0x05010000 0x1000>; 570 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 571 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; 572 clock-names = "ahb", "mod"; 573 dmas = <&dma 22>, <&dma 22>; 574 dma-names = "rx", "tx"; 575 resets = <&ccu RST_BUS_SPI0>; 576 status = "disabled"; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 }; 580 581 spi1: spi@5011000 { 582 compatible = "allwinner,sun50i-h6-spi", 583 "allwinner,sun8i-h3-spi"; 584 reg = <0x05011000 0x1000>; 585 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 586 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; 587 clock-names = "ahb", "mod"; 588 dmas = <&dma 23>, <&dma 23>; 589 dma-names = "rx", "tx"; 590 resets = <&ccu RST_BUS_SPI1>; 591 status = "disabled"; 592 #address-cells = <1>; 593 #size-cells = <0>; 594 }; 595 596 emac: ethernet@5020000 { 597 compatible = "allwinner,sun50i-h6-emac", 598 "allwinner,sun50i-a64-emac"; 599 syscon = <&syscon>; 600 reg = <0x05020000 0x10000>; 601 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 602 interrupt-names = "macirq"; 603 resets = <&ccu RST_BUS_EMAC>; 604 reset-names = "stmmaceth"; 605 clocks = <&ccu CLK_BUS_EMAC>; 606 clock-names = "stmmaceth"; 607 status = "disabled"; 608 609 mdio: mdio { 610 compatible = "snps,dwmac-mdio"; 611 #address-cells = <1>; 612 #size-cells = <0>; 613 }; 614 }; 615 616 i2s1: i2s@5091000 { 617 #sound-dai-cells = <0>; 618 compatible = "allwinner,sun50i-h6-i2s"; 619 reg = <0x05091000 0x1000>; 620 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 621 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>; 622 clock-names = "apb", "mod"; 623 dmas = <&dma 4>, <&dma 4>; 624 resets = <&ccu RST_BUS_I2S1>; 625 dma-names = "rx", "tx"; 626 status = "disabled"; 627 }; 628 629 spdif: spdif@5093000 { 630 #sound-dai-cells = <0>; 631 compatible = "allwinner,sun50i-h6-spdif"; 632 reg = <0x05093000 0x400>; 633 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 635 clock-names = "apb", "spdif"; 636 resets = <&ccu RST_BUS_SPDIF>; 637 dmas = <&dma 2>; 638 dma-names = "tx"; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&spdif_tx_pin>; 641 status = "disabled"; 642 }; 643 644 usb2otg: usb@5100000 { 645 compatible = "allwinner,sun50i-h6-musb", 646 "allwinner,sun8i-a33-musb"; 647 reg = <0x05100000 0x0400>; 648 clocks = <&ccu CLK_BUS_OTG>; 649 resets = <&ccu RST_BUS_OTG>; 650 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-names = "mc"; 652 phys = <&usb2phy 0>; 653 phy-names = "usb"; 654 extcon = <&usb2phy 0>; 655 status = "disabled"; 656 }; 657 658 usb2phy: phy@5100400 { 659 compatible = "allwinner,sun50i-h6-usb-phy"; 660 reg = <0x05100400 0x24>, 661 <0x05101800 0x4>, 662 <0x05311800 0x4>; 663 reg-names = "phy_ctrl", 664 "pmu0", 665 "pmu3"; 666 clocks = <&ccu CLK_USB_PHY0>, 667 <&ccu CLK_USB_PHY3>; 668 clock-names = "usb0_phy", 669 "usb3_phy"; 670 resets = <&ccu RST_USB_PHY0>, 671 <&ccu RST_USB_PHY3>; 672 reset-names = "usb0_reset", 673 "usb3_reset"; 674 status = "disabled"; 675 #phy-cells = <1>; 676 }; 677 678 ehci0: usb@5101000 { 679 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 680 reg = <0x05101000 0x100>; 681 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 682 clocks = <&ccu CLK_BUS_OHCI0>, 683 <&ccu CLK_BUS_EHCI0>, 684 <&ccu CLK_USB_OHCI0>; 685 resets = <&ccu RST_BUS_OHCI0>, 686 <&ccu RST_BUS_EHCI0>; 687 phys = <&usb2phy 0>; 688 phy-names = "usb"; 689 status = "disabled"; 690 }; 691 692 ohci0: usb@5101400 { 693 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 694 reg = <0x05101400 0x100>; 695 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 696 clocks = <&ccu CLK_BUS_OHCI0>, 697 <&ccu CLK_USB_OHCI0>; 698 resets = <&ccu RST_BUS_OHCI0>; 699 phys = <&usb2phy 0>; 700 phy-names = "usb"; 701 status = "disabled"; 702 }; 703 704 dwc3: usb@5200000 { 705 compatible = "snps,dwc3"; 706 reg = <0x05200000 0x10000>; 707 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 708 clocks = <&ccu CLK_BUS_XHCI>, 709 <&ccu CLK_BUS_XHCI>, 710 <&rtc 0>; 711 clock-names = "ref", "bus_early", "suspend"; 712 resets = <&ccu RST_BUS_XHCI>; 713 /* 714 * The datasheet of the chip doesn't declare the 715 * peripheral function, and there's no boards known 716 * to have a USB Type-B port routed to the port. 717 * In addition, no one has tested the peripheral 718 * function yet. 719 * So set the dr_mode to "host" in the DTSI file. 720 */ 721 dr_mode = "host"; 722 phys = <&usb3phy>; 723 phy-names = "usb3-phy"; 724 status = "disabled"; 725 }; 726 727 usb3phy: phy@5210000 { 728 compatible = "allwinner,sun50i-h6-usb3-phy"; 729 reg = <0x5210000 0x10000>; 730 clocks = <&ccu CLK_USB_PHY1>; 731 resets = <&ccu RST_USB_PHY1>; 732 #phy-cells = <0>; 733 status = "disabled"; 734 }; 735 736 ehci3: usb@5311000 { 737 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 738 reg = <0x05311000 0x100>; 739 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 740 clocks = <&ccu CLK_BUS_OHCI3>, 741 <&ccu CLK_BUS_EHCI3>, 742 <&ccu CLK_USB_OHCI3>; 743 resets = <&ccu RST_BUS_OHCI3>, 744 <&ccu RST_BUS_EHCI3>; 745 phys = <&usb2phy 3>; 746 phy-names = "usb"; 747 status = "disabled"; 748 }; 749 750 ohci3: usb@5311400 { 751 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 752 reg = <0x05311400 0x100>; 753 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 754 clocks = <&ccu CLK_BUS_OHCI3>, 755 <&ccu CLK_USB_OHCI3>; 756 resets = <&ccu RST_BUS_OHCI3>; 757 phys = <&usb2phy 3>; 758 phy-names = "usb"; 759 status = "disabled"; 760 }; 761 762 hdmi: hdmi@6000000 { 763 compatible = "allwinner,sun50i-h6-dw-hdmi"; 764 reg = <0x06000000 0x10000>; 765 reg-io-width = <1>; 766 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 767 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 768 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 769 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 770 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 771 "hdcp-bus"; 772 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 773 reset-names = "ctrl", "hdcp"; 774 phys = <&hdmi_phy>; 775 phy-names = "phy"; 776 pinctrl-names = "default"; 777 pinctrl-0 = <&hdmi_pins>; 778 status = "disabled"; 779 780 ports { 781 #address-cells = <1>; 782 #size-cells = <0>; 783 784 hdmi_in: port@0 { 785 reg = <0>; 786 787 hdmi_in_tcon_top: endpoint { 788 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 789 }; 790 }; 791 792 hdmi_out: port@1 { 793 reg = <1>; 794 }; 795 }; 796 }; 797 798 hdmi_phy: hdmi-phy@6010000 { 799 compatible = "allwinner,sun50i-h6-hdmi-phy"; 800 reg = <0x06010000 0x10000>; 801 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 802 clock-names = "bus", "mod"; 803 resets = <&ccu RST_BUS_HDMI>; 804 reset-names = "phy"; 805 #phy-cells = <0>; 806 }; 807 808 tcon_top: tcon-top@6510000 { 809 compatible = "allwinner,sun50i-h6-tcon-top"; 810 reg = <0x06510000 0x1000>; 811 clocks = <&ccu CLK_BUS_TCON_TOP>, 812 <&ccu CLK_TCON_TV0>; 813 clock-names = "bus", 814 "tcon-tv0"; 815 clock-output-names = "tcon-top-tv0"; 816 resets = <&ccu RST_BUS_TCON_TOP>; 817 #clock-cells = <1>; 818 819 ports { 820 #address-cells = <1>; 821 #size-cells = <0>; 822 823 tcon_top_mixer0_in: port@0 { 824 #address-cells = <1>; 825 #size-cells = <0>; 826 reg = <0>; 827 828 tcon_top_mixer0_in_mixer0: endpoint@0 { 829 reg = <0>; 830 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 831 }; 832 }; 833 834 tcon_top_mixer0_out: port@1 { 835 #address-cells = <1>; 836 #size-cells = <0>; 837 reg = <1>; 838 839 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 840 reg = <2>; 841 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 842 }; 843 }; 844 845 tcon_top_hdmi_in: port@4 { 846 #address-cells = <1>; 847 #size-cells = <0>; 848 reg = <4>; 849 850 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 851 reg = <0>; 852 remote-endpoint = <&tcon_tv_out_tcon_top>; 853 }; 854 }; 855 856 tcon_top_hdmi_out: port@5 { 857 reg = <5>; 858 859 tcon_top_hdmi_out_hdmi: endpoint { 860 remote-endpoint = <&hdmi_in_tcon_top>; 861 }; 862 }; 863 }; 864 }; 865 866 tcon_tv: lcd-controller@6515000 { 867 compatible = "allwinner,sun50i-h6-tcon-tv", 868 "allwinner,sun8i-r40-tcon-tv"; 869 reg = <0x06515000 0x1000>; 870 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&ccu CLK_BUS_TCON_TV0>, 872 <&tcon_top CLK_TCON_TOP_TV0>; 873 clock-names = "ahb", 874 "tcon-ch1"; 875 resets = <&ccu RST_BUS_TCON_TV0>; 876 reset-names = "lcd"; 877 878 ports { 879 #address-cells = <1>; 880 #size-cells = <0>; 881 882 tcon_tv_in: port@0 { 883 reg = <0>; 884 885 tcon_tv_in_tcon_top_mixer0: endpoint { 886 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 887 }; 888 }; 889 890 tcon_tv_out: port@1 { 891 #address-cells = <1>; 892 #size-cells = <0>; 893 reg = <1>; 894 895 tcon_tv_out_tcon_top: endpoint@1 { 896 reg = <1>; 897 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 898 }; 899 }; 900 }; 901 }; 902 903 rtc: rtc@7000000 { 904 compatible = "allwinner,sun50i-h6-rtc"; 905 reg = <0x07000000 0x400>; 906 interrupt-parent = <&r_intc>; 907 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 909 clock-output-names = "osc32k", "osc32k-out", "iosc"; 910 #clock-cells = <1>; 911 }; 912 913 r_ccu: clock@7010000 { 914 compatible = "allwinner,sun50i-h6-r-ccu"; 915 reg = <0x07010000 0x400>; 916 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 917 <&ccu CLK_PLL_PERIPH0>; 918 clock-names = "hosc", "losc", "iosc", "pll-periph"; 919 #clock-cells = <1>; 920 #reset-cells = <1>; 921 }; 922 923 r_watchdog: watchdog@7020400 { 924 compatible = "allwinner,sun50i-h6-wdt", 925 "allwinner,sun6i-a31-wdt"; 926 reg = <0x07020400 0x20>; 927 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&osc24M>; 929 }; 930 931 r_intc: interrupt-controller@7021000 { 932 compatible = "allwinner,sun50i-h6-r-intc"; 933 interrupt-controller; 934 #interrupt-cells = <3>; 935 reg = <0x07021000 0x400>; 936 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 937 }; 938 939 r_pio: pinctrl@7022000 { 940 compatible = "allwinner,sun50i-h6-r-pinctrl"; 941 reg = <0x07022000 0x400>; 942 interrupt-parent = <&r_intc>; 943 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; 946 clock-names = "apb", "hosc", "losc"; 947 gpio-controller; 948 #gpio-cells = <3>; 949 interrupt-controller; 950 #interrupt-cells = <3>; 951 952 r_i2c_pins: r-i2c-pins { 953 pins = "PL0", "PL1"; 954 function = "s_i2c"; 955 }; 956 957 r_ir_rx_pin: r-ir-rx-pin { 958 pins = "PL9"; 959 function = "s_cir_rx"; 960 }; 961 962 r_rsb_pins: r-rsb-pins { 963 pins = "PL0", "PL1"; 964 function = "s_rsb"; 965 }; 966 }; 967 968 r_ir: ir@7040000 { 969 compatible = "allwinner,sun50i-h6-ir", 970 "allwinner,sun6i-a31-ir"; 971 reg = <0x07040000 0x400>; 972 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&r_ccu CLK_R_APB1_IR>, 974 <&r_ccu CLK_IR>; 975 clock-names = "apb", "ir"; 976 resets = <&r_ccu RST_R_APB1_IR>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&r_ir_rx_pin>; 979 status = "disabled"; 980 }; 981 982 r_i2c: i2c@7081400 { 983 compatible = "allwinner,sun50i-h6-i2c", 984 "allwinner,sun6i-a31-i2c"; 985 reg = <0x07081400 0x400>; 986 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 987 clocks = <&r_ccu CLK_R_APB2_I2C>; 988 resets = <&r_ccu RST_R_APB2_I2C>; 989 pinctrl-names = "default"; 990 pinctrl-0 = <&r_i2c_pins>; 991 status = "disabled"; 992 #address-cells = <1>; 993 #size-cells = <0>; 994 }; 995 996 r_rsb: rsb@7083000 { 997 compatible = "allwinner,sun8i-a23-rsb"; 998 reg = <0x07083000 0x400>; 999 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1000 clocks = <&r_ccu CLK_R_APB2_RSB>; 1001 clock-frequency = <3000000>; 1002 resets = <&r_ccu RST_R_APB2_RSB>; 1003 pinctrl-names = "default"; 1004 pinctrl-0 = <&r_rsb_pins>; 1005 status = "disabled"; 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 }; 1009 1010 ths: thermal-sensor@5070400 { 1011 compatible = "allwinner,sun50i-h6-ths"; 1012 reg = <0x05070400 0x100>; 1013 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&ccu CLK_BUS_THS>; 1015 clock-names = "bus"; 1016 resets = <&ccu RST_BUS_THS>; 1017 nvmem-cells = <&ths_calibration>; 1018 nvmem-cell-names = "calibration"; 1019 #thermal-sensor-cells = <1>; 1020 }; 1021 }; 1022 1023 thermal-zones { 1024 cpu-thermal { 1025 polling-delay-passive = <0>; 1026 polling-delay = <0>; 1027 thermal-sensors = <&ths 0>; 1028 1029 trips { 1030 cpu_alert: cpu-alert { 1031 temperature = <85000>; 1032 hysteresis = <2000>; 1033 type = "passive"; 1034 }; 1035 1036 cpu-crit { 1037 temperature = <100000>; 1038 hysteresis = <0>; 1039 type = "critical"; 1040 }; 1041 }; 1042 1043 cooling-maps { 1044 map0 { 1045 trip = <&cpu_alert>; 1046 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1047 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1048 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1049 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1050 }; 1051 }; 1052 }; 1053 1054 gpu-thermal { 1055 polling-delay-passive = <0>; 1056 polling-delay = <0>; 1057 thermal-sensors = <&ths 1>; 1058 }; 1059 }; 1060}; 1061