1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2// Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/sun50i-h6-ccu.h> 6#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 7#include <dt-bindings/clock/sun8i-de2.h> 8#include <dt-bindings/clock/sun8i-tcon-top.h> 9#include <dt-bindings/reset/sun50i-h6-ccu.h> 10#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 11#include <dt-bindings/reset/sun8i-de2.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53"; 25 device_type = "cpu"; 26 reg = <0>; 27 enable-method = "psci"; 28 }; 29 30 cpu1: cpu@1 { 31 compatible = "arm,cortex-a53"; 32 device_type = "cpu"; 33 reg = <1>; 34 enable-method = "psci"; 35 }; 36 37 cpu2: cpu@2 { 38 compatible = "arm,cortex-a53"; 39 device_type = "cpu"; 40 reg = <2>; 41 enable-method = "psci"; 42 }; 43 44 cpu3: cpu@3 { 45 compatible = "arm,cortex-a53"; 46 device_type = "cpu"; 47 reg = <3>; 48 enable-method = "psci"; 49 }; 50 }; 51 52 de: display-engine { 53 compatible = "allwinner,sun50i-h6-display-engine"; 54 allwinner,pipelines = <&mixer0>; 55 status = "disabled"; 56 }; 57 58 osc24M: osc24M_clk { 59 #clock-cells = <0>; 60 compatible = "fixed-clock"; 61 clock-frequency = <24000000>; 62 clock-output-names = "osc24M"; 63 }; 64 65 ext_osc32k: ext_osc32k_clk { 66 #clock-cells = <0>; 67 compatible = "fixed-clock"; 68 clock-frequency = <32768>; 69 clock-output-names = "ext_osc32k"; 70 }; 71 72 pmu { 73 compatible = "arm,cortex-a53-pmu", 74 "arm,armv8-pmuv3"; 75 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 76 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 77 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 79 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 80 }; 81 82 psci { 83 compatible = "arm,psci-0.2"; 84 method = "smc"; 85 }; 86 87 timer { 88 compatible = "arm,armv8-timer"; 89 interrupts = <GIC_PPI 13 90 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 91 <GIC_PPI 14 92 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 93 <GIC_PPI 11 94 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 95 <GIC_PPI 10 96 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 97 }; 98 99 soc { 100 compatible = "simple-bus"; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 ranges; 104 105 bus@1000000 { 106 compatible = "allwinner,sun50i-h6-de3", 107 "allwinner,sun50i-a64-de2"; 108 reg = <0x1000000 0x400000>; 109 allwinner,sram = <&de2_sram 1>; 110 #address-cells = <1>; 111 #size-cells = <1>; 112 ranges = <0 0x1000000 0x400000>; 113 114 display_clocks: clock@0 { 115 compatible = "allwinner,sun50i-h6-de3-clk"; 116 reg = <0x0 0x10000>; 117 clocks = <&ccu CLK_DE>, 118 <&ccu CLK_BUS_DE>; 119 clock-names = "mod", 120 "bus"; 121 resets = <&ccu RST_BUS_DE>; 122 #clock-cells = <1>; 123 #reset-cells = <1>; 124 }; 125 126 mixer0: mixer@100000 { 127 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 128 reg = <0x100000 0x100000>; 129 clocks = <&display_clocks CLK_BUS_MIXER0>, 130 <&display_clocks CLK_MIXER0>; 131 clock-names = "bus", 132 "mod"; 133 resets = <&display_clocks RST_MIXER0>; 134 135 ports { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 mixer0_out: port@1 { 140 reg = <1>; 141 142 mixer0_out_tcon_top_mixer0: endpoint { 143 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 144 }; 145 }; 146 }; 147 }; 148 }; 149 150 video-codec@1c0e000 { 151 compatible = "allwinner,sun50i-h6-video-engine"; 152 reg = <0x01c0e000 0x2000>; 153 clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>, 154 <&ccu CLK_MBUS_VE>; 155 clock-names = "ahb", "mod", "ram"; 156 resets = <&ccu RST_BUS_VE>; 157 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 158 allwinner,sram = <&ve_sram 1>; 159 }; 160 161 gpu: gpu@1800000 { 162 compatible = "allwinner,sun50i-h6-mali", 163 "arm,mali-t720"; 164 reg = <0x01800000 0x4000>; 165 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 168 interrupt-names = "job", "mmu", "gpu"; 169 clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; 170 clock-names = "core", "bus"; 171 resets = <&ccu RST_BUS_GPU>; 172 status = "disabled"; 173 }; 174 175 crypto: crypto@1904000 { 176 compatible = "allwinner,sun50i-h6-crypto"; 177 reg = <0x01904000 0x1000>; 178 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&ccu CLK_BUS_CE>, <&ccu CLK_CE>, <&ccu CLK_MBUS_CE>; 180 clock-names = "bus", "mod", "ram"; 181 resets = <&ccu RST_BUS_CE>; 182 }; 183 184 syscon: syscon@3000000 { 185 compatible = "allwinner,sun50i-h6-system-control", 186 "allwinner,sun50i-a64-system-control"; 187 reg = <0x03000000 0x1000>; 188 #address-cells = <1>; 189 #size-cells = <1>; 190 ranges; 191 192 sram_c: sram@28000 { 193 compatible = "mmio-sram"; 194 reg = <0x00028000 0x1e000>; 195 #address-cells = <1>; 196 #size-cells = <1>; 197 ranges = <0 0x00028000 0x1e000>; 198 199 de2_sram: sram-section@0 { 200 compatible = "allwinner,sun50i-h6-sram-c", 201 "allwinner,sun50i-a64-sram-c"; 202 reg = <0x0000 0x1e000>; 203 }; 204 }; 205 206 sram_c1: sram@1a00000 { 207 compatible = "mmio-sram"; 208 reg = <0x01a00000 0x200000>; 209 #address-cells = <1>; 210 #size-cells = <1>; 211 ranges = <0 0x01a00000 0x200000>; 212 213 ve_sram: sram-section@0 { 214 compatible = "allwinner,sun50i-h6-sram-c1", 215 "allwinner,sun4i-a10-sram-c1"; 216 reg = <0x000000 0x200000>; 217 }; 218 }; 219 }; 220 221 ccu: clock@3001000 { 222 compatible = "allwinner,sun50i-h6-ccu"; 223 reg = <0x03001000 0x1000>; 224 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>; 225 clock-names = "hosc", "losc", "iosc"; 226 #clock-cells = <1>; 227 #reset-cells = <1>; 228 }; 229 230 dma: dma-controller@3002000 { 231 compatible = "allwinner,sun50i-h6-dma"; 232 reg = <0x03002000 0x1000>; 233 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 234 clocks = <&ccu CLK_BUS_DMA>, <&ccu CLK_MBUS_DMA>; 235 clock-names = "bus", "mbus"; 236 dma-channels = <16>; 237 dma-requests = <46>; 238 resets = <&ccu RST_BUS_DMA>; 239 #dma-cells = <1>; 240 }; 241 242 sid: efuse@3006000 { 243 compatible = "allwinner,sun50i-h6-sid"; 244 reg = <0x03006000 0x400>; 245 #address-cells = <1>; 246 #size-cells = <1>; 247 248 ths_calibration: thermal-sensor-calibration@14 { 249 reg = <0x14 0x8>; 250 }; 251 }; 252 253 watchdog: watchdog@30090a0 { 254 compatible = "allwinner,sun50i-h6-wdt", 255 "allwinner,sun6i-a31-wdt"; 256 reg = <0x030090a0 0x20>; 257 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 258 clocks = <&osc24M>; 259 /* Broken on some H6 boards */ 260 status = "disabled"; 261 }; 262 263 pwm: pwm@300a000 { 264 compatible = "allwinner,sun50i-h6-pwm"; 265 reg = <0x0300a000 0x400>; 266 clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; 267 clock-names = "mod", "bus"; 268 resets = <&ccu RST_BUS_PWM>; 269 #pwm-cells = <3>; 270 status = "disabled"; 271 }; 272 273 pio: pinctrl@300b000 { 274 compatible = "allwinner,sun50i-h6-pinctrl"; 275 reg = <0x0300b000 0x400>; 276 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 280 clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>; 281 clock-names = "apb", "hosc", "losc"; 282 gpio-controller; 283 #gpio-cells = <3>; 284 interrupt-controller; 285 #interrupt-cells = <3>; 286 287 ext_rgmii_pins: rgmii-pins { 288 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 289 "PD5", "PD7", "PD8", "PD9", "PD10", 290 "PD11", "PD12", "PD13", "PD19", "PD20"; 291 function = "emac"; 292 drive-strength = <40>; 293 }; 294 295 hdmi_pins: hdmi-pins { 296 pins = "PH8", "PH9", "PH10"; 297 function = "hdmi"; 298 }; 299 300 i2c0_pins: i2c0-pins { 301 pins = "PD25", "PD26"; 302 function = "i2c0"; 303 }; 304 305 i2c1_pins: i2c1-pins { 306 pins = "PH5", "PH6"; 307 function = "i2c1"; 308 }; 309 310 i2c2_pins: i2c2-pins { 311 pins = "PD23", "PD24"; 312 function = "i2c2"; 313 }; 314 315 mmc0_pins: mmc0-pins { 316 pins = "PF0", "PF1", "PF2", "PF3", 317 "PF4", "PF5"; 318 function = "mmc0"; 319 drive-strength = <30>; 320 bias-pull-up; 321 }; 322 323 /omit-if-no-ref/ 324 mmc1_pins: mmc1-pins { 325 pins = "PG0", "PG1", "PG2", "PG3", 326 "PG4", "PG5"; 327 function = "mmc1"; 328 drive-strength = <30>; 329 bias-pull-up; 330 }; 331 332 mmc2_pins: mmc2-pins { 333 pins = "PC1", "PC4", "PC5", "PC6", 334 "PC7", "PC8", "PC9", "PC10", 335 "PC11", "PC12", "PC13", "PC14"; 336 function = "mmc2"; 337 drive-strength = <30>; 338 bias-pull-up; 339 }; 340 341 spdif_tx_pin: spdif-tx-pin { 342 pins = "PH7"; 343 function = "spdif"; 344 }; 345 346 uart0_ph_pins: uart0-ph-pins { 347 pins = "PH0", "PH1"; 348 function = "uart0"; 349 }; 350 351 uart1_pins: uart1-pins { 352 pins = "PG6", "PG7"; 353 function = "uart1"; 354 }; 355 356 uart1_rts_cts_pins: uart1-rts-cts-pins { 357 pins = "PG8", "PG9"; 358 function = "uart1"; 359 }; 360 }; 361 362 gic: interrupt-controller@3021000 { 363 compatible = "arm,gic-400"; 364 reg = <0x03021000 0x1000>, 365 <0x03022000 0x2000>, 366 <0x03024000 0x2000>, 367 <0x03026000 0x2000>; 368 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 369 interrupt-controller; 370 #interrupt-cells = <3>; 371 }; 372 373 mmc0: mmc@4020000 { 374 compatible = "allwinner,sun50i-h6-mmc", 375 "allwinner,sun50i-a64-mmc"; 376 reg = <0x04020000 0x1000>; 377 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 378 clock-names = "ahb", "mmc"; 379 resets = <&ccu RST_BUS_MMC0>; 380 reset-names = "ahb"; 381 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 382 pinctrl-names = "default"; 383 pinctrl-0 = <&mmc0_pins>; 384 status = "disabled"; 385 #address-cells = <1>; 386 #size-cells = <0>; 387 }; 388 389 mmc1: mmc@4021000 { 390 compatible = "allwinner,sun50i-h6-mmc", 391 "allwinner,sun50i-a64-mmc"; 392 reg = <0x04021000 0x1000>; 393 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 394 clock-names = "ahb", "mmc"; 395 resets = <&ccu RST_BUS_MMC1>; 396 reset-names = "ahb"; 397 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&mmc1_pins>; 400 status = "disabled"; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 }; 404 405 mmc2: mmc@4022000 { 406 compatible = "allwinner,sun50i-h6-emmc", 407 "allwinner,sun50i-a64-emmc"; 408 reg = <0x04022000 0x1000>; 409 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 410 clock-names = "ahb", "mmc"; 411 resets = <&ccu RST_BUS_MMC2>; 412 reset-names = "ahb"; 413 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 414 pinctrl-names = "default"; 415 pinctrl-0 = <&mmc2_pins>; 416 status = "disabled"; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 }; 420 421 uart0: serial@5000000 { 422 compatible = "snps,dw-apb-uart"; 423 reg = <0x05000000 0x400>; 424 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 425 reg-shift = <2>; 426 reg-io-width = <4>; 427 clocks = <&ccu CLK_BUS_UART0>; 428 resets = <&ccu RST_BUS_UART0>; 429 status = "disabled"; 430 }; 431 432 uart1: serial@5000400 { 433 compatible = "snps,dw-apb-uart"; 434 reg = <0x05000400 0x400>; 435 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 436 reg-shift = <2>; 437 reg-io-width = <4>; 438 clocks = <&ccu CLK_BUS_UART1>; 439 resets = <&ccu RST_BUS_UART1>; 440 status = "disabled"; 441 }; 442 443 uart2: serial@5000800 { 444 compatible = "snps,dw-apb-uart"; 445 reg = <0x05000800 0x400>; 446 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 447 reg-shift = <2>; 448 reg-io-width = <4>; 449 clocks = <&ccu CLK_BUS_UART2>; 450 resets = <&ccu RST_BUS_UART2>; 451 status = "disabled"; 452 }; 453 454 uart3: serial@5000c00 { 455 compatible = "snps,dw-apb-uart"; 456 reg = <0x05000c00 0x400>; 457 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 458 reg-shift = <2>; 459 reg-io-width = <4>; 460 clocks = <&ccu CLK_BUS_UART3>; 461 resets = <&ccu RST_BUS_UART3>; 462 status = "disabled"; 463 }; 464 465 i2c0: i2c@5002000 { 466 compatible = "allwinner,sun50i-h6-i2c", 467 "allwinner,sun6i-a31-i2c"; 468 reg = <0x05002000 0x400>; 469 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 470 clocks = <&ccu CLK_BUS_I2C0>; 471 resets = <&ccu RST_BUS_I2C0>; 472 pinctrl-names = "default"; 473 pinctrl-0 = <&i2c0_pins>; 474 status = "disabled"; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 }; 478 479 i2c1: i2c@5002400 { 480 compatible = "allwinner,sun50i-h6-i2c", 481 "allwinner,sun6i-a31-i2c"; 482 reg = <0x05002400 0x400>; 483 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&ccu CLK_BUS_I2C1>; 485 resets = <&ccu RST_BUS_I2C1>; 486 pinctrl-names = "default"; 487 pinctrl-0 = <&i2c1_pins>; 488 status = "disabled"; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 }; 492 493 i2c2: i2c@5002800 { 494 compatible = "allwinner,sun50i-h6-i2c", 495 "allwinner,sun6i-a31-i2c"; 496 reg = <0x05002800 0x400>; 497 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 498 clocks = <&ccu CLK_BUS_I2C2>; 499 resets = <&ccu RST_BUS_I2C2>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&i2c2_pins>; 502 status = "disabled"; 503 #address-cells = <1>; 504 #size-cells = <0>; 505 }; 506 507 emac: ethernet@5020000 { 508 compatible = "allwinner,sun50i-h6-emac", 509 "allwinner,sun50i-a64-emac"; 510 syscon = <&syscon>; 511 reg = <0x05020000 0x10000>; 512 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 513 interrupt-names = "macirq"; 514 resets = <&ccu RST_BUS_EMAC>; 515 reset-names = "stmmaceth"; 516 clocks = <&ccu CLK_BUS_EMAC>; 517 clock-names = "stmmaceth"; 518 status = "disabled"; 519 520 mdio: mdio { 521 compatible = "snps,dwmac-mdio"; 522 #address-cells = <1>; 523 #size-cells = <0>; 524 }; 525 }; 526 527 spdif: spdif@5093000 { 528 #sound-dai-cells = <0>; 529 compatible = "allwinner,sun50i-h6-spdif"; 530 reg = <0x05093000 0x400>; 531 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 532 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>; 533 clock-names = "apb", "spdif"; 534 resets = <&ccu RST_BUS_SPDIF>; 535 dmas = <&dma 2>; 536 dma-names = "tx"; 537 pinctrl-names = "default"; 538 pinctrl-0 = <&spdif_tx_pin>; 539 status = "disabled"; 540 }; 541 542 usb2otg: usb@5100000 { 543 compatible = "allwinner,sun50i-h6-musb", 544 "allwinner,sun8i-a33-musb"; 545 reg = <0x05100000 0x0400>; 546 clocks = <&ccu CLK_BUS_OTG>; 547 resets = <&ccu RST_BUS_OTG>; 548 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 549 interrupt-names = "mc"; 550 phys = <&usb2phy 0>; 551 phy-names = "usb"; 552 extcon = <&usb2phy 0>; 553 status = "disabled"; 554 }; 555 556 usb2phy: phy@5100400 { 557 compatible = "allwinner,sun50i-h6-usb-phy"; 558 reg = <0x05100400 0x24>, 559 <0x05101800 0x4>, 560 <0x05311800 0x4>; 561 reg-names = "phy_ctrl", 562 "pmu0", 563 "pmu3"; 564 clocks = <&ccu CLK_USB_PHY0>, 565 <&ccu CLK_USB_PHY3>; 566 clock-names = "usb0_phy", 567 "usb3_phy"; 568 resets = <&ccu RST_USB_PHY0>, 569 <&ccu RST_USB_PHY3>; 570 reset-names = "usb0_reset", 571 "usb3_reset"; 572 status = "disabled"; 573 #phy-cells = <1>; 574 }; 575 576 ehci0: usb@5101000 { 577 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 578 reg = <0x05101000 0x100>; 579 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&ccu CLK_BUS_OHCI0>, 581 <&ccu CLK_BUS_EHCI0>, 582 <&ccu CLK_USB_OHCI0>; 583 resets = <&ccu RST_BUS_OHCI0>, 584 <&ccu RST_BUS_EHCI0>; 585 status = "disabled"; 586 }; 587 588 ohci0: usb@5101400 { 589 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 590 reg = <0x05101400 0x100>; 591 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&ccu CLK_BUS_OHCI0>, 593 <&ccu CLK_USB_OHCI0>; 594 resets = <&ccu RST_BUS_OHCI0>; 595 status = "disabled"; 596 }; 597 598 dwc3: dwc3@5200000 { 599 compatible = "snps,dwc3"; 600 reg = <0x05200000 0x10000>; 601 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&ccu CLK_BUS_XHCI>, 603 <&ccu CLK_BUS_XHCI>, 604 <&rtc 0>; 605 clock-names = "ref", "bus_early", "suspend"; 606 resets = <&ccu RST_BUS_XHCI>; 607 /* 608 * The datasheet of the chip doesn't declare the 609 * peripheral function, and there's no boards known 610 * to have a USB Type-B port routed to the port. 611 * In addition, no one has tested the peripheral 612 * function yet. 613 * So set the dr_mode to "host" in the DTSI file. 614 */ 615 dr_mode = "host"; 616 phys = <&usb3phy>; 617 phy-names = "usb3-phy"; 618 status = "disabled"; 619 }; 620 621 usb3phy: phy@5210000 { 622 compatible = "allwinner,sun50i-h6-usb3-phy"; 623 reg = <0x5210000 0x10000>; 624 clocks = <&ccu CLK_USB_PHY1>; 625 resets = <&ccu RST_USB_PHY1>; 626 #phy-cells = <0>; 627 status = "disabled"; 628 }; 629 630 ehci3: usb@5311000 { 631 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 632 reg = <0x05311000 0x100>; 633 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 634 clocks = <&ccu CLK_BUS_OHCI3>, 635 <&ccu CLK_BUS_EHCI3>, 636 <&ccu CLK_USB_OHCI3>; 637 resets = <&ccu RST_BUS_OHCI3>, 638 <&ccu RST_BUS_EHCI3>; 639 phys = <&usb2phy 3>; 640 phy-names = "usb"; 641 status = "disabled"; 642 }; 643 644 ohci3: usb@5311400 { 645 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 646 reg = <0x05311400 0x100>; 647 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&ccu CLK_BUS_OHCI3>, 649 <&ccu CLK_USB_OHCI3>; 650 resets = <&ccu RST_BUS_OHCI3>; 651 phys = <&usb2phy 3>; 652 phy-names = "usb"; 653 status = "disabled"; 654 }; 655 656 hdmi: hdmi@6000000 { 657 compatible = "allwinner,sun50i-h6-dw-hdmi"; 658 reg = <0x06000000 0x10000>; 659 reg-io-width = <1>; 660 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 662 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 663 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 664 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 665 "hdcp-bus"; 666 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 667 reset-names = "ctrl", "hdcp"; 668 phys = <&hdmi_phy>; 669 phy-names = "phy"; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&hdmi_pins>; 672 status = "disabled"; 673 674 ports { 675 #address-cells = <1>; 676 #size-cells = <0>; 677 678 hdmi_in: port@0 { 679 reg = <0>; 680 681 hdmi_in_tcon_top: endpoint { 682 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 683 }; 684 }; 685 686 hdmi_out: port@1 { 687 reg = <1>; 688 }; 689 }; 690 }; 691 692 hdmi_phy: hdmi-phy@6010000 { 693 compatible = "allwinner,sun50i-h6-hdmi-phy"; 694 reg = <0x06010000 0x10000>; 695 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 696 clock-names = "bus", "mod"; 697 resets = <&ccu RST_BUS_HDMI>; 698 reset-names = "phy"; 699 #phy-cells = <0>; 700 }; 701 702 tcon_top: tcon-top@6510000 { 703 compatible = "allwinner,sun50i-h6-tcon-top"; 704 reg = <0x06510000 0x1000>; 705 clocks = <&ccu CLK_BUS_TCON_TOP>, 706 <&ccu CLK_TCON_TV0>; 707 clock-names = "bus", 708 "tcon-tv0"; 709 clock-output-names = "tcon-top-tv0"; 710 resets = <&ccu RST_BUS_TCON_TOP>; 711 #clock-cells = <1>; 712 713 ports { 714 #address-cells = <1>; 715 #size-cells = <0>; 716 717 tcon_top_mixer0_in: port@0 { 718 #address-cells = <1>; 719 #size-cells = <0>; 720 reg = <0>; 721 722 tcon_top_mixer0_in_mixer0: endpoint@0 { 723 reg = <0>; 724 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 725 }; 726 }; 727 728 tcon_top_mixer0_out: port@1 { 729 #address-cells = <1>; 730 #size-cells = <0>; 731 reg = <1>; 732 733 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 734 reg = <2>; 735 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 736 }; 737 }; 738 739 tcon_top_hdmi_in: port@4 { 740 #address-cells = <1>; 741 #size-cells = <0>; 742 reg = <4>; 743 744 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 745 reg = <0>; 746 remote-endpoint = <&tcon_tv_out_tcon_top>; 747 }; 748 }; 749 750 tcon_top_hdmi_out: port@5 { 751 reg = <5>; 752 753 tcon_top_hdmi_out_hdmi: endpoint { 754 remote-endpoint = <&hdmi_in_tcon_top>; 755 }; 756 }; 757 }; 758 }; 759 760 tcon_tv: lcd-controller@6515000 { 761 compatible = "allwinner,sun50i-h6-tcon-tv", 762 "allwinner,sun8i-r40-tcon-tv"; 763 reg = <0x06515000 0x1000>; 764 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&ccu CLK_BUS_TCON_TV0>, 766 <&tcon_top CLK_TCON_TOP_TV0>; 767 clock-names = "ahb", 768 "tcon-ch1"; 769 resets = <&ccu RST_BUS_TCON_TV0>; 770 reset-names = "lcd"; 771 772 ports { 773 #address-cells = <1>; 774 #size-cells = <0>; 775 776 tcon_tv_in: port@0 { 777 reg = <0>; 778 779 tcon_tv_in_tcon_top_mixer0: endpoint { 780 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 781 }; 782 }; 783 784 tcon_tv_out: port@1 { 785 #address-cells = <1>; 786 #size-cells = <0>; 787 reg = <1>; 788 789 tcon_tv_out_tcon_top: endpoint@1 { 790 reg = <1>; 791 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 792 }; 793 }; 794 }; 795 }; 796 797 rtc: rtc@7000000 { 798 compatible = "allwinner,sun50i-h6-rtc"; 799 reg = <0x07000000 0x400>; 800 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 801 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 802 clock-output-names = "osc32k", "osc32k-out", "iosc"; 803 clocks = <&ext_osc32k>; 804 #clock-cells = <1>; 805 }; 806 807 r_ccu: clock@7010000 { 808 compatible = "allwinner,sun50i-h6-r-ccu"; 809 reg = <0x07010000 0x400>; 810 clocks = <&osc24M>, <&rtc 0>, <&rtc 2>, 811 <&ccu CLK_PLL_PERIPH0>; 812 clock-names = "hosc", "losc", "iosc", "pll-periph"; 813 #clock-cells = <1>; 814 #reset-cells = <1>; 815 }; 816 817 r_watchdog: watchdog@7020400 { 818 compatible = "allwinner,sun50i-h6-wdt", 819 "allwinner,sun6i-a31-wdt"; 820 reg = <0x07020400 0x20>; 821 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 822 clocks = <&osc24M>; 823 }; 824 825 r_intc: interrupt-controller@7021000 { 826 compatible = "allwinner,sun50i-h6-r-intc", 827 "allwinner,sun6i-a31-r-intc"; 828 interrupt-controller; 829 #interrupt-cells = <2>; 830 reg = <0x07021000 0x400>; 831 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 832 }; 833 834 r_pio: pinctrl@7022000 { 835 compatible = "allwinner,sun50i-h6-r-pinctrl"; 836 reg = <0x07022000 0x400>; 837 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 839 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>; 840 clock-names = "apb", "hosc", "losc"; 841 gpio-controller; 842 #gpio-cells = <3>; 843 interrupt-controller; 844 #interrupt-cells = <3>; 845 846 r_i2c_pins: r-i2c-pins { 847 pins = "PL0", "PL1"; 848 function = "s_i2c"; 849 }; 850 851 r_ir_rx_pin: r-ir-rx-pin { 852 pins = "PL9"; 853 function = "s_cir_rx"; 854 }; 855 }; 856 857 r_ir: ir@7040000 { 858 compatible = "allwinner,sun50i-h6-ir", 859 "allwinner,sun6i-a31-ir"; 860 reg = <0x07040000 0x400>; 861 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 862 clocks = <&r_ccu CLK_R_APB1_IR>, 863 <&r_ccu CLK_IR>; 864 clock-names = "apb", "ir"; 865 resets = <&r_ccu RST_R_APB1_IR>; 866 pinctrl-names = "default"; 867 pinctrl-0 = <&r_ir_rx_pin>; 868 status = "disabled"; 869 }; 870 871 r_i2c: i2c@7081400 { 872 compatible = "allwinner,sun50i-h6-i2c", 873 "allwinner,sun6i-a31-i2c"; 874 reg = <0x07081400 0x400>; 875 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&r_ccu CLK_R_APB2_I2C>; 877 resets = <&r_ccu RST_R_APB2_I2C>; 878 pinctrl-names = "default"; 879 pinctrl-0 = <&r_i2c_pins>; 880 status = "disabled"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 }; 884 885 ths: thermal-sensor@5070400 { 886 compatible = "allwinner,sun50i-h6-ths"; 887 reg = <0x05070400 0x100>; 888 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&ccu CLK_BUS_THS>; 890 clock-names = "bus"; 891 resets = <&ccu RST_BUS_THS>; 892 nvmem-cells = <&ths_calibration>; 893 nvmem-cell-names = "calibration"; 894 #thermal-sensor-cells = <1>; 895 }; 896 }; 897 898 thermal-zones { 899 cpu-thermal { 900 polling-delay-passive = <0>; 901 polling-delay = <0>; 902 thermal-sensors = <&ths 0>; 903 }; 904 905 gpu-thermal { 906 polling-delay-passive = <0>; 907 polling-delay = <0>; 908 thermal-sensors = <&ths 1>; 909 }; 910 }; 911}; 912