1// SPDX-License-Identifier: (GPL-2.0+ or MIT) 2/* 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/sun50i-h6-ccu.h> 8#include <dt-bindings/clock/sun50i-h6-r-ccu.h> 9#include <dt-bindings/clock/sun8i-de2.h> 10#include <dt-bindings/clock/sun8i-tcon-top.h> 11#include <dt-bindings/reset/sun50i-h6-ccu.h> 12#include <dt-bindings/reset/sun50i-h6-r-ccu.h> 13#include <dt-bindings/reset/sun8i-de2.h> 14 15/ { 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a53"; 26 device_type = "cpu"; 27 reg = <0>; 28 enable-method = "psci"; 29 }; 30 31 cpu1: cpu@1 { 32 compatible = "arm,cortex-a53"; 33 device_type = "cpu"; 34 reg = <1>; 35 enable-method = "psci"; 36 }; 37 38 cpu2: cpu@2 { 39 compatible = "arm,cortex-a53"; 40 device_type = "cpu"; 41 reg = <2>; 42 enable-method = "psci"; 43 }; 44 45 cpu3: cpu@3 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 reg = <3>; 49 enable-method = "psci"; 50 }; 51 }; 52 53 de: display-engine { 54 compatible = "allwinner,sun50i-h6-display-engine"; 55 allwinner,pipelines = <&mixer0>; 56 status = "disabled"; 57 }; 58 59 iosc: internal-osc-clk { 60 #clock-cells = <0>; 61 compatible = "fixed-clock"; 62 clock-frequency = <16000000>; 63 clock-accuracy = <300000000>; 64 clock-output-names = "iosc"; 65 }; 66 67 osc24M: osc24M_clk { 68 #clock-cells = <0>; 69 compatible = "fixed-clock"; 70 clock-frequency = <24000000>; 71 clock-output-names = "osc24M"; 72 }; 73 74 osc32k: osc32k_clk { 75 #clock-cells = <0>; 76 compatible = "fixed-clock"; 77 clock-frequency = <32768>; 78 clock-output-names = "osc32k"; 79 }; 80 81 psci { 82 compatible = "arm,psci-0.2"; 83 method = "smc"; 84 }; 85 86 timer { 87 compatible = "arm,armv8-timer"; 88 interrupts = <GIC_PPI 13 89 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 90 <GIC_PPI 14 91 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 92 <GIC_PPI 11 93 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 94 <GIC_PPI 10 95 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 96 }; 97 98 soc { 99 compatible = "simple-bus"; 100 #address-cells = <1>; 101 #size-cells = <1>; 102 ranges; 103 104 display-engine@1000000 { 105 compatible = "allwinner,sun50i-h6-de3", 106 "allwinner,sun50i-a64-de2"; 107 reg = <0x1000000 0x400000>; 108 allwinner,sram = <&de2_sram 1>; 109 #address-cells = <1>; 110 #size-cells = <1>; 111 ranges = <0 0x1000000 0x400000>; 112 113 display_clocks: clock@0 { 114 compatible = "allwinner,sun50i-h6-de3-clk"; 115 reg = <0x0 0x10000>; 116 clocks = <&ccu CLK_DE>, 117 <&ccu CLK_BUS_DE>; 118 clock-names = "mod", 119 "bus"; 120 resets = <&ccu RST_BUS_DE>; 121 #clock-cells = <1>; 122 #reset-cells = <1>; 123 }; 124 125 mixer0: mixer@100000 { 126 compatible = "allwinner,sun50i-h6-de3-mixer-0"; 127 reg = <0x100000 0x100000>; 128 clocks = <&display_clocks CLK_BUS_MIXER0>, 129 <&display_clocks CLK_MIXER0>; 130 clock-names = "bus", 131 "mod"; 132 resets = <&display_clocks RST_MIXER0>; 133 134 ports { 135 #address-cells = <1>; 136 #size-cells = <0>; 137 138 mixer0_out: port@1 { 139 reg = <1>; 140 141 mixer0_out_tcon_top_mixer0: endpoint { 142 remote-endpoint = <&tcon_top_mixer0_in_mixer0>; 143 }; 144 }; 145 }; 146 }; 147 }; 148 149 syscon: syscon@3000000 { 150 compatible = "allwinner,sun50i-h6-system-control", 151 "allwinner,sun50i-a64-system-control"; 152 reg = <0x03000000 0x1000>; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 ranges; 156 157 sram_c: sram@28000 { 158 compatible = "mmio-sram"; 159 reg = <0x00028000 0x1e000>; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 ranges = <0 0x00028000 0x1e000>; 163 164 de2_sram: sram-section@0 { 165 compatible = "allwinner,sun50i-h6-sram-c", 166 "allwinner,sun50i-a64-sram-c"; 167 reg = <0x0000 0x1e000>; 168 }; 169 }; 170 171 sram_c1: sram@1a00000 { 172 compatible = "mmio-sram"; 173 reg = <0x01a00000 0x200000>; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 ranges = <0 0x01a00000 0x200000>; 177 178 ve_sram: sram-section@0 { 179 compatible = "allwinner,sun50i-h6-sram-c1", 180 "allwinner,sun4i-a10-sram-c1"; 181 reg = <0x000000 0x200000>; 182 }; 183 }; 184 }; 185 186 ccu: clock@3001000 { 187 compatible = "allwinner,sun50i-h6-ccu"; 188 reg = <0x03001000 0x1000>; 189 clocks = <&osc24M>, <&osc32k>, <&iosc>; 190 clock-names = "hosc", "losc", "iosc"; 191 #clock-cells = <1>; 192 #reset-cells = <1>; 193 }; 194 195 pio: pinctrl@300b000 { 196 compatible = "allwinner,sun50i-h6-pinctrl"; 197 reg = <0x0300b000 0x400>; 198 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 202 clocks = <&ccu CLK_APB1>, <&osc24M>, <&osc32k>; 203 clock-names = "apb", "hosc", "losc"; 204 gpio-controller; 205 #gpio-cells = <3>; 206 interrupt-controller; 207 #interrupt-cells = <3>; 208 209 ext_rgmii_pins: rgmii_pins { 210 pins = "PD0", "PD1", "PD2", "PD3", "PD4", 211 "PD5", "PD7", "PD8", "PD9", "PD10", 212 "PD11", "PD12", "PD13", "PD19", "PD20"; 213 function = "emac"; 214 drive-strength = <40>; 215 }; 216 217 hdmi_pins: hdmi-pins { 218 pins = "PH8", "PH9", "PH10"; 219 function = "hdmi"; 220 }; 221 222 mmc0_pins: mmc0-pins { 223 pins = "PF0", "PF1", "PF2", "PF3", 224 "PF4", "PF5"; 225 function = "mmc0"; 226 drive-strength = <30>; 227 bias-pull-up; 228 }; 229 230 mmc2_pins: mmc2-pins { 231 pins = "PC1", "PC4", "PC5", "PC6", 232 "PC7", "PC8", "PC9", "PC10", 233 "PC11", "PC12", "PC13", "PC14"; 234 function = "mmc2"; 235 drive-strength = <30>; 236 bias-pull-up; 237 }; 238 239 uart0_ph_pins: uart0-ph { 240 pins = "PH0", "PH1"; 241 function = "uart0"; 242 }; 243 }; 244 245 gic: interrupt-controller@3021000 { 246 compatible = "arm,gic-400"; 247 reg = <0x03021000 0x1000>, 248 <0x03022000 0x2000>, 249 <0x03024000 0x2000>, 250 <0x03026000 0x2000>; 251 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 252 interrupt-controller; 253 #interrupt-cells = <3>; 254 }; 255 256 mmc0: mmc@4020000 { 257 compatible = "allwinner,sun50i-h6-mmc", 258 "allwinner,sun50i-a64-mmc"; 259 reg = <0x04020000 0x1000>; 260 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 261 clock-names = "ahb", "mmc"; 262 resets = <&ccu RST_BUS_MMC0>; 263 reset-names = "ahb"; 264 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 265 status = "disabled"; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 }; 269 270 mmc1: mmc@4021000 { 271 compatible = "allwinner,sun50i-h6-mmc", 272 "allwinner,sun50i-a64-mmc"; 273 reg = <0x04021000 0x1000>; 274 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 275 clock-names = "ahb", "mmc"; 276 resets = <&ccu RST_BUS_MMC1>; 277 reset-names = "ahb"; 278 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 279 status = "disabled"; 280 #address-cells = <1>; 281 #size-cells = <0>; 282 }; 283 284 mmc2: mmc@4022000 { 285 compatible = "allwinner,sun50i-h6-emmc", 286 "allwinner,sun50i-a64-emmc"; 287 reg = <0x04022000 0x1000>; 288 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 289 clock-names = "ahb", "mmc"; 290 resets = <&ccu RST_BUS_MMC2>; 291 reset-names = "ahb"; 292 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 293 status = "disabled"; 294 #address-cells = <1>; 295 #size-cells = <0>; 296 }; 297 298 uart0: serial@5000000 { 299 compatible = "snps,dw-apb-uart"; 300 reg = <0x05000000 0x400>; 301 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 302 reg-shift = <2>; 303 reg-io-width = <4>; 304 clocks = <&ccu CLK_BUS_UART0>; 305 resets = <&ccu RST_BUS_UART0>; 306 status = "disabled"; 307 }; 308 309 uart1: serial@5000400 { 310 compatible = "snps,dw-apb-uart"; 311 reg = <0x05000400 0x400>; 312 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 313 reg-shift = <2>; 314 reg-io-width = <4>; 315 clocks = <&ccu CLK_BUS_UART1>; 316 resets = <&ccu RST_BUS_UART1>; 317 status = "disabled"; 318 }; 319 320 uart2: serial@5000800 { 321 compatible = "snps,dw-apb-uart"; 322 reg = <0x05000800 0x400>; 323 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 324 reg-shift = <2>; 325 reg-io-width = <4>; 326 clocks = <&ccu CLK_BUS_UART2>; 327 resets = <&ccu RST_BUS_UART2>; 328 status = "disabled"; 329 }; 330 331 uart3: serial@5000c00 { 332 compatible = "snps,dw-apb-uart"; 333 reg = <0x05000c00 0x400>; 334 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 335 reg-shift = <2>; 336 reg-io-width = <4>; 337 clocks = <&ccu CLK_BUS_UART3>; 338 resets = <&ccu RST_BUS_UART3>; 339 status = "disabled"; 340 }; 341 342 emac: ethernet@5020000 { 343 compatible = "allwinner,sun50i-h6-emac", 344 "allwinner,sun50i-a64-emac"; 345 syscon = <&syscon>; 346 reg = <0x05020000 0x10000>; 347 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 348 interrupt-names = "macirq"; 349 resets = <&ccu RST_BUS_EMAC>; 350 reset-names = "stmmaceth"; 351 clocks = <&ccu CLK_BUS_EMAC>; 352 clock-names = "stmmaceth"; 353 status = "disabled"; 354 355 mdio: mdio { 356 compatible = "snps,dwmac-mdio"; 357 #address-cells = <1>; 358 #size-cells = <0>; 359 }; 360 }; 361 362 usb2otg: usb@5100000 { 363 compatible = "allwinner,sun50i-h6-musb", 364 "allwinner,sun8i-a33-musb"; 365 reg = <0x05100000 0x0400>; 366 clocks = <&ccu CLK_BUS_OTG>; 367 resets = <&ccu RST_BUS_OTG>; 368 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 369 interrupt-names = "mc"; 370 phys = <&usb2phy 0>; 371 phy-names = "usb"; 372 extcon = <&usb2phy 0>; 373 status = "disabled"; 374 }; 375 376 usb2phy: phy@5100400 { 377 compatible = "allwinner,sun50i-h6-usb-phy"; 378 reg = <0x05100400 0x24>, 379 <0x05101800 0x4>, 380 <0x05311800 0x4>; 381 reg-names = "phy_ctrl", 382 "pmu0", 383 "pmu3"; 384 clocks = <&ccu CLK_USB_PHY0>, 385 <&ccu CLK_USB_PHY3>; 386 clock-names = "usb0_phy", 387 "usb3_phy"; 388 resets = <&ccu RST_USB_PHY0>, 389 <&ccu RST_USB_PHY3>; 390 reset-names = "usb0_reset", 391 "usb3_reset"; 392 status = "disabled"; 393 #phy-cells = <1>; 394 }; 395 396 ehci0: usb@5101000 { 397 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 398 reg = <0x05101000 0x100>; 399 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 400 clocks = <&ccu CLK_BUS_OHCI0>, 401 <&ccu CLK_BUS_EHCI0>, 402 <&ccu CLK_USB_OHCI0>; 403 resets = <&ccu RST_BUS_OHCI0>, 404 <&ccu RST_BUS_EHCI0>; 405 status = "disabled"; 406 }; 407 408 ohci0: usb@5101400 { 409 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 410 reg = <0x05101400 0x100>; 411 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&ccu CLK_BUS_OHCI0>, 413 <&ccu CLK_USB_OHCI0>; 414 resets = <&ccu RST_BUS_OHCI0>; 415 status = "disabled"; 416 }; 417 418 ehci3: usb@5311000 { 419 compatible = "allwinner,sun50i-h6-ehci", "generic-ehci"; 420 reg = <0x05311000 0x100>; 421 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 422 clocks = <&ccu CLK_BUS_OHCI3>, 423 <&ccu CLK_BUS_EHCI3>, 424 <&ccu CLK_USB_OHCI3>; 425 resets = <&ccu RST_BUS_OHCI3>, 426 <&ccu RST_BUS_EHCI3>; 427 phys = <&usb2phy 3>; 428 phy-names = "usb"; 429 status = "disabled"; 430 }; 431 432 ohci3: usb@5311400 { 433 compatible = "allwinner,sun50i-h6-ohci", "generic-ohci"; 434 reg = <0x05311400 0x100>; 435 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 436 clocks = <&ccu CLK_BUS_OHCI3>, 437 <&ccu CLK_USB_OHCI3>; 438 resets = <&ccu RST_BUS_OHCI3>; 439 phys = <&usb2phy 3>; 440 phy-names = "usb"; 441 status = "disabled"; 442 }; 443 444 hdmi: hdmi@6000000 { 445 compatible = "allwinner,sun50i-h6-dw-hdmi"; 446 reg = <0x06000000 0x10000>; 447 reg-io-width = <1>; 448 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>, 450 <&ccu CLK_HDMI>, <&ccu CLK_HDMI_CEC>, 451 <&ccu CLK_HDCP>, <&ccu CLK_BUS_HDCP>; 452 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp", 453 "hdcp-bus"; 454 resets = <&ccu RST_BUS_HDMI_SUB>, <&ccu RST_BUS_HDCP>; 455 reset-names = "ctrl", "hdcp"; 456 phys = <&hdmi_phy>; 457 phy-names = "hdmi-phy"; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&hdmi_pins>; 460 status = "disabled"; 461 462 ports { 463 #address-cells = <1>; 464 #size-cells = <0>; 465 466 hdmi_in: port@0 { 467 reg = <0>; 468 469 hdmi_in_tcon_top: endpoint { 470 remote-endpoint = <&tcon_top_hdmi_out_hdmi>; 471 }; 472 }; 473 474 hdmi_out: port@1 { 475 reg = <1>; 476 }; 477 }; 478 }; 479 480 hdmi_phy: hdmi-phy@6010000 { 481 compatible = "allwinner,sun50i-h6-hdmi-phy"; 482 reg = <0x06010000 0x10000>; 483 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>; 484 clock-names = "bus", "mod"; 485 resets = <&ccu RST_BUS_HDMI>; 486 reset-names = "phy"; 487 #phy-cells = <0>; 488 }; 489 490 tcon_top: tcon-top@6510000 { 491 compatible = "allwinner,sun50i-h6-tcon-top"; 492 reg = <0x06510000 0x1000>; 493 clocks = <&ccu CLK_BUS_TCON_TOP>, 494 <&ccu CLK_TCON_TV0>; 495 clock-names = "bus", 496 "tcon-tv0"; 497 clock-output-names = "tcon-top-tv0"; 498 resets = <&ccu RST_BUS_TCON_TOP>; 499 reset-names = "rst"; 500 #clock-cells = <1>; 501 502 ports { 503 #address-cells = <1>; 504 #size-cells = <0>; 505 506 tcon_top_mixer0_in: port@0 { 507 #address-cells = <1>; 508 #size-cells = <0>; 509 reg = <0>; 510 511 tcon_top_mixer0_in_mixer0: endpoint@0 { 512 reg = <0>; 513 remote-endpoint = <&mixer0_out_tcon_top_mixer0>; 514 }; 515 }; 516 517 tcon_top_mixer0_out: port@1 { 518 #address-cells = <1>; 519 #size-cells = <0>; 520 reg = <1>; 521 522 tcon_top_mixer0_out_tcon_tv: endpoint@2 { 523 reg = <2>; 524 remote-endpoint = <&tcon_tv_in_tcon_top_mixer0>; 525 }; 526 }; 527 528 tcon_top_hdmi_in: port@4 { 529 #address-cells = <1>; 530 #size-cells = <0>; 531 reg = <4>; 532 533 tcon_top_hdmi_in_tcon_tv: endpoint@0 { 534 reg = <0>; 535 remote-endpoint = <&tcon_tv_out_tcon_top>; 536 }; 537 }; 538 539 tcon_top_hdmi_out: port@5 { 540 reg = <5>; 541 542 tcon_top_hdmi_out_hdmi: endpoint { 543 remote-endpoint = <&hdmi_in_tcon_top>; 544 }; 545 }; 546 }; 547 }; 548 549 tcon_tv: lcd-controller@6515000 { 550 compatible = "allwinner,sun50i-h6-tcon-tv", 551 "allwinner,sun8i-r40-tcon-tv"; 552 reg = <0x06515000 0x1000>; 553 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&ccu CLK_BUS_TCON_TV0>, 555 <&tcon_top CLK_TCON_TOP_TV0>; 556 clock-names = "ahb", 557 "tcon-ch1"; 558 resets = <&ccu RST_BUS_TCON_TV0>; 559 reset-names = "lcd"; 560 561 ports { 562 #address-cells = <1>; 563 #size-cells = <0>; 564 565 tcon_tv_in: port@0 { 566 reg = <0>; 567 568 tcon_tv_in_tcon_top_mixer0: endpoint { 569 remote-endpoint = <&tcon_top_mixer0_out_tcon_tv>; 570 }; 571 }; 572 573 tcon_tv_out: port@1 { 574 #address-cells = <1>; 575 #size-cells = <0>; 576 reg = <1>; 577 578 tcon_tv_out_tcon_top: endpoint@1 { 579 reg = <1>; 580 remote-endpoint = <&tcon_top_hdmi_in_tcon_tv>; 581 }; 582 }; 583 }; 584 }; 585 586 r_ccu: clock@7010000 { 587 compatible = "allwinner,sun50i-h6-r-ccu"; 588 reg = <0x07010000 0x400>; 589 clocks = <&osc24M>, <&osc32k>, <&iosc>, 590 <&ccu CLK_PLL_PERIPH0>; 591 clock-names = "hosc", "losc", "iosc", "pll-periph"; 592 #clock-cells = <1>; 593 #reset-cells = <1>; 594 }; 595 596 r_intc: interrupt-controller@7021000 { 597 compatible = "allwinner,sun50i-h6-r-intc", 598 "allwinner,sun6i-a31-r-intc"; 599 interrupt-controller; 600 #interrupt-cells = <2>; 601 reg = <0x07021000 0x400>; 602 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 603 }; 604 605 r_pio: pinctrl@7022000 { 606 compatible = "allwinner,sun50i-h6-r-pinctrl"; 607 reg = <0x07022000 0x400>; 608 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 610 clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&osc32k>; 611 clock-names = "apb", "hosc", "losc"; 612 gpio-controller; 613 #gpio-cells = <3>; 614 interrupt-controller; 615 #interrupt-cells = <3>; 616 617 r_i2c_pins: r-i2c { 618 pins = "PL0", "PL1"; 619 function = "s_i2c"; 620 }; 621 }; 622 623 r_i2c: i2c@7081400 { 624 compatible = "allwinner,sun6i-a31-i2c"; 625 reg = <0x07081400 0x400>; 626 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&r_ccu CLK_R_APB2_I2C>; 628 resets = <&r_ccu RST_R_APB2_I2C>; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&r_i2c_pins>; 631 status = "disabled"; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 }; 635 }; 636}; 637