1/* 2 * Copyright (C) 2016 ARM Ltd. 3 * based on the Allwinner H3 dtsi: 4 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com> 5 * 6 * This file is dual-licensed: you can use it either under the terms 7 * of the GPL or the X11 license, at your option. Note that this dual 8 * licensing only applies to this file, and not this project as a 9 * whole. 10 * 11 * a) This file is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of the 14 * License, or (at your option) any later version. 15 * 16 * This file is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * Or, alternatively, 22 * 23 * b) Permission is hereby granted, free of charge, to any person 24 * obtaining a copy of this software and associated documentation 25 * files (the "Software"), to deal in the Software without 26 * restriction, including without limitation the rights to use, 27 * copy, modify, merge, publish, distribute, sublicense, and/or 28 * sell copies of the Software, and to permit persons to whom the 29 * Software is furnished to do so, subject to the following 30 * conditions: 31 * 32 * The above copyright notice and this permission notice shall be 33 * included in all copies or substantial portions of the Software. 34 * 35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 42 * OTHER DEALINGS IN THE SOFTWARE. 43 */ 44 45#include <dt-bindings/clock/sun50i-a64-ccu.h> 46#include <dt-bindings/interrupt-controller/arm-gic.h> 47#include <dt-bindings/reset/sun50i-a64-ccu.h> 48 49/ { 50 interrupt-parent = <&gic>; 51 #address-cells = <1>; 52 #size-cells = <1>; 53 54 cpus { 55 #address-cells = <1>; 56 #size-cells = <0>; 57 58 cpu0: cpu@0 { 59 compatible = "arm,cortex-a53", "arm,armv8"; 60 device_type = "cpu"; 61 reg = <0>; 62 enable-method = "psci"; 63 }; 64 65 cpu1: cpu@1 { 66 compatible = "arm,cortex-a53", "arm,armv8"; 67 device_type = "cpu"; 68 reg = <1>; 69 enable-method = "psci"; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a53", "arm,armv8"; 74 device_type = "cpu"; 75 reg = <2>; 76 enable-method = "psci"; 77 }; 78 79 cpu3: cpu@3 { 80 compatible = "arm,cortex-a53", "arm,armv8"; 81 device_type = "cpu"; 82 reg = <3>; 83 enable-method = "psci"; 84 }; 85 }; 86 87 osc24M: osc24M_clk { 88 #clock-cells = <0>; 89 compatible = "fixed-clock"; 90 clock-frequency = <24000000>; 91 clock-output-names = "osc24M"; 92 }; 93 94 osc32k: osc32k_clk { 95 #clock-cells = <0>; 96 compatible = "fixed-clock"; 97 clock-frequency = <32768>; 98 clock-output-names = "osc32k"; 99 }; 100 101 psci { 102 compatible = "arm,psci-0.2"; 103 method = "smc"; 104 }; 105 106 timer { 107 compatible = "arm,armv8-timer"; 108 interrupts = <GIC_PPI 13 109 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 110 <GIC_PPI 14 111 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 112 <GIC_PPI 11 113 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 114 <GIC_PPI 10 115 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 116 }; 117 118 soc { 119 compatible = "simple-bus"; 120 #address-cells = <1>; 121 #size-cells = <1>; 122 ranges; 123 124 mmc0: mmc@1c0f000 { 125 compatible = "allwinner,sun50i-a64-mmc"; 126 reg = <0x01c0f000 0x1000>; 127 clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; 128 clock-names = "ahb", "mmc"; 129 resets = <&ccu RST_BUS_MMC0>; 130 reset-names = "ahb"; 131 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 132 max-frequency = <150000000>; 133 status = "disabled"; 134 #address-cells = <1>; 135 #size-cells = <0>; 136 }; 137 138 mmc1: mmc@1c10000 { 139 compatible = "allwinner,sun50i-a64-mmc"; 140 reg = <0x01c10000 0x1000>; 141 clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; 142 clock-names = "ahb", "mmc"; 143 resets = <&ccu RST_BUS_MMC1>; 144 reset-names = "ahb"; 145 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 146 max-frequency = <150000000>; 147 status = "disabled"; 148 #address-cells = <1>; 149 #size-cells = <0>; 150 }; 151 152 mmc2: mmc@1c11000 { 153 compatible = "allwinner,sun50i-a64-emmc"; 154 reg = <0x01c11000 0x1000>; 155 clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; 156 clock-names = "ahb", "mmc"; 157 resets = <&ccu RST_BUS_MMC2>; 158 reset-names = "ahb"; 159 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 160 max-frequency = <200000000>; 161 status = "disabled"; 162 #address-cells = <1>; 163 #size-cells = <0>; 164 }; 165 166 usb_otg: usb@01c19000 { 167 compatible = "allwinner,sun8i-a33-musb"; 168 reg = <0x01c19000 0x0400>; 169 clocks = <&ccu CLK_BUS_OTG>; 170 resets = <&ccu RST_BUS_OTG>; 171 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 172 interrupt-names = "mc"; 173 phys = <&usbphy 0>; 174 phy-names = "usb"; 175 extcon = <&usbphy 0>; 176 status = "disabled"; 177 }; 178 179 usbphy: phy@01c19400 { 180 compatible = "allwinner,sun50i-a64-usb-phy"; 181 reg = <0x01c19400 0x14>, 182 <0x01c1b800 0x4>; 183 reg-names = "phy_ctrl", 184 "pmu1"; 185 clocks = <&ccu CLK_USB_PHY0>, 186 <&ccu CLK_USB_PHY1>; 187 clock-names = "usb0_phy", 188 "usb1_phy"; 189 resets = <&ccu RST_USB_PHY0>, 190 <&ccu RST_USB_PHY1>; 191 reset-names = "usb0_reset", 192 "usb1_reset"; 193 status = "disabled"; 194 #phy-cells = <1>; 195 }; 196 197 ehci1: usb@01c1b000 { 198 compatible = "allwinner,sun50i-a64-ehci", "generic-ehci"; 199 reg = <0x01c1b000 0x100>; 200 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&ccu CLK_BUS_OHCI1>, 202 <&ccu CLK_BUS_EHCI1>, 203 <&ccu CLK_USB_OHCI1>; 204 resets = <&ccu RST_BUS_OHCI1>, 205 <&ccu RST_BUS_EHCI1>; 206 phys = <&usbphy 1>; 207 phy-names = "usb"; 208 status = "disabled"; 209 }; 210 211 ohci1: usb@01c1b400 { 212 compatible = "allwinner,sun50i-a64-ohci", "generic-ohci"; 213 reg = <0x01c1b400 0x100>; 214 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&ccu CLK_BUS_OHCI1>, 216 <&ccu CLK_USB_OHCI1>; 217 resets = <&ccu RST_BUS_OHCI1>; 218 phys = <&usbphy 1>; 219 phy-names = "usb"; 220 status = "disabled"; 221 }; 222 223 ccu: clock@01c20000 { 224 compatible = "allwinner,sun50i-a64-ccu"; 225 reg = <0x01c20000 0x400>; 226 clocks = <&osc24M>, <&osc32k>; 227 clock-names = "hosc", "losc"; 228 #clock-cells = <1>; 229 #reset-cells = <1>; 230 }; 231 232 pio: pinctrl@1c20800 { 233 compatible = "allwinner,sun50i-a64-pinctrl"; 234 reg = <0x01c20800 0x400>; 235 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 238 clocks = <&ccu 58>; 239 gpio-controller; 240 #gpio-cells = <3>; 241 interrupt-controller; 242 #interrupt-cells = <3>; 243 244 i2c1_pins: i2c1_pins { 245 pins = "PH2", "PH3"; 246 function = "i2c1"; 247 }; 248 249 mmc0_pins: mmc0-pins { 250 pins = "PF0", "PF1", "PF2", "PF3", 251 "PF4", "PF5"; 252 function = "mmc0"; 253 drive-strength = <30>; 254 bias-pull-up; 255 }; 256 257 mmc1_pins: mmc1-pins { 258 pins = "PG0", "PG1", "PG2", "PG3", 259 "PG4", "PG5"; 260 function = "mmc1"; 261 drive-strength = <30>; 262 bias-pull-up; 263 }; 264 265 mmc2_pins: mmc2-pins { 266 pins = "PC1", "PC5", "PC6", "PC8", "PC9", 267 "PC10","PC11", "PC12", "PC13", 268 "PC14", "PC15", "PC16"; 269 function = "mmc2"; 270 drive-strength = <30>; 271 bias-pull-up; 272 }; 273 274 uart0_pins_a: uart0@0 { 275 pins = "PB8", "PB9"; 276 function = "uart0"; 277 }; 278 279 uart1_pins: uart1_pins { 280 pins = "PG6", "PG7"; 281 function = "uart1"; 282 }; 283 284 uart1_rts_cts_pins: uart1_rts_cts_pins { 285 pins = "PG8", "PG9"; 286 function = "uart1"; 287 }; 288 }; 289 290 uart0: serial@1c28000 { 291 compatible = "snps,dw-apb-uart"; 292 reg = <0x01c28000 0x400>; 293 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 294 reg-shift = <2>; 295 reg-io-width = <4>; 296 clocks = <&ccu 67>; 297 resets = <&ccu 46>; 298 status = "disabled"; 299 }; 300 301 uart1: serial@1c28400 { 302 compatible = "snps,dw-apb-uart"; 303 reg = <0x01c28400 0x400>; 304 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 305 reg-shift = <2>; 306 reg-io-width = <4>; 307 clocks = <&ccu 68>; 308 resets = <&ccu 47>; 309 status = "disabled"; 310 }; 311 312 uart2: serial@1c28800 { 313 compatible = "snps,dw-apb-uart"; 314 reg = <0x01c28800 0x400>; 315 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 316 reg-shift = <2>; 317 reg-io-width = <4>; 318 clocks = <&ccu 69>; 319 resets = <&ccu 48>; 320 status = "disabled"; 321 }; 322 323 uart3: serial@1c28c00 { 324 compatible = "snps,dw-apb-uart"; 325 reg = <0x01c28c00 0x400>; 326 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 327 reg-shift = <2>; 328 reg-io-width = <4>; 329 clocks = <&ccu 70>; 330 resets = <&ccu 49>; 331 status = "disabled"; 332 }; 333 334 uart4: serial@1c29000 { 335 compatible = "snps,dw-apb-uart"; 336 reg = <0x01c29000 0x400>; 337 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 338 reg-shift = <2>; 339 reg-io-width = <4>; 340 clocks = <&ccu 71>; 341 resets = <&ccu 50>; 342 status = "disabled"; 343 }; 344 345 i2c0: i2c@1c2ac00 { 346 compatible = "allwinner,sun6i-a31-i2c"; 347 reg = <0x01c2ac00 0x400>; 348 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&ccu 63>; 350 resets = <&ccu 42>; 351 status = "disabled"; 352 #address-cells = <1>; 353 #size-cells = <0>; 354 }; 355 356 i2c1: i2c@1c2b000 { 357 compatible = "allwinner,sun6i-a31-i2c"; 358 reg = <0x01c2b000 0x400>; 359 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 360 clocks = <&ccu 64>; 361 resets = <&ccu 43>; 362 status = "disabled"; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 }; 366 367 i2c2: i2c@1c2b400 { 368 compatible = "allwinner,sun6i-a31-i2c"; 369 reg = <0x01c2b400 0x400>; 370 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&ccu 65>; 372 resets = <&ccu 44>; 373 status = "disabled"; 374 #address-cells = <1>; 375 #size-cells = <0>; 376 }; 377 378 gic: interrupt-controller@1c81000 { 379 compatible = "arm,gic-400"; 380 reg = <0x01c81000 0x1000>, 381 <0x01c82000 0x2000>, 382 <0x01c84000 0x2000>, 383 <0x01c86000 0x2000>; 384 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 385 interrupt-controller; 386 #interrupt-cells = <3>; 387 }; 388 389 rtc: rtc@1f00000 { 390 compatible = "allwinner,sun6i-a31-rtc"; 391 reg = <0x01f00000 0x54>; 392 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 394 }; 395 }; 396}; 397