1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Andreas Färber 4 */ 5 6#include <dt-bindings/clock/actions,s900-cmu.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8 9/ { 10 compatible = "actions,s900"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cpus { 16 #address-cells = <2>; 17 #size-cells = <0>; 18 19 cpu0: cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a53", "arm,armv8"; 22 reg = <0x0 0x0>; 23 enable-method = "psci"; 24 }; 25 26 cpu1: cpu@1 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a53", "arm,armv8"; 29 reg = <0x0 0x1>; 30 enable-method = "psci"; 31 }; 32 33 cpu2: cpu@2 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a53", "arm,armv8"; 36 reg = <0x0 0x2>; 37 enable-method = "psci"; 38 }; 39 40 cpu3: cpu@3 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 reg = <0x0 0x3>; 44 enable-method = "psci"; 45 }; 46 }; 47 48 reserved-memory { 49 #address-cells = <2>; 50 #size-cells = <2>; 51 ranges; 52 53 secmon@1f000000 { 54 reg = <0x0 0x1f000000 0x0 0x1000000>; 55 no-map; 56 }; 57 }; 58 59 psci { 60 compatible = "arm,psci-0.2"; 61 method = "smc"; 62 }; 63 64 arm-pmu { 65 compatible = "arm,cortex-a53-pmu"; 66 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 70 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 71 }; 72 73 timer { 74 compatible = "arm,armv8-timer"; 75 interrupts = <GIC_PPI 13 76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 77 <GIC_PPI 14 78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 79 <GIC_PPI 11 80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 81 <GIC_PPI 10 82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 83 }; 84 85 hosc: hosc { 86 compatible = "fixed-clock"; 87 clock-frequency = <24000000>; 88 #clock-cells = <0>; 89 }; 90 91 losc: losc { 92 compatible = "fixed-clock"; 93 clock-frequency = <32768>; 94 #clock-cells = <0>; 95 }; 96 97 diff24M: diff24M { 98 compatible = "fixed-clock"; 99 clock-frequency = <24000000>; 100 #clock-cells = <0>; 101 }; 102 103 soc { 104 compatible = "simple-bus"; 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 109 gic: interrupt-controller@e00f1000 { 110 compatible = "arm,gic-400"; 111 reg = <0x0 0xe00f1000 0x0 0x1000>, 112 <0x0 0xe00f2000 0x0 0x2000>, 113 <0x0 0xe00f4000 0x0 0x2000>, 114 <0x0 0xe00f6000 0x0 0x2000>; 115 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 116 interrupt-controller; 117 #interrupt-cells = <3>; 118 }; 119 120 uart0: serial@e0120000 { 121 compatible = "actions,s900-uart", "actions,owl-uart"; 122 reg = <0x0 0xe0120000 0x0 0x2000>; 123 clocks = <&cmu CLK_UART0>; 124 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 125 status = "disabled"; 126 }; 127 128 uart1: serial@e0122000 { 129 compatible = "actions,s900-uart", "actions,owl-uart"; 130 reg = <0x0 0xe0122000 0x0 0x2000>; 131 clocks = <&cmu CLK_UART1>; 132 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 133 status = "disabled"; 134 }; 135 136 uart2: serial@e0124000 { 137 compatible = "actions,s900-uart", "actions,owl-uart"; 138 reg = <0x0 0xe0124000 0x0 0x2000>; 139 clocks = <&cmu CLK_UART2>; 140 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 141 status = "disabled"; 142 }; 143 144 uart3: serial@e0126000 { 145 compatible = "actions,s900-uart", "actions,owl-uart"; 146 reg = <0x0 0xe0126000 0x0 0x2000>; 147 clocks = <&cmu CLK_UART3>; 148 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 149 status = "disabled"; 150 }; 151 152 uart4: serial@e0128000 { 153 compatible = "actions,s900-uart", "actions,owl-uart"; 154 reg = <0x0 0xe0128000 0x0 0x2000>; 155 clocks = <&cmu CLK_UART4>; 156 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 157 status = "disabled"; 158 }; 159 160 uart5: serial@e012a000 { 161 compatible = "actions,s900-uart", "actions,owl-uart"; 162 reg = <0x0 0xe012a000 0x0 0x2000>; 163 clocks = <&cmu CLK_UART5>; 164 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 165 status = "disabled"; 166 }; 167 168 uart6: serial@e012c000 { 169 compatible = "actions,s900-uart", "actions,owl-uart"; 170 reg = <0x0 0xe012c000 0x0 0x2000>; 171 clocks = <&cmu CLK_UART6>; 172 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 173 status = "disabled"; 174 }; 175 176 sps: power-controller@e012e000 { 177 compatible = "actions,s900-sps"; 178 reg = <0x0 0xe012e000 0x0 0x2000>; 179 #power-domain-cells = <1>; 180 }; 181 182 cmu: clock-controller@e0160000 { 183 compatible = "actions,s900-cmu"; 184 reg = <0x0 0xe0160000 0x0 0x1000>; 185 clocks = <&hosc>, <&losc>; 186 #clock-cells = <1>; 187 }; 188 189 i2c0: i2c@e0170000 { 190 compatible = "actions,s900-i2c"; 191 reg = <0 0xe0170000 0 0x1000>; 192 clocks = <&cmu CLK_I2C0>; 193 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 194 #address-cells = <1>; 195 #size-cells = <0>; 196 status = "disabled"; 197 }; 198 199 i2c1: i2c@e0172000 { 200 compatible = "actions,s900-i2c"; 201 reg = <0 0xe0172000 0 0x1000>; 202 clocks = <&cmu CLK_I2C1>; 203 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 204 #address-cells = <1>; 205 #size-cells = <0>; 206 status = "disabled"; 207 }; 208 209 i2c2: i2c@e0174000 { 210 compatible = "actions,s900-i2c"; 211 reg = <0 0xe0174000 0 0x1000>; 212 clocks = <&cmu CLK_I2C2>; 213 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 status = "disabled"; 217 }; 218 219 i2c3: i2c@e0176000 { 220 compatible = "actions,s900-i2c"; 221 reg = <0 0xe0176000 0 0x1000>; 222 clocks = <&cmu CLK_I2C3>; 223 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 224 #address-cells = <1>; 225 #size-cells = <0>; 226 status = "disabled"; 227 }; 228 229 i2c4: i2c@e0178000 { 230 compatible = "actions,s900-i2c"; 231 reg = <0 0xe0178000 0 0x1000>; 232 clocks = <&cmu CLK_I2C4>; 233 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 234 #address-cells = <1>; 235 #size-cells = <0>; 236 status = "disabled"; 237 }; 238 239 i2c5: i2c@e017a000 { 240 compatible = "actions,s900-i2c"; 241 reg = <0 0xe017a000 0 0x1000>; 242 clocks = <&cmu CLK_I2C5>; 243 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 244 #address-cells = <1>; 245 #size-cells = <0>; 246 status = "disabled"; 247 }; 248 249 pinctrl: pinctrl@e01b0000 { 250 compatible = "actions,s900-pinctrl"; 251 reg = <0x0 0xe01b0000 0x0 0x1000>; 252 clocks = <&cmu CLK_GPIO>; 253 gpio-controller; 254 gpio-ranges = <&pinctrl 0 0 146>; 255 #gpio-cells = <2>; 256 }; 257 258 timer: timer@e0228000 { 259 compatible = "actions,s900-timer"; 260 reg = <0x0 0xe0228000 0x0 0x8000>; 261 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 262 interrupt-names = "timer1"; 263 }; 264 265 dma: dma-controller@e0260000 { 266 compatible = "actions,s900-dma"; 267 reg = <0x0 0xe0260000 0x0 0x1000>; 268 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 269 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 270 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 271 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 272 #dma-cells = <1>; 273 dma-channels = <12>; 274 dma-requests = <46>; 275 clocks = <&cmu CLK_DMAC>; 276 }; 277 }; 278}; 279