xref: /openbmc/linux/arch/arm64/boot/dts/actions/s700.dtsi (revision 9fb29c73)
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Andreas Färber
4 */
5
6#include <dt-bindings/clock/actions,s700-cmu.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10	compatible = "actions,s700";
11	interrupt-parent = <&gic>;
12	#address-cells = <2>;
13	#size-cells = <2>;
14
15	cpus {
16		#address-cells = <2>;
17		#size-cells = <0>;
18
19		cpu0: cpu@0 {
20			device_type = "cpu";
21			compatible = "arm,cortex-a53", "arm,armv8";
22			reg = <0x0 0x0>;
23			enable-method = "psci";
24		};
25
26		cpu1: cpu@1 {
27			device_type = "cpu";
28			compatible = "arm,cortex-a53", "arm,armv8";
29			reg = <0x0 0x1>;
30			enable-method = "psci";
31		};
32
33		cpu2: cpu@2 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53", "arm,armv8";
36			reg = <0x0 0x2>;
37			enable-method = "psci";
38		};
39
40		cpu3: cpu@3 {
41			device_type = "cpu";
42			compatible = "arm,cortex-a53", "arm,armv8";
43			reg = <0x0 0x3>;
44			enable-method = "psci";
45		};
46	};
47
48	reserved-memory {
49		#address-cells = <2>;
50		#size-cells = <2>;
51		ranges;
52
53		secmon@1f000000 {
54			reg = <0x0 0x1f000000 0x0 0x1000000>;
55			no-map;
56		};
57	};
58
59	psci {
60		compatible = "arm,psci-0.2";
61		method = "smc";
62	};
63
64	arm-pmu {
65		compatible = "arm,cortex-a53-pmu";
66		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
67		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
68		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
69		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
70		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
71	};
72
73	timer {
74		compatible = "arm,armv8-timer";
75		interrupts = <GIC_PPI 13
76			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77			     <GIC_PPI 14
78			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
79			     <GIC_PPI 11
80			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
81			     <GIC_PPI 10
82			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
83	};
84
85	hosc: hosc {
86		compatible = "fixed-clock";
87		clock-frequency = <24000000>;
88		#clock-cells = <0>;
89	};
90
91	losc: losc {
92		compatible = "fixed-clock";
93		clock-frequency = <32768>;
94		#clock-cells = <0>;
95	};
96
97	soc {
98		compatible = "simple-bus";
99		#address-cells = <2>;
100		#size-cells = <2>;
101		ranges;
102
103		gic: interrupt-controller@e00f1000 {
104			compatible = "arm,gic-400";
105			reg = <0x0 0xe00f1000 0x0 0x1000>,
106			      <0x0 0xe00f2000 0x0 0x2000>,
107			      <0x0 0xe00f4000 0x0 0x2000>,
108			      <0x0 0xe00f6000 0x0 0x2000>;
109			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
110			interrupt-controller;
111			#interrupt-cells = <3>;
112		};
113
114		uart0: serial@e0120000 {
115			compatible = "actions,s900-uart", "actions,owl-uart";
116			reg = <0x0 0xe0120000 0x0 0x2000>;
117			clocks = <&cmu CLK_UART0>;
118			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
119			status = "disabled";
120		};
121
122		uart1: serial@e0122000 {
123			compatible = "actions,s900-uart", "actions,owl-uart";
124			reg = <0x0 0xe0122000 0x0 0x2000>;
125			clocks = <&cmu CLK_UART1>;
126			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
127			status = "disabled";
128		};
129
130		uart2: serial@e0124000 {
131			compatible = "actions,s900-uart", "actions,owl-uart";
132			reg = <0x0 0xe0124000 0x0 0x2000>;
133			clocks = <&cmu CLK_UART2>;
134			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
135			status = "disabled";
136		};
137
138		uart3: serial@e0126000 {
139			compatible = "actions,s900-uart", "actions,owl-uart";
140			reg = <0x0 0xe0126000 0x0 0x2000>;
141			clocks = <&cmu CLK_UART3>;
142			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
143			status = "disabled";
144		};
145
146		uart4: serial@e0128000 {
147			compatible = "actions,s900-uart", "actions,owl-uart";
148			reg = <0x0 0xe0128000 0x0 0x2000>;
149			clocks = <&cmu CLK_UART4>;
150			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
151			status = "disabled";
152		};
153
154		uart5: serial@e012a000 {
155			compatible = "actions,s900-uart", "actions,owl-uart";
156			reg = <0x0 0xe012a000 0x0 0x2000>;
157			clocks = <&cmu CLK_UART5>;
158			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
159			status = "disabled";
160		};
161
162		uart6: serial@e012c000 {
163			compatible = "actions,s900-uart", "actions,owl-uart";
164			reg = <0x0 0xe012c000 0x0 0x2000>;
165			clocks = <&cmu CLK_UART6>;
166			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
167			status = "disabled";
168		};
169
170		cmu: clock-controller@e0168000 {
171			compatible = "actions,s700-cmu";
172			reg = <0x0 0xe0168000 0x0 0x1000>;
173			clocks = <&hosc>, <&losc>;
174			#clock-cells = <1>;
175		};
176
177		sps: power-controller@e01b0100 {
178			compatible = "actions,s700-sps";
179			reg = <0x0 0xe01b0100 0x0 0x100>;
180			#power-domain-cells = <1>;
181		};
182
183		timer: timer@e024c000 {
184			compatible = "actions,s700-timer";
185			reg = <0x0 0xe024c000 0x0 0x4000>;
186			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
187			interrupt-names = "timer1";
188		};
189	};
190};
191