1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2017 Andreas Färber 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7 8/ { 9 compatible = "actions,s700"; 10 interrupt-parent = <&gic>; 11 #address-cells = <2>; 12 #size-cells = <2>; 13 14 cpus { 15 #address-cells = <2>; 16 #size-cells = <0>; 17 18 cpu0: cpu@0 { 19 device_type = "cpu"; 20 compatible = "arm,cortex-a53", "arm,armv8"; 21 reg = <0x0 0x0>; 22 enable-method = "psci"; 23 }; 24 25 cpu1: cpu@1 { 26 device_type = "cpu"; 27 compatible = "arm,cortex-a53", "arm,armv8"; 28 reg = <0x0 0x1>; 29 enable-method = "psci"; 30 }; 31 32 cpu2: cpu@2 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a53", "arm,armv8"; 35 reg = <0x0 0x2>; 36 enable-method = "psci"; 37 }; 38 39 cpu3: cpu@3 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53", "arm,armv8"; 42 reg = <0x0 0x3>; 43 enable-method = "psci"; 44 }; 45 }; 46 47 reserved-memory { 48 #address-cells = <2>; 49 #size-cells = <2>; 50 ranges; 51 52 secmon@1f000000 { 53 reg = <0x0 0x1f000000 0x0 0x1000000>; 54 no-map; 55 }; 56 }; 57 58 psci { 59 compatible = "arm,psci-0.2"; 60 method = "smc"; 61 }; 62 63 arm-pmu { 64 compatible = "arm,cortex-a53-pmu"; 65 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 66 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 67 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 69 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 70 }; 71 72 timer { 73 compatible = "arm,armv8-timer"; 74 interrupts = <GIC_PPI 13 75 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 76 <GIC_PPI 14 77 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 78 <GIC_PPI 11 79 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 80 <GIC_PPI 10 81 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 82 }; 83 84 hosc: hosc { 85 compatible = "fixed-clock"; 86 clock-frequency = <24000000>; 87 #clock-cells = <0>; 88 }; 89 90 soc { 91 compatible = "simple-bus"; 92 #address-cells = <2>; 93 #size-cells = <2>; 94 ranges; 95 96 gic: interrupt-controller@e00f1000 { 97 compatible = "arm,gic-400"; 98 reg = <0x0 0xe00f1000 0x0 0x1000>, 99 <0x0 0xe00f2000 0x0 0x2000>, 100 <0x0 0xe00f4000 0x0 0x2000>, 101 <0x0 0xe00f6000 0x0 0x2000>; 102 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 103 interrupt-controller; 104 #interrupt-cells = <3>; 105 }; 106 107 uart0: serial@e0120000 { 108 compatible = "actions,s900-uart", "actions,owl-uart"; 109 reg = <0x0 0xe0120000 0x0 0x2000>; 110 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 111 status = "disabled"; 112 }; 113 114 uart1: serial@e0122000 { 115 compatible = "actions,s900-uart", "actions,owl-uart"; 116 reg = <0x0 0xe0122000 0x0 0x2000>; 117 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 118 status = "disabled"; 119 }; 120 121 uart2: serial@e0124000 { 122 compatible = "actions,s900-uart", "actions,owl-uart"; 123 reg = <0x0 0xe0124000 0x0 0x2000>; 124 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 125 status = "disabled"; 126 }; 127 128 uart3: serial@e0126000 { 129 compatible = "actions,s900-uart", "actions,owl-uart"; 130 reg = <0x0 0xe0126000 0x0 0x2000>; 131 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 132 status = "disabled"; 133 }; 134 135 uart4: serial@e0128000 { 136 compatible = "actions,s900-uart", "actions,owl-uart"; 137 reg = <0x0 0xe0128000 0x0 0x2000>; 138 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 139 status = "disabled"; 140 }; 141 142 uart5: serial@e012a000 { 143 compatible = "actions,s900-uart", "actions,owl-uart"; 144 reg = <0x0 0xe012a000 0x0 0x2000>; 145 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 146 status = "disabled"; 147 }; 148 149 uart6: serial@e012c000 { 150 compatible = "actions,s900-uart", "actions,owl-uart"; 151 reg = <0x0 0xe012c000 0x0 0x2000>; 152 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 153 status = "disabled"; 154 }; 155 156 sps: power-controller@e01b0100 { 157 compatible = "actions,s700-sps"; 158 reg = <0x0 0xe01b0100 0x0 0x100>; 159 #power-domain-cells = <1>; 160 }; 161 162 timer: timer@e024c000 { 163 compatible = "actions,s700-timer"; 164 reg = <0x0 0xe024c000 0x0 0x4000>; 165 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 166 interrupt-names = "timer1"; 167 }; 168 }; 169}; 170